KR20160141355A - Methods of manufacturing semiconductor substrates and substrates for semiconductor growth - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor substrate and a substrate for semiconductor growth. According to the present invention, the method comprises the following steps of: forming a buffer layer on a growth substrate; forming, on a buffer layer, a plurality of openings penetrating the buffer layer and disposed spaced apart from each other; forming, on the growth substrate, a plurality of cavities disposed under the plurality of openings; forming a semiconductor layer growing from the buffer layer, filling the plurality of openings, and extending in an upper direction of the buffer layer; and the buffer layer and the semiconductor layer being separated from the growth substrate by stress acting on the plurality of cavities. On a boundary of the growth substrate and the buffer layer, the diameter of the plurality of openings is less than the diameter of the plurality of cavities.

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a semiconductor substrate,

The present invention relates to a method of manufacturing a semiconductor substrate and a substrate for semiconductor growth.

BACKGROUND ART Semiconductor light emitting devices are known as next generation light sources having advantages such as long lifetime, low power consumption, quick response speed, and environmental friendliness, and they are attracting attention as important light sources in various products such as backlight of illumination devices and display devices. In particular, Group III nitride-based light-emitting devices such as GaN, AlGaN, InGaN, and InAlGaN play an important role as semiconductor light emitting devices that output blue or ultraviolet light.

As the substrate used for manufacturing the semiconductor light emitting device, a sapphire substrate, a silicon (Si) substrate, a GaN substrate, or the like is used. In particular, when a nitride-based light-emitting device is manufactured using a GaN substrate, defects in the light-emitting device can be significantly reduced. In the production of such a GaN substrate, there is a demand for a technique capable of manufacturing a large area without increasing the manufacturing cost by using a simpler process.

One of the technical problems to be solved by the technical idea of the present invention is to provide a method of manufacturing a semiconductor substrate which is easy to process and a substrate for semiconductor growth.

A method of manufacturing a semiconductor substrate according to an embodiment of the present invention includes the steps of forming a buffer layer on a growth substrate, forming a plurality of openings spaced apart from each other through the buffer layer in the buffer layer, Forming a plurality of cavities disposed below the plurality of openings, growing a semiconductor layer extending from the buffer layer and extending to the top of the buffer layer to fill the plurality of openings, Wherein a diameter of the plurality of openings is smaller than a diameter of the plurality of cavities at a boundary between the growth substrate and the buffer layer by a stress acting on the buffer layer and the semiconductor layer, have.

For example, in the plurality of cavities, the buffer layer may protrude from the growth substrate to form an undercut region.

In one example, the plurality of cavities may be covered with the semiconductor layer to form closed regions between the semiconductor layer and the growth substrate.

For example, in the separating step, a crack may occur in the lateral direction along the boundary between the buffer layer and the growth substrate from the plurality of cavities.

For example, the plurality of openings may be formed by a dry etching process, and the plurality of cavities may be formed by a wet etching process.

In one example, the plurality of openings and the plurality of cavities may be formed in a single process.

For example, the plurality of cavities may be defined by the surfaces along the crystal faces of the growth substrate.

In one example, each of the plurality of cavities may be defined by seven or more faces.

For example, one surface of the growth substrate connected to the buffer layer in the plurality of cavities may be a negative inclined surface.

For example, the plurality of cavities may be formed only in a part of the growth substrate.

In one embodiment, in the separating step, the semiconductor layer may start to separate from the partial region where the plurality of cavities are formed.

In one example, by controlling the size and density of the plurality of openings, it is possible to control the thickness of the semiconductor layer grown before being separated from the growth substrate.

For example, the area of the plurality of openings may range from about 20% to 90% of the area of the buffer layer.

As an example, the ratio of the diameter of the plurality of openings to the distance between the plurality of openings may be in a range of 0.65 to 18.

For example, the growth substrate and the buffer layer may have different thermal expansion coefficients.

For example, the growth substrate may be a silicon (Si) substrate, and the buffer layer and the semiconductor layer may be made of gallium nitride.

For example, the method may further include forming a growth inhibiting layer on the surface of the growth substrate exposed through the plurality of cavities.

In one embodiment, forming the growth inhibiting layer may include treating the growth substrate with ammonia.

A method of manufacturing a semiconductor substrate according to an embodiment of the present invention includes the steps of forming a buffer layer on a growth substrate, forming a plurality of openings spaced apart from each other through the buffer layer in the buffer layer, Forming a plurality of cavities disposed below the plurality of openings, growing a semiconductor layer extending from the buffer layer and extending to the top of the buffer layer to fill the plurality of openings, And the step of separating the buffer layer and the semiconductor layer from the growth substrate by a stress acting thereon.

For example, in the plurality of cavities, the buffer layer may protrude from the growth substrate to form an undercut region.

For example, the growth substrate may be a silicon wafer, and the buffer layer and the semiconductor layer may be a single crystal III-nitride.

A method of fabricating a semiconductor substrate according to an embodiment of the present invention includes the steps of providing a stacked structure of a growth substrate and a buffer layer, forming a plurality of openings extending through the buffer layer and extending into the growth substrate, Growing a semiconductor layer from the buffer layer such that a plurality of cavities are formed in the growth substrate and separating the buffer layer and the semiconductor layer from the growth substrate by stress acting on the plurality of cavities, .

A substrate for semiconductor growth according to an embodiment of the present invention includes a growth substrate having a plurality of cavities spaced apart from each other on one surface thereof and a plurality of grooves disposed on the growth substrate and corresponding to the plurality of cavities Wherein a diameter of the plurality of openings at a boundary between the growth substrate and the buffer layer may be smaller than a diameter of the plurality of cavities.

For example, the plurality of cavities may be disposed in only a part of the growth substrate.

For example, the growth substrate may be a silicon wafer, and the buffer layer may be a group III nitride.

By forming cavities and openings in each of the growth substrate and the buffer layer, it is possible to provide a semiconductor substrate manufacturing method and a semiconductor growth substrate which can be easily processed.

The various and advantageous advantages and effects of the present invention are not limited to the above description, and can be more easily understood in the course of describing a specific embodiment of the present invention.

FIGS. 1 to 6 are major cross-sectional views schematically showing a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.
7 is a flowchart schematically showing a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.
8A to 8C are cross-sectional views schematically showing a cross-section of a substrate for semiconductor growth according to an embodiment of the present invention.
9 and 10 are cross-sectional views illustrating major steps in a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.
11 is a cross-sectional view schematically showing one step of a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.
12 is a plan view schematically showing a substrate for semiconductor growth according to an embodiment of the present invention.
13A and 13B are plan views schematically showing a part of a substrate for semiconductor growth according to an embodiment of the present invention.
14 to 16 are cross-sectional views illustrating an example of a semiconductor light emitting device including a semiconductor substrate according to an embodiment of the present invention.
17 to 19 show an example in which a semiconductor light emitting device including a semiconductor substrate according to an embodiment of the present invention is applied to a package.
20 is a schematic view showing a white light source module according to an embodiment of the present invention.
21 is a CIE coordinate system for explaining a wavelength conversion material that can be used in a semiconductor light emitting device package according to an embodiment of the present invention.
22 is an exploded perspective view schematically illustrating a lamp including a communication module as a lighting device according to an embodiment of the present invention.
23 is an exploded perspective view schematically showing a bar-type lamp as a lighting device according to an embodiment of the present invention.
24 schematically shows a lighting apparatus employing a light source module according to an embodiment of the present invention.
25 is a schematic view for explaining an indoor lighting control network system;
26 shows an embodiment of a network system applied to an open space.
27 is a block diagram for explaining a communication operation between a smart engine and a mobile device of a lighting device by visible light wireless communication.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

The embodiments of the present invention may be modified into various other forms or various embodiments may be combined, and the scope of the present invention is not limited to the following embodiments. Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings may be exaggerated for clarity of description, and the elements denoted by the same reference numerals in the drawings are the same elements.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. As used herein, terms such as " comprise, "" comprise ", or "have ", and the like, specify features, numbers, steps, operations, elements, parts, or combinations thereof described in the specification Steps, operations, elements, parts, or combinations thereof, which do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. The term "and / or" includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various elements, components, regions, layers and / or portions, these members, components, regions, layers and / It is obvious that no. These terms are only used to distinguish one member, component, region, layer or section from another region, layer or section. Thus, a first member, component, region, layer or section described below may refer to a second member, component, region, layer or section without departing from the teachings of the present invention.

In the description of embodiments of the present invention, a Miller index is used, which is expressed as a set of three integers as a notation describing a crystallographic plane or direction. A plurality of planes and orientations having the same relative symmetry with respect to the crystal axis are equivalent in terms of crystallography and some planes and directions having a given Miller index are selected only to select the position and orientation of the unit cell Lt; RTI ID = 0.0 > lattice < / RTI > These equivalent faces and orientations can be represented by a family, and the description of one face belonging to one family, for example, crystal face {100}, can be represented by three equivalent faces 100 ), (010), and (001).

FIGS. 1 to 6 are major cross-sectional views schematically showing a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.

7 is a flowchart schematically showing a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.

Referring to FIGS. 1 and 7, a buffer layer 110 may be formed on a growth substrate 101 to provide a stacked structure of a growth substrate 101 and a buffer layer 110 (S110).

The growth substrate 101 may be a substrate for semiconductor growth and a different substrate for gallium nitride (GaN), which is a semiconductor layer to be grown. The growth substrate 101 may be made of an insulating material, a conductive material, or a semiconductor material such as silicon (Si), sapphire, SiC, MgAl ₂ O ₄ , MgO, LiAlO ₂ or LiGaO ₂ . In the case of using silicon (Si) as the growth substrate 101, for example, a single crystal silicon (Si) wafer of 6 inches or more can be used. In this case, . For example, a (111) surface of a silicon (Si) substrate can be used for growth of a nitride compound. In one embodiment, the growth substrate 101 may include impurities in at least some regions.

The buffer layer 110 is a layer for improving the crystallinity of the semiconductor layers to be grown, and may include single or multiple layers. The buffer layer 110 may have a thermal expansion coefficient different from that of the growth substrate 101 and may include a material having a different thermal expansion coefficient from the growth substrate 101. In the case where the growth substrate 101 is a silicon (Si) substrate, the thermal expansion coefficient is about 2.6 x 10 ^-6 / K (111) or about 3.7 x 10 ^-6 / K (100 ) Plane, and in the case of a SiC substrate, it may be 4.2 to 4.7 x 10 < ^-6 > / K. Therefore, when the buffer layer 110 is made of GaN, the thermal expansion coefficient is 5.59 x 10 < ^-6 > / K, so that a difference in thermal expansion coefficient from the growth substrate 101 may occur.

The buffer layer 110 may be made of a Group III nitride, for example, Al _x In _y Ga _{1 -x- y} N (0? X? 1, 0? _Y <1, 0? _X + . &Lt; / RTI &gt; If made of a plurality of layers of the buffer layer 110, as the layers are, for example, AlN, SiC, Al ₂ O _3, AlGaN, AlInGaN, AlInBGaN, AlBGaN, GaN, multi-layered structure consisting of a single layer or a combination of XY . Here, X may be Ti, Cr, Zr, Hf, Nb or Ta, and Y may be nitrogen (N) or boron (B, B ₂ ). In one embodiment, the layer in direct contact with the growth substrate 101 is made of AlN to form nuclei for epitaxial growth of the semiconductor layer, and the silicon (Si) of the growth substrate 101 and the gallium (Ga) And the melt back phenomenon of forming the eutectic metal can be prevented.

The buffer layer 110 may be formed on the growth substrate 101 by metal organic chemical vapor deposition (MOCVD) or hydride vapor phase epitaxy (HVPE).

Referring to FIGS. 2 and 7, a plurality of openings H may be formed in the buffer layer 110 (S120).

The plurality of openings H may be spaced apart from each other through the buffer layer 110. The openings H may have various shapes such as a circle, an ellipse, a rectangle, and a polygon on a plane.

The openings H can be formed by an etching process such as dry etching. The sidewalls of the buffer layer 110 forming the openings H may have a predetermined inclination with respect to the upper surface of the growth substrate 101. However, the present invention is not limited thereto.

Referring to FIGS. 3 and 7, a plurality of cavities C may be formed on the growth substrate 101 (S130).

A plurality of cavities C may be formed at the bottom of the plurality of openings H so as to be connected to the plurality of openings H, respectively. The cavities C may be formed by removing the growth substrate 101 to a predetermined depth D1. The openings H may be formed by an etching process such as dry etching or wet etching. In one embodiment, this step S130 may be performed in a single step with step S120 of forming the openings H. In one embodiment, the step of forming the openings H (S120) may be performed by a dry etching process, and the present step (S130) may be performed by a wet etching process.

The cavities C may be defined by the etched surfaces 101Pa and 101Pb of the growth substrate 101. [ The side surface 101Pb of the surfaces 101Pa and 101Pb may be inclined with respect to the upper surface, and the bottom surface 101Pa may be parallel to the upper surface. However, the shape of the cavities C may be variously changed according to the embodiments. At least a part of the surfaces 101Pa and 101Pb may correspond to a crystal plane of the growth substrate 101, but the present invention is not limited thereto.

At the boundary between the buffer layer 110 and the growth substrate 101, the plurality of openings H each have a diameter of a first length L1, and the plurality of cavities C have a diameter smaller than a first length L1 And may have a larger second length L2. If the shapes of the openings H and the cavities C are not circular, the "diameter" may mean a dimension having the longest length in the plane. For example, when the shapes of the openings H and the cavities C are rectangular, the "diameter" may mean the diagonal length. The size of the cavities C is larger than the openings H so that the buffer layer 110 protrudes from the growth substrate 101 in the openings H and the cavities C An undercut region UC may be formed. The undercut region UC may correspond to a region under the protruded buffer layer 110. [ The undercut area UC at one side may have an upper length ranging from 10% to 30% of the second length L2, for example.

Referring to FIGS. 4 and 7, the semiconductor layer 120 may be grown on the buffer layer 110 (S140).

The semiconductor layer 120 may be epitaxially grown from the buffer layer 110. The semiconductor layer 120 may be a single crystal and may have a composition of Al _x In _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? The semiconductor layer 120 may grow from the buffer layer 110 to fill the openings H. [ At this time, the growth of the cavities C of the growth substrate 101 may be deteriorated or the growth may not occur due to the geometric characteristics. The cavity C may be partially grown on the growth substrate 101 in the cavity C so that the cavity C may remain as an empty space even if the growth is performed as in the cavity semiconductor layer 125 shown in FIG.

As the openings H are filled with the semiconductor layer 120 grown on the upper portion of the buffer layer 110, the cavities C form a closed region between the semiconductor layer 120 and the growth substrate 101 .

The semiconductor layer 120 can be grown by HVPE. In this case, the growth rate of GaN is faster than that of MOCVD, and the thick semiconductor layer 120 can be grown with a large area.

Referring to FIGS. 5 and 7, the buffer layer 110 and the semiconductor layer 120 may be spontaneously separated from the growth substrate 101 (S150).

The stress caused by the difference in thermal expansion coefficient between the growth substrate 101 and the buffer layer 110 and the difference in lattice constant can be concentrated in the cavities C when the semiconductor layer 120 is grown to a predetermined thickness D2 . The buffer layer 110 and the semiconductor layer 120 can be separated from the growth substrate 101 due to the generation of cracks in the lateral direction along the boundary between the growth substrate 101 and the buffer layer 110 from the cavities C have. That is, the growth substrate 101 can be separated from the stacked structure of the buffer layer 110 and the semiconductor layer 120.

This separation is induced by the cavities C and may occur spontaneously when the semiconductor layer 120 is grown to a predetermined thickness D2 according to the size of the cavities C. [ The thickness D2 of the semiconductor layer 120 to be separated may be in the range of, for example, 10 to 5 mm, and the size of the cavities C may be determined in consideration of the thickness of the desired semiconductor layer 120 , Such a spontaneous separation can be induced.

According to the manufacturing method of the semiconductor substrate of this embodiment, there is no need to perform a separate process when removing the growth substrate 101, which is a heterogeneous substrate after the semiconductor layer 120 is formed, so that the process can be simplified . In addition, since the cavities C can be formed uniformly and separation is uniformly performed, the semiconductor layer 120 can be grown with a large area.

Referring to FIG. 6, the semiconductor layer 120 may be sliced into a plurality of semiconductor substrates 121-126.

This step may be selectively performed, and a plurality of semiconductor substrates 121-126 may be manufactured by slicing the semiconductor layer 120 according to the application. This step may be omitted depending on the thickness of the desired semiconductor substrate, and in one embodiment, may be performed to remove only the region including the lower buffer layer 110.

The semiconductor substrates 121-126 are each a freestanding substrate and can be used for manufacturing semiconductor devices. For example, each of the semiconductor substrates 121-126 may be used to grow GaN semiconductor layers on the top to manufacture a semiconductor light emitting device.

8A to 8C are cross-sectional views schematically showing a substrate for semiconductor growth according to an embodiment of the present invention.

 8A to 8C are sectional views of a semiconductor growth substrate having a structure in which a growth substrate 101 on which cavities C are formed and a buffer layer 110 on which openings H are formed are stacked Indicates one area.

Referring to FIG. 8A, the cavity Ca can be defined by the etched surfaces 101Pa, 101Pb, and 101Pc of the growth substrate 101. The side surfaces 101Pb and 101Pc of the surfaces 101Pa, 101Pb and 101Pc may be inclined with respect to the upper surface of the growth substrate 101 and the bottom surface 101Pa may be parallel to the upper surface. The planes 101Pa, 101Pb, and 101Pc may correspond to the crystal planes of the growth substrate 101. This can be formed by forming the etching along the crystal face at the time of forming the cavity Ca. The cavity Ca may be defined as five faces in the illustrated cross-section, and may be defined as seven or more faces in consideration of an unillustrated region. In particular, the surface 101Pc of the growth substrate 101 connected to the buffer layer 110 may be a negative inclined surface. In the present specification, the term &quot; negative slope &quot; is used to mean a slope formed so that the width decreases from the upper surface. That is, since the surface 101Pc of the growth substrate 101 is inclined to decrease the width of the growth substrate 101 as the distance from the top surface of the growth substrate 101 decreases, the surface 101Pc may be referred to as a negative sloped surface.

Referring to FIG. 8B, the cavity Cb may be formed by etching the growth substrate 101 to a curved surface. In this case also, the buffer layer 110 protrudes from the growth substrate 101 at the boundary between the growth substrate 101 and the buffer layer 110, and an undercut region can be formed in the cavity Cb.

Referring to FIG. 8C, the cavity Cc may be formed such that the growth substrate 101 is formed along the crystal planes as shown in FIG. 8A, while the boundary between the planes is relaxed to form a curved surface. Also in this case, the buffer layer 110 protrudes from the growth substrate 101 at the boundary between the growth substrate 101 and the buffer layer 110, and an undercut region can be formed in the cavity Cc.

Thus, in the substrates for semiconductor growth, the cavities Ca, Cb, and Cc can have various shapes within a range in which the buffer layer 110 protrudes into the cavities Ca, Cb, and Cc.

9 and 10 are cross-sectional views illustrating major steps in a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.

First, as described above with reference to FIGS. 1 to 3, a substrate for semiconductor growth having a structure in which a growth substrate 101 on which cavities C are formed and a buffer layer 110 on which openings H are formed are stacked, May be performed.

Next, referring to FIG. 9, the growth inhibiting layer 105 may be formed on the surface of the growth substrate 101 exposed through the cavities C.

The growth inhibiting layer 105 may be a layer which prevents subsequent growth of the semiconductor. The growth inhibiting layer 105 may be made of, for example, silicon nitride. In this case, the growth inhibiting layer 105 can be formed by treating the surface of the exposed growth substrate 101 with ammonia gas.

Referring to FIG. 10, the semiconductor layer 120 may be grown on the buffer layer 110.

At this time, the semiconductor is not grown in the cavity C by the growth inhibiting layer 105, and the cavity C may remain in the empty space.

Next, as described above with reference to Fig. 5, the separation process of the growth substrate 101 can be performed.

11 is a cross-sectional view schematically showing one step of a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.

First, as described above with reference to FIGS. 1 to 3, a substrate for semiconductor growth having a structure in which a growth substrate 101 on which cavities C are formed and a buffer layer 110 on which openings H are formed are stacked, May be performed.

Next, referring to FIG. 11, after the additional buffer layers 112 and 114 are formed, a semiconductor layer 120a may be formed. Additional buffer layers 112 and 114 may be additionally formed on the buffer layer 110 to further reduce defects such as dislocation or to reduce stress.

The additional buffer layers 112 and 114 may be different in composition and / or growth conditions from the buffer layer 110. Further, the additional buffer layers 112 and 114 may have a lower defect density than the buffer layer 110. [ In one embodiment, any one of the additional buffer layers 112 and 114 may serve as a masking layer blocking the threading dislocations, for example, SiN. However, the number of the additional buffer layers 112 and 114 is not limited to the illustrated ones, and various numbers and materials may be selected according to the embodiments.

Next, as described above with reference to Fig. 5, the separation process of the growth substrate 101 can be performed.

12 is a plan view schematically showing a substrate for semiconductor growth according to an embodiment of the present invention.

12, the substrate for semiconductor growth has a structure in which a growth substrate 101 on which cavities C are formed and a buffer layer 110 on which openings H are formed are stacked.

Each of the openings H and the cavities C are disposed at positions corresponding to each other, and the centers thereof can be matched. The openings H and cavities C may be arranged evenly in rows and columns, and are not limited to the arrangement shown. In this embodiment, the cavities C are uniformly formed on the entire growth substrate 101, so that the separation of the growth substrate 101 and the semiconductor layer 120 described above with reference to FIG. 5 can be uniformly performed as a whole . Therefore, even when the semiconductor layer 120 is grown in a large area, stable separation can be achieved

The openings H have a first length L1 'on the upper surface of the buffer layer 110 and the cavities C have a second length L2 larger than the first length L1' As shown in FIG. The first length L 1 'may be, for example, in the range of 1 μm to 10 μm and the second length L 2 may be in the range of 3 μm to 15 μm, but is not limited thereto.

The first length L1 'and the second length L2 can be determined in consideration of the thickness of the semiconductor layer 120 (see FIG. 5) grown before being separated. For example, if the thickness of the semiconductor layer 120 to be formed is relatively thick, the first length L1 'and the second length L2 may be selected to be relatively small such that the cavities C are formed small . Conversely, when the thickness of the semiconductor layer 120 to be formed is relatively thin, the first length L1 'and the second length L2 can be selected to be relatively large so that the cavities C are formed to be large.

The ratio of L1 ': L3, that is, L1' / L3, may be in the range of, for example, 0.65 to 18, where L3 is the length between adjacent openings H. Accordingly, the area occupied by the openings H in the buffer layer 110 can be determined within a range of 20% to 90% of the area of the buffer layer 110. If the area of the openings H is smaller than the above range, the growth substrate 101 may be difficult to separate. If the area of the openings H is larger than the above range, the semiconductor layer 120 is difficult to grow, There is a risk that the semiconductor layer 120 is broken during growth.

13A and 13B are plan views schematically showing a part of a substrate for semiconductor growth according to an embodiment of the present invention.

13A and 13B, the growth substrates 101a and 101b constituting the substrate for semiconductor growth may be formed with cavities C only in a part of the regions R and Ra. Accordingly, the openings H of the upper buffer layer 110 (see FIG. 12) can be formed only in the partial regions R and Ra where the cavities C are formed.

The cavities C are formed only in the partial regions R and Ra other than the entire regions of the growth substrates 101a and 101b so that the subsequently grown semiconductor layer 120 Separation can be started from the regions R and Ra where the cavities C are formed. In addition, even when the stress and strain generated in the substrate for semiconductor growth during the growth of the semiconductor layer 120 are not uniform, the positions of the regions R and Ra where the cavities C are formed are adjusted , Separation can occur at the desired thickness without defects such as cracks.

In this embodiment, the thickness of the semiconductor layer 120 grown on the upper portion can be controlled by adjusting the area of the regions R and Ra where the cavities C are formed. The area of the regions R and Ra where the cavities C are formed may be smaller than about 70% of the area of the entire growth substrates 101a and 101b, but the present invention is not limited thereto. For example, when the semiconductor layer 120 is formed relatively thick, the regions R and Ra where the cavities C are formed are made small, so that the separation time of the semiconductor layer 120 can be reduced. In some embodiments, the first length L1 ', the second length L2, or L1', as described with reference to Figure 12, as well as the area of the areas R, Ra where the cavities C are formed, : L3, the thickness at which the semiconductor layer 120 is separated may be controlled.

13A, when the growth substrate 101a has a circular shape, the cavities C may be disposed only in the peripheral region R except for the central portion. As a result, the separation of the semiconductor layer 120 can be induced from the outside of the growth substrate 101a to the inside as shown by the arrows. Even when the growth substrate 101a has a shape other than a circular shape, the cavity forming region R can be disposed along the edge. The width D3 of the region R where the cavities C are formed can be variously adjusted within the radius D4 of the growth substrate 101a.

13B, when the growth substrate 101b has a circular shape, the cavities C may be disposed only in the central region Ra, and the cavities C may be disposed in the peripheral region around the center region Ra . As a result, the separation of the semiconductor layer 120 can be induced from the center of the growth substrate 101b to the outside as shown by the arrow. Even when the growth substrate 101b has a shape other than a circular shape, the cavity forming region Ra can be located at the center. The width or diameter D5 of the area Ra in which the cavities C are formed can be variously adjusted in the embodiments.

14 to 16 are cross-sectional views illustrating an example of a semiconductor light emitting device including a semiconductor substrate according to an embodiment of the present invention.

14, a semiconductor light emitting device 200 includes a substrate 201 and a first conductive semiconductor layer 214, an active layer 215, and a second conductive semiconductor layer (not shown) 216). The semiconductor light emitting device 200 may further include an element buffer layer 212 disposed between the substrate 201 and the first conductive semiconductor layer 214. The semiconductor light emitting device 200 includes a first electrode 219a disposed on the first conductive semiconductor layer 214, an ohmic contact layer 218 sequentially disposed on the second conductive semiconductor layer 216, Two electrodes 219b may be further included.

The substrate 201 may be a GaN substrate, and may be a substrate manufactured according to the method of manufacturing a semiconductor substrate according to an embodiment of the present invention described above with reference to FIGS. 1 to 13B.

The buffer layer 212 may be made of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1). For example, the buffer layer 212 may be GaN, AlN, AlGaN, InGaN. In one embodiment, the buffer layer 212 may be a combination of multiple layers, or may be used with a gradual change in composition.

The first conductive semiconductor layer 214 may be made of a nitride semiconductor of n-type In _x Al _y Ga _{1 -xy} N (0? _X <1, 0? Y <1, 0? _X + y < The n-type impurity may be silicon (Si). For example, the first conductivity type semiconductor layer 214 may be n-type GaN.

In the present embodiment, the first conductive semiconductor layer 214 may include a first conductive semiconductor contact layer 214a and a current diffusion layer 214b. The impurity concentration of the first conductivity type semiconductor contact layer 214a may be in the range of 2 × 10 ¹⁸ cm ^-3 to 9 × 10 ¹⁹ cm ^-3 . The thickness of the first conductivity type semiconductor contact layer 214a may be between 1 탆 and 5 탆. The current diffusion layer 214b includes a plurality of In _x Al _y Ga _(1-xy) N (0? X, y? 1, 0? _X + y? 1) layers having different compositions or different impurity contents It can have a repeatedly stacked structure. For example, the current diffusion layer 214b may include an n-type GaN layer having a thickness of 1 nm to 500 nm and / or an Al _x In _y Ga _z N (0? X, y, z? 1, 0 &lt; / RTI &gt; (except for &quot; 0 &quot;) may be repeated to form an n-type superlattice layer. The impurity concentration of the current diffusion layer 214b may be in the range of 2 x 10 ¹⁸ cm ^-3 to 9 x 10 ¹⁹ cm ^-3 . In one embodiment, a layer of insulating material may be further introduced into the current spreading layer 214b.

The second conductive semiconductor layer 216 may be made of a nitride semiconductor of p-type In _x Al _y Ga _{1 -x- y} N (0? _X <1, 0? _Y <1, 0? _X + y < And the p-type impurity may be magnesium (Mg). For example, the second conductive semiconductor layer 216 may have a single-layer structure, but may have a multi-layer structure having different compositions as in the present embodiment. 14, the second conductivity type semiconductor layer 216 includes an electron blocking layer (EBL) 216a, a lightly doped p-type GaN layer 216b, and a high concentration p-type GaN Layer 216c. For example, the electron blocking layer 216a may comprise a plurality of different compositions of In _x Al _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1 , 0? X + y? 1), or a single layer having a composition of Al _y Ga _(1-y) N (0 <y? 1). The energy band gap Eg of the electron blocking layer 216a may decrease as the distance from the active layer 215 increases. For example, the aluminum (Al) composition of the electron blocking layer 216a may decrease as the distance from the active layer 215 increases.

The active layer 215 may be a multiple quantum well (MQW) structure in which quantum well layers and quantum barrier layers are alternately stacked. For example, the quantum well layer and the quantum barrier layer may be formed of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) Lt; / RTI &gt; In one embodiment, the quantum well layer may be made of In _x Ga _{1 -x} N (0 &lt; x &lt; ₁ ), and the quantum barrier layer may be made of GaN or AlGaN. The thicknesses of the quantum well layer and the quantum barrier layer may be in the range of 1 nm to 50 nm, respectively. The structure of the active layer 215 is not limited to a multiple quantum well structure, and may have a single quantum well structure.

The first electrode 219a may include a material such as Ag, Ni, Al, Cr, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Structure. In one embodiment, a pad electrode layer may be further disposed on the first electrode 219a. The pad electrode layer may be a layer containing at least one of Au, Ni, and Sn.

The ohmic contact layer 218 may be variously implemented depending on the packaging structure at the time of packaging. For example, in the case of a flip chip structure, the ohmic contact layer 218 may comprise a metal such as Ag, Au, Al, or a transparent conductive oxide such as ITO, ZIO, GIO, and the like. For example, in the structure in which light is emitted upward in the drawing, the ohmic contact layer 218 may be made of a light-transmitting electrode. The light-transmitting electrode may include any one of a transparent conductive oxide layer and a nitride layer. The transmissive electrode may be formed of, for example, ITO (Indium Tin Oxide), ZINO (Zinc-doped Indium Tin Oxide), ZIO (Zinc Indium Oxide), GIO (Gallium Indium Oxide), ZTO (Zinc TinOxide) Tin Oxide), AZO (Aluminum-doped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), In ₄ Sn ₃ O ₁₂ and Zn _(1-x) Mg _x O (Zinc Magnesium Oxide, At least one selected. In one embodiment, the ohmic contact layer 218 may comprise a graphene. The second electrode 219b may include at least one of Al, Au, Cr, Ni, Ti, and Sn.

Referring to FIG. 15, a semiconductor light emitting device 300 includes a substrate 301 and a semiconductor stacked body S formed on the substrate 301. The semiconductor stacked body S may include a first conductive type semiconductor layer 314, an active layer 315, and a second conductive type semiconductor layer 316. The semiconductor light emitting device 300 may further include first and second electrodes 322 and 324 connected to the first and second conductivity type semiconductor layers 314 and 316, respectively.

The substrate 301 may be a GaN substrate, and may be a substrate manufactured according to the method of manufacturing a semiconductor substrate according to an embodiment of the present invention described above with reference to FIGS. 1 to 13B.

The first electrode 322 includes a connection electrode portion 322a in the form of a conductive via which is connected to the first conductivity type semiconductor layer 314 through the second conductivity type semiconductor layer 316 and the active layer 315, And a first electrode pad 322b connected to the first electrode pad 322a. The connection electrode portion 322a may be surrounded by the insulating portion 321 and electrically separated from the active layer 315 and the second conductivity type semiconductor layer 316. [ The connection electrode portion 322a may be disposed in an area where the semiconductor stacked body 310 is etched. The number, shape, pitch, or contact area of the connection electrode portion 322a with the first conductivity type semiconductor layer 314 can be appropriately designed so as to lower the contact resistance. Further, the connection electrode portion 322a is arranged in rows and columns on the semiconductor stacked body 310, thereby improving current flow.

The second electrode 324 may include an ohmic contact layer 324a and a second electrode pad 324b on the second conductive semiconductor layer 316. [ The connection electrode portion and the ohmic contact layers 322a and 324a may have a single layer or a multilayer structure of a conductive material having ohmic characteristics with the first and second conductivity type semiconductor layers 314 and 316, respectively. For example, the connection electrode portion and the ohmic contact layers 322a and 324a may be formed of at least one of Ag, Al, Ni, Cr, and a transparent conductive oxide (TCO).

The first and second electrode pads 322b and 324b may be connected to the connection electrode portion and the ohmic contact layers 322a and 324a to function as external terminals of the semiconductor light emitting device 300. [ For example, the first and second electrode pads 322b and 324b may include Au, Ag, Al, Ti, W, Cu, Sn, Ni, Pt, Cr, NiSn, TiW, AuSn, . The first and second electrodes 322 and 324 may be disposed in the same direction as each other, and may be mounted in a lead frame or the like in the form of a flip chip.

The first and second electrodes 322 and 324 may be electrically separated from each other by an insulating portion 321. [ The insulating portion 321 may be made of an insulating material, and a material having a low light absorptivity may be used. For example, the insulating portion 321 may use silicon oxide such as SiO ₂ , SiO _x N _y , Si _x N _y , or silicon nitride.

In one embodiment, the insulating portion 321 may be formed of a light reflecting structure in which a light reflective filler is dispersed in a light transmitting material. Alternatively, the insulating portion 321 may be a multilayered reflection structure in which a plurality of insulating layers having different refractive indices are alternately laminated. For example, such a multilayered reflection structure may be a distributed Bragg reflector (DBR) in which a first insulating film having a first refractive index and a second insulating film having a second refractive index are alternately laminated. The multi-layered reflection structure may have a structure in which a plurality of insulating layers having different refractive indices are repeatedly laminated two to 100 times. The plurality of insulating layers may be oxides or nitrides such as SiO ₂ , SiN, SiO _x N _y , TiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiN, AlN, ZrO ₂ , TiAlN, TiSiN, have. For example, when the wavelength of light generated in the active layer 315 is? And n is the refractive index of the insulating layer, the first insulating film and the second insulating film may be formed to have a thickness of? / 4n , &Lt; / RTI &gt; and a thickness of about 300 ANGSTROM to 900 ANGSTROM. At this time, the refractive index and thickness of each of the first insulating film and the second insulating film may be selected so that the multilayered reflective structure has a high reflectivity of 95% or more with respect to the wavelength of light generated in the active layer 315. The refractive indexes of the first insulating layer and the second insulating layer may be in a range of about 1.4 to 2.5 and may be less than a refractive index of the first conductive type semiconductor layer 314.

16, the semiconductor light emitting device 400 includes a substrate 401 and a nano-light-emitting structure S disposed on the substrate 401. Referring to FIG. The nano-light-emitting structure S may include a first conductivity type semiconductor core 422, an active layer 424, and a second conductivity type semiconductor layer 426. The semiconductor light emitting device 400 includes a base layer 410 disposed between the substrate 401 and the nano-light-emitting structure S, an insulating layer 416, and a transparent electrode layer 442 covering the nano- A filling layer 418, and first and second electrodes 430 and 440 having an electrode structure.

The substrate 401 may be a GaN substrate, and may be a substrate manufactured according to the method of manufacturing a semiconductor substrate according to an embodiment of the present invention described above with reference to FIGS. 1 to 13B.

The base layer 410 may be disposed on the substrate 401. Base layer 410 may be a III-V group compound, for example GaN. The base layer 410 may be, for example, n-GaN doped with n-type. In this embodiment, the base layer 410 not only provides a crystal plane for growing the first conductivity type semiconductor core S, but also serves as a contact electrode in common to one side of the nanosillectural structures S . &Lt; / RTI &gt;

An insulating layer 416 may be disposed on the base layer 410. Insulating layer 416 may be formed of silicon oxide or silicon nitride, for example, at least one of SiO _x, SiO _x N _y, Si _x N _y, Al ₂ O _3, TiN, AlN, ZrO, TiAlN, TiSiN Lt; / RTI &gt; The insulating layer 416 includes a plurality of openings that expose a portion of the base layer 410. The diameter, length, position, and growth conditions of the nano-light-emitting structure S can be determined according to the size of the plurality of openings. The plurality of openings may have various shapes such as a circle, a rectangle, and a hexagon.

A plurality of nano-light-emitting structures S may be disposed at positions corresponding to the plurality of openings, respectively. The nano-light-emitting structure S includes a first conductivity type semiconductor core 422 grown from the base layer 410 exposed by the plurality of openings, an active layer sequentially formed on the surface of the first conductivity type semiconductor core 422, A second conductivity type semiconductor layer 424 and a second conductivity type semiconductor layer 426. [

The number of the nano-light-emitting structures S included in the semiconductor light-emitting device 400 is not limited to that shown in the figure, and the semiconductor light-emitting device 400 may include, for example, tens to millions of nano- . The nano-light-emitting structure S of the present embodiment may be composed of a lower hexagonal column region and an upper hexagonal pyramid region. According to an embodiment, the nano-light-emitting structure S may be pyramidal or columnar. Since the nano-light-emitting structure S has such a three-dimensional shape, the light-emitting surface area is relatively wide and the light efficiency can be increased.

The transparent electrode layer 442 covers the top and sides of the nano-light-emitting structure S and may be arranged to be connected to each other between the adjacent nano-light-emitting structures S. The transparent electrode layer 442, for example, ITO (Indium tin Oxide), AZO (Aluminium Zinc Oxide), IZO (Indium Zinc Oxide), ZnO, GZO (ZnO: Ga), In 2 O 3, SnO 2, CdO, CdSnO _4, or may be a Ga ₂ O _3.

The filling layer 418 is filled between adjacent nanostructured structures S and may be disposed to cover the nanostructured structure S and the transparent electrode layer 442 on the nanostructured structure S. [ The filling layer 418 may be formed of a transmissive insulating material, for example, it may include _{SiO 2, SiN x, Al 2} O 3, HfO, TiO 2 or ZrO.

The first and second electrodes 430 and 440 are disposed on the base layer 410 and the transparent electrode layer 442 so as to be electrically connected to the base layer 410 and the second conductivity type semiconductor layer 424, .

Since the GaN substrate manufactured according to one embodiment of the present invention is used as the substrates 201, 301 and 401 in the semiconductor light emitting devices 200, 300 and 400 described above, compared to the case of using another substrate such as a sapphire substrate, The crystal quality of the semiconductor layers including the active layers 215, 315, and 424 formed in the semiconductor light emitting devices 200, 300, and 400 can be improved. The substrates 201, 301 and 401 may be formed as large-area substrates and may be formed by stacking the semiconductor light emitting devices 200, 300, and 400 and the following semiconductor light emitting device packages 600, 700, Can be manufactured.

17 to 19 show an example in which a semiconductor light emitting device including a semiconductor substrate according to an embodiment of the present invention is applied to a package.

17, the semiconductor light emitting device package 600 includes the light emitting stack S, the first and second terminals Ta and Tb, the phosphor layer 607, and the lens 620 disposed on the mounting substrate 611 ). In the semiconductor light emitting device package 600, electrodes are formed on the lower surface of the light emitting device 610 opposite to the main light extracting surface, and the phosphor layer 607 and the lens 620 are integrally formed, Package, CSP) structure.

The light emitting laminate S may include first and second conductive semiconductor layers 604 and 606 and an active layer 605 disposed therebetween. The first and second conductive semiconductor layers 604 and 606 may be p-type and n-type semiconductor layers, respectively, and may be a nitride semiconductor, for example, Al _x In _y Ga _(1-xy) , 0 <y <1, 0 <x + y <1). In addition to the nitride semiconductor, a GaAs-based semiconductor or a GaP-based semiconductor may also be used.

The active layer 605 formed between the first and second conductivity type semiconductor layers 604 and 606 emits light having a predetermined energy by recombination of electrons and holes and the quantum well layer and the quantum barrier layer alternate with each other A multi quantum well (MQW) structure. In the case of a multiple quantum well structure, for example, InGaN / GaN, AlGaN / GaN structures may be used.

The semiconductor light emitting device 610 may be formed in a state in which the substrate is removed, and the surface on which the substrate is removed may be provided with projections and depressions P. Further, the phosphor layer 807 may be disposed as a light conversion layer on the surface on which the unevenness P is formed. The substrate may be a substrate manufactured according to the method of manufacturing a semiconductor substrate according to an embodiment of the present invention described above with reference to FIGS. 1 to 13B. In one embodiment, the substrate may not be removed, and the irregularities P and the light conversion layer may be formed on the back surface of the substrate.

The first and second electrodes 609a and 609b may be connected to the first and second conductivity type semiconductor layers 604 and 606, respectively. The first electrode 609a may include a conductive via 608 connected to the second conductive semiconductor layer 604 through the second conductive semiconductor layer 606 and the active layer 605. The insulating layer 603 surrounding the conductive via 608 can prevent the active layer 605 and the second conductive type semiconductor layer 606 from short-circuiting. In this embodiment, one of the conductive vias 608 is illustrated as an example, but a plurality of conductive vias 608 may be arranged in various shapes to facilitate current dispersion. The diameter L4 of the conductive via 608 may be determined in consideration of the area of the luminescent laminate S. [

The mounting substrate 611 may be a substrate to which a semiconductor process such as a silicon substrate can be easily applied, but is not limited thereto. The mounting substrate 611 and the light emitting element 610 may be bonded by the bonding layers 602 and 612. The bonding layers 602 and 612 may be made of an insulating material or an electrically conductive material. For example, oxides such as SiO ₂ and SiN, resin materials such as silicon resin and epoxy resin, Ag, Al, Ti, W, Cu, Sn, Ni, Pt, Cr, NiSn, TiW, AuSn or their eutectic metals.

In one embodiment, the first and second electrodes 609a and 609b may be connected to the first and second terminals Ta and Tb of the mounting board 611 without the bonding layers 602 and 612. In one embodiment, the first and second electrodes 609a and 609b may each comprise a plurality of metal layers. For example, the first and second electrodes 609a, 609b may comprise a UBM (Under Bump Metallurgy) layer comprising a solder pad and a solder bumper layer. In this case, the mounting substrate 611, the bonding layers 602 and 612, and the first and second terminals Ta and Tb may be omitted.

Referring to FIG. 18, the semiconductor light emitting device package 700 may include a semiconductor light emitting device 701, a mounting substrate 710, and a sealing member 703 having the same structure as shown in FIG.

The semiconductor light emitting device 701 may be mounted on the mounting substrate 710 and electrically connected to the mounting substrate 710 through the wire W. [ The mounting substrate 710 may include a substrate body 711, an upper electrode 713, a lower electrode 714 and a penetrating electrode 712 connecting the upper electrode 713 and the lower electrode 714. The body of the mounting board 710 may be made of resin, ceramic, or metal, and the upper or lower electrodes 713 and 714 may be a metal layer made of a metal such as Au, Cu, Ag, or Al. For example, the mounting substrate 713 may be provided as a PCB, MCPCB, MPCB, FPCB, or the like, and the structure of the mounting substrate 710 may be applied in various forms.

The sealing member 703 may be formed in a dome-shaped lens structure having a convex upper surface. However, according to the embodiment, the surface of the sealing member 703 may be formed into a convex or concave lens structure so that the light emitted through the upper surface of the sealing member 703 It is possible to adjust the angle.

Referring to FIG. 19, the semiconductor light emitting device package 800 may include a semiconductor light emitting device 801, a package body 802, and a pair of lead frames 803 having the same structure as shown in FIG.

The semiconductor light emitting element 801 is mounted on the lead frame 803 so that each electrode can be electrically connected to the lead frame 803 by the wire W. [ In one embodiment, the semiconductor light emitting element 801 may be mounted in an area other than the lead frame 803, for example, in the package body 802. [ The package body 802 may have a cup-shaped groove portion so as to improve the reflection efficiency of light. The package body 802 may be formed of a light transmitting material to seal the semiconductor light emitting element 801 and the wire W, May be formed. In one embodiment, the plugs 805 may contain wavelength changing materials such as phosphors and / or quantum dots.

20 is a schematic view showing a white light source module according to an embodiment of the present invention.

The white light source module shown in FIG. 20 may include a plurality of light emitting device packages each mounted on a circuit board. The plurality of light emitting device packages mounted on one white light source module may be composed of light emitting device packages of the same type emitting light of the same wavelength or different types of light emitting device packages emitting light of different wavelengths.

20 (a), the white light source module may be configured by combining a white light emitting device package ('40', '30') and a red light emitting device package ('red') having color temperatures of 4000 K and 3000 K have. The white light source module can provide white light having a color temperature ranging from 3000 K to 4000 K and a color rendering property Ra ranging from 85 to 100.

In one embodiment, the white light source module may include a white light emitting device package composed of only a white light emitting device package and emitting white light of a color temperature different from (a). For example, as shown in FIG. 20B, a white light emitting device package ('27') having a color temperature of 2700 K and a white light emitting device package ('50' 5000 K and can provide white light having a color rendering property Ra of 85 to 99. [ Here, the number of light emitting device packages at each color temperature can be changed mainly depending on the basic color temperature setting value. For example, if the default setting is a lighting device near the color temperature of 4000 K, the number of packages corresponding to 4000 K may be higher than the color temperature 3000 K or the number of red light emitting device packages.

As described above, the different kinds of light emitting device packages may include at least one of a purple, blue, green, red or infrared light emitting device package in a light emitting device package that emits white light by combining phosphors of yellow, green, red, So that the color temperature and the color rendering index (CRI) of the white light can be adjusted.

The white light source module may be used as the light source module 2040 of the bulb type illumination device 2000 (see FIG. 22) described below.

In a single light emitting device package, light of a desired color can be determined according to the wavelength of the LED chip, which is a light emitting element, and the type and blending ratio of the phosphor. In the case of the white light emitting device package, the color temperature and the color rendering property can be controlled.

For example, when the LED chip emits blue light, the light emitting device package including at least one of the yellow, green, and red phosphors may emit white light having various color temperatures depending on the compounding ratio of the phosphors. Alternatively, a light emitting device package to which a green or red phosphor is applied to a blue LED chip may emit green or red light. Thus, the color temperature and the color rendering property of white light can be controlled by combining a light emitting device package emitting white light and a package emitting green or red light. Further, the light emitting device package may be configured to include at least one of the light emitting devices emitting violet, blue, green, red, or infrared rays.

In this case, the illuminating device can adjust the color rendering property from sodium (Na) to sunlight level, and can generate various white light with a color temperature ranging from 1500 K to 20000 K. If necessary, the color of purple, blue, green, Orange visible light or infrared light can be generated to adjust the illumination color according to the ambient atmosphere or mood. The illumination device may also generate light of a particular wavelength that can promote plant growth.

(X, y) of the CIE 1931 coordinate system, as shown in FIG. 21, has a peak wavelength of two or more, and the white light made of a combination of yellow, green and red phosphors and / The coordinates can be located in the segment area connecting (0.4476, 0.4074), (0.3484, 0.3516), (0.3101, 0.3162), (0.3128, 0.3292), (0.3333, 0.3333). Alternatively, the (x, y) coordinate may be located in an area surrounded by the line segment and the blackbody radiation spectrum. The color temperature of the white light corresponds to the range of 1500 K to 20000 K. In FIG. 21, the white light near the point E (0.3333, 0.3333) located under the black body radiation spectrum is in a state in which the light of the yellowish component is relatively weak, and in the region where the light has a clearer or fresh feeling It can be used as an illumination light source. Therefore, the lighting product using the white light near the point E (0.3333, 0.3333) located below the blackbody radiation spectrum is effective as a commercial lighting for selling foodstuffs, clothing, and the like.

As a material for converting the wavelength of light emitted from the semiconductor light emitting element, various materials such as a phosphor and / or a quantum dot can be used

The phosphor may have the following composition formula and color.

· Oxide system: yellow and green Y ₃ Al ₅ O ₁₂ : Ce, Tb ₃ Al ₅ O ₁₂ : Ce, Lu ₃ Al ₅ O ₁₂ : Ce

(Ba, Sr) ₂ SiO ₄ : Eu, yellow and orange (Ba, Sr) ₃ SiO ₅ : Ce

, Nitride-based: the green β-SiAlON: Eu, yellow _{La 3 Si 6 N 11: Ce} , orange-colored α-SiAlON: Eu, red _{CaAlSiN 3: Eu, Sr 2 Si} 5 N 8: Eu, SrSiAl 4 N 7: Eu, _{SrLiAl 3 N 4: Eu, Ln} 4 -x (Eu z M 1 -z) x Si 12-y Al y O 3 + x + y N 18-xy (0.5≤x≤3, 0 <z <0.3, 0 < y? 4), wherein Ln is at least one element selected from the group consisting of Group IIIa elements and rare earth elements, and M is at least one kind of element selected from the group consisting of Ca, Ba, .

, Fluorite (fluoride) type: KSF-based Red ^{_{K 2 SiF 6: Mn 4 +}} , K 2 TiF 6: Mn 4 +, NaYF 4: Mn 4 +, NaGdF 4: Mn 4 +, K 3 SiF 7: Mn 4 ⁺

The phosphor composition should basically correspond to stoichiometry, and each element can be replaced with another element in each group on the periodic table. For example, Sr can be replaced with Ba, Ca, Mg, etc. of the alkaline earth (II) group, and Y can be replaced with Tb, Lu, Sc, Gd and the like of the lanthanide series. In addition, Eu, which is an activator, can be substituted with Ce, Tb, Pr, Er, Yb or the like according to a desired energy level.

In particular, the fluorite red phosphor may be coated with a fluoride that does not contain Mn in order to improve reliability at a high temperature / high humidity, or may be coated with an organic material on a fluoride surface or a fluoride coated surface not containing Mn. Unlike other phosphors, the fluorite red phosphor can be used in a high-resolution TV such as a UHD TV because it can realize a narrow bandwidth of 40 nm or less.

Table 1 below shows the types of phosphors for application fields of white light emitting devices using blue LED chips (440 to 460 nm) or UV LED chips (380 to 440 nm).

Usage Phosphor LED TV BLU ^{β-SiAlON: Eu 2 +,} (Ca, Sr) AlSiN 3: Eu 2 +, La 3 Si 6 N 11: Ce 3 +, K 2 SiF 6: Mn 4 +, SrLiAl 3 N 4: Eu, Ln 4 - _{x (Eu z M 1 -z)} x Si 12- y Al y O 3 + x + y N 18 -xy (0.5≤x≤3, 0 <z <0.3, 0 <y≤4), K 2 TiF 6: Mn ^{4 +} , NaYF ₄ : Mn ^{4 +} , NaGdF ₄ : Mn ^{4 +} light _{Lu 3 Al 5 O 12: Ce} 3 +, Ca-α-SiAlON: Eu 2 +, La 3 Si 6 N 11: Ce 3 +, (Ca, Sr) AlSiN 3: Eu 2 +, Y 3 Al 5 O 12 _{^{: Ce 3+, K 2 SiF 6}} : Mn 4 +, SrLiAl 3 N 4: Eu, Ln 4 -x (Eu z M 1 -z) x Si 12- y Al y O 3 + x + y N 18 -xy ( K ₂ TiF ₆ : Mn ^{4 +} , NaYF ₄ : Mn ^{4 +} , NaGdF ₄ : Mn ^{4 +} Side view
(Mobile, Note PC) _{Lu 3 Al 5 O 12: Ce} 3 +, Ca-α-SiAlON: Eu 2 +, La 3 Si 6 N 11: Ce 3 +, (Ca, Sr) AlSiN 3: Eu 2 +, Y 3 Al 5 O 12 ^{: Ce 3+, (Sr, Ba} , Ca, Mg) 2 SiO 4: Eu 2 +, K 2 SiF 6: Mn 4 +, SrLiAl 3 N 4: Eu, Ln 4 -x (Eu z M 1 -z) _{x Si 12- y Al y O 3} + x + y N 18 -xy (0.5≤x≤3, 0 <z <0.3, 0 <y≤4), K 2 TiF 6: Mn 4 +, NaYF 4: Mn 4 ⁺ , NaGdF ₄ : Mn ^{4 +} Battlefield
(Head lamp, etc.) _{Lu 3 Al 5 O 12: Ce} 3 +, Ca-α-SiAlON: Eu 2 +, La 3 Si 6 N 11: Ce 3 +, (Ca, Sr) AlSiN 3: Eu 2 +, Y 3 Al 5 O 12 _{^{: Ce 3+, K 2 SiF 6}} : Mn 4 +, SrLiAl 3 N 4: Eu, Ln 4 -x (Eu z M 1 -z) x Si 12- y Al y O 3 + x + y N 18 -xy ( 0.5≤x≤3, 0 <z <0.3, 0 <y≤4), K 2 TiF 6: Mn 4 +, NaYF 4: Mn 4+, NaGdF 4: Mn 4 +

In addition, the wavelength converting part may be a wavelength converting material such as a quantum dot (QD) by replacing the fluorescent material or mixing with the fluorescent material.

22 is an exploded perspective view schematically illustrating a lamp including a communication module as a lighting device according to an embodiment of the present invention.

22, the lighting apparatus 2000 may include a socket 2010, a power supply unit 2020, a heat dissipation unit 2030, a light source module 2040, and a cover unit 2070.

The power supplied to the lighting apparatus 2000 can be applied through the socket 2010. [ The socket 2010 can be configured to be replaceable with a conventional lighting device. As shown in the figure, the power supply unit 2020 may be separately assembled into the first power supply unit 2021 and the second power supply unit 2022. The heat dissipating unit 2030 may include an internal heat dissipating unit 2031 and an external heat dissipating unit 2032. The internal heat dissipation unit 2031 may be directly connected to the light source module 2040 and / or the power supply unit 2020, and heat may be transmitted to the external heat dissipation unit 2032 through the internal heat dissipation unit 2031. The optical unit 2070 may be configured to evenly disperse the light emitted by the light source module 2040.

The light source module 2040 may receive power from the power source unit 2020 and emit light to the cover unit 2070. The light source module 2040 may include one or more light emitting devices 2041, a circuit board 2042 and a controller 2043 and the controller 2043 may store driving information of the light emitting devices 2041. The light emitting device 2041 may include a substrate manufactured according to the method of manufacturing a semiconductor substrate according to an embodiment of the present invention described above with reference to FIGS. 1 to 13B, or may be an element manufactured using the substrate.

The reflection plate 2050 is disposed on the upper part of the light source module 2040 and the reflection plate 2050 spreads the light from the light source evenly to the side and back to reduce glare. A communication module 2060 can be mounted on the upper part of the reflection plate 2050 and a home-network communication can be realized through the communication module 2060. For example, the communication module 2060 may be a wireless communication module using Zigbee, WiFi, or LiFi, and may turn on / off the lighting device through a smart phone or a wireless controller off, brightness control, and so on. Also, by using the LIFI communication module using the visible light wavelength of the illumination device installed inside or outside the home, it is possible to control electronic products and automobile systems inside and outside the home, such as a TV, a refrigerator, an air conditioner, a door lock, and a car. The reflection plate 2050 and the communication module 2060 can be covered by the cover portion 2070.

23 is an exploded perspective view schematically showing a bar-type lamp as a lighting device according to an embodiment of the present invention.

23, the lighting apparatus 3000 may include a heat dissipating member 3100, a cover 3200, a light source module 3300, a first socket 3400, and a second socket 3500.

A plurality of heat dissipation fins 3110 and 3120 may be formed on the inner and / or outer surfaces of the heat dissipating member 3100 and the heat dissipation fins 3110 and 3120 may be designed to have various shapes and intervals. A protruding support base 3130 is formed on the inner side of the heat radiation member 3100. The light source module 3430 may be fixed to the support base 3130. At both ends of the heat dissipating member 3100, a latching jaw 3140 may be formed.

The cover 3200 is formed with a latching groove 3210 and the latching jaw 3140 of the heat releasing member 35100 can be coupled to the latching groove 3210 in a hook coupling structure. The positions where the latching groove 3210 and the latching jaw 3140 are formed may be mutually changed.

The light source module 3300 may include a light emitting element array. The light source module 3300 may include a printed circuit board 3310, a light source 3320, and a controller 3330. The light source 3320 may include a substrate manufactured according to the method of manufacturing a semiconductor substrate according to an embodiment of the present invention described above with reference to FIGS. 1 to 13B, or may be an element manufactured using the substrate. The controller 3330 can store driving information of the light source 3320. [ Circuit wirings for operating the light source 3320 are formed on the printed circuit board 3310 and components for operating the light source 3320 may be included.

The first and second sockets 3400 and 3500 have a structure that is coupled to both ends of a cylindrical cover unit composed of the heat radiation member 3100 and the cover 3200 as a pair of sockets. For example, the first socket 3400 may include an electrode terminal 3410 and a power supply 3420, and a dummy terminal 3510 may be disposed in the second socket 3500. Further, the optical sensor and / or the communication module may be embedded in the socket of either the first socket 3400 or the second socket 3500. For example, the optical sensor and / or the communication module may be embedded in the second socket 3500 where the dummy terminal 3510 is disposed. As another example, the optical sensor and / or the communication module may be embedded in the first socket 3400 in which the electrode terminal 3410 is disposed.

24 schematically shows a lighting apparatus employing a light source module according to an embodiment of the present invention. The illumination device according to the present embodiment may include, for example, a rear lamp of an automobile.

24, the lighting apparatus 4000 includes a housing 4020 supporting the light source module 4010, a cover 4030 covering the housing 4020 to protect the light source module 4010, 4010 may be provided with a reflector 4040. The reflector 4040 includes a plurality of through holes 4042 provided on the bottom surfaces of the plurality of reflecting surfaces 4041 and the reflecting surfaces 4041 and the plurality of light emitting units 4200 of the light source module 4010 And can be exposed to the reflecting surface 4041 through the through holes 4042, respectively.

The illuminating device 4000 may have a gentle curved structure as a whole corresponding to the shape of the corner portion of the automobile so that the light emitting unit 4200 is assembled to the frame 4100 to match the curved structure of the illuminating device 4000 The light source module 4010 having the step structure corresponding to the curved surface structure can be formed. The structure of the light source module 4010 may be variously modified according to the design of the illumination device 4000, that is, the rear lamp. Also, the number of the light emitting units 4200 to be assembled may be variously changed.

In the present embodiment, the illumination device 4000 is a rear lamp of an automobile, but the present invention is not limited thereto. For example, the lighting device 4000 may include a headlight of an automobile and a turn signal light mounted on a door mirror of an automobile. In this case, the light source module 4010 may include a multi-stage May be formed to have a step structure.

25 is a schematic view for explaining an indoor lighting control network system;

The network system 5000 according to the present embodiment may be a complex smart lighting-network system in which lighting technology using light emitting devices such as LEDs, Internet (IoT) technology, and wireless communication technology are combined. The network system 5000 may be implemented using various lighting devices and wired / wireless communication devices, and may be realized by software for sensors, controllers, communication means, network control and maintenance, and the like.

The network system 5000 can be applied not only to a closed space defined in a building such as a home or an office, but also to an open space such as a park, a street, and the like. The network system 5000 can be implemented based on the object Internet environment so that various information can be collected / processed and provided to the user. The LED lamp 5200 included in the network system 5000 receives information about the surrounding environment from the gateway 5100 to control the illumination of the LED lamp 5200 itself, And may perform functions such as checking and controlling the operation status of other devices 5300-5800 included in the object Internet environment based on functions such as visible light communication.

25, the network system 5000 includes a gateway 5100 for processing data transmitted and received according to different communication protocols, an LED lamp (not shown) connected to the gateway 5100 in a communicable manner and including LED light emitting elements 5200 and a plurality of devices 5300-5800 connected to the gateway 5100 so as to be able to communicate with the gateway 5100 according to various wireless communication schemes. To implement the network system 5000 based on the object Internet environment, each of the devices 5300-5800, including the LED lamp 5200, may include at least one communication module. In one embodiment, the LED lamp 5200 may be communicatively coupled to the gateway 5100 by a wireless communication protocol such as WiFi, Zigbee, LiFi, etc., for which at least one communication module 5210 for the lamp Lt; / RTI &gt;

As described above, the network system 5000 can be applied to an open space such as a street or a park as well as a closed space such as a home or an office. When the network system 5000 is applied to the home, a plurality of apparatuses 5300-5800, which are included in the network system 5000 and are communicably connected to the gateway 5100 based on the object Internet technology, are connected to the television 5310 An electronic appliance 5300 such as a refrigerator 5320, a digital door lock 5400, a garage door lock 5500, a lighting switch 5600 installed on a wall, a router 5700 for wireless communication network relay, and a smart phone, A mobile device 5800 such as a computer, and the like.

In the network system 5000, the LED lamp 5200 can check the operation status of various devices 5300-5800 using a wireless communication network (Zigbee, WiFi, LiFi, etc.) installed in the home, The illuminance of the LED lamp 5200 itself can be automatically adjusted. Also, it is possible to control the devices 5300-5800 included in the network system 5000 by using LiFi communication using the visible light emitted from the LED lamp 5200.

The LED lamp 5200 is connected to the LED lamp 5200 based on the ambient environment transmitted from the gateway 5100 via the lamp communication module 5210 or the ambient environment information collected from the sensor mounted on the LED lamp 5200. [ ) Can be automatically adjusted. For example, the brightness of the LED lamp 5200 can be automatically adjusted according to the type of program being broadcast on the television 5310 or the brightness of the screen. To this end, the LED lamp 5200 may receive operational information of the television 5310 from the communication module 5210 for the lamp connected to the gateway 5100. [ The communication module 5210 for a lamp may be modularized as a unit with a sensor and / or a controller included in the LED lamp 5200. [

For example, when the program value of a TV program is a human drama, the lighting is lowered to a color temperature of 12000K or less, for example, 5000K according to a predetermined setting value, and the color is adjusted to produce a cozy atmosphere . In contrast, when the program value is a gag program, the network system 5000 can be configured such that the color temperature is increased to 5000 K or more according to the setting value of the illumination and adjusted to the white illumination of the blue color system.

In addition, when a certain period of time has elapsed after the digital door lock 5400 is locked in the absence of a person in the home, all the turn-on LED lamps 5200 are turned off to prevent electric waste. Alternatively, if the security mode is set via the mobile device 5800 or the like, the LED lamp 5200 may be kept in the turn-on state if the digital door lock 5400 is locked in the absence of a person in the home.

The operation of the LED lamp 5200 may be controlled according to the ambient environment collected through various sensors connected to the network system 5000. For example, if a network system 5000 is implemented in a building, it combines lighting, position sensors, and communication modules within the building, collects location information of people in the building, turns the lighting on or off, In real time to enable efficient use of facility management and idle space. Generally, since the illumination device such as the LED lamp 5200 is disposed in almost all the spaces of each floor in the building, various information in the building is collected through the sensor provided integrally with the LED lamp 5200, It can be used for space utilization and so on.

Meanwhile, by combining the LED lamp 5200 with the image sensor, the storage device, and the lamp communication module 5210, it can be used as an apparatus capable of maintaining building security or detecting and responding to an emergency situation. For example, when a smoke or a temperature sensor is attached to the LED lamp 5200, damage can be minimized by quickly detecting whether or not a fire has occurred. In addition, the brightness of the lighting can be adjusted in consideration of the outside weather and the amount of sunshine, saving energy and providing a pleasant lighting environment.

26 shows an embodiment of a network system applied to an open space.

Referring to FIG. 26, the network system 5000 'according to the present embodiment includes a communication connection device 5100', a plurality of lighting devices installed at predetermined intervals and connected to communicate with the communication connection device 5100 ' 5200 ', 5300', a server 5400 ', a computer 5500' for managing the server 5400 ', a communication base station 5600', a communication network 5700 ' Device 5800 ', and the like.

Each of a plurality of lighting devices 5200 ', 5300' installed in an open external space such as a street or a park may include a smart engine 5210 ', 5310'. The smart engines 5210 'and 5310' may include a light emitting device for emitting light, a driving driver for driving the light emitting device, a sensor for collecting information on the surrounding environment, and a communication module. The communication module enables the smart engines 5210 'and 5310' to communicate with other peripheral devices according to communication protocols such as WiFi, Zigbee, and LiFi.

In one example, one smart engine 5210 'may be communicatively coupled to another smart engine 5310'. At this time, the WiFi extension technology (WiFi mesh) may be applied to the communication between the smart engines 5210 'and 5310'. At least one smart engine 5210 'may be connected to the communication link 5100' connected to the communication network 5700 'by wire / wireless communication. In order to increase the efficiency of communication, several smart engines 5210 'and 5310' may be grouped into one group and connected to one communication connection device 5100 '.

The communication connection device 5100 'is an access point (AP) capable of wired / wireless communication, and can mediate communication between the communication network 5700' and other devices. The communication connection device 5100 'may be connected to the communication network 5700' by at least one of wire / wireless methods and may be mechanically housed in any one of the lighting devices 5200 ', 5300' have.

The communication connection 5100 'may be connected to the mobile device 5800' via a communication protocol such as WiFi. The user of the mobile device 5800'may collect a plurality of smart engines 5210'and 5310'through the communication connection 5100'connected to the smart engine 5210'of the adjacent surrounding lighting device 5200' It is possible to receive the surrounding information. The surrounding environment information may include surrounding traffic information, weather information, and the like. The mobile device 5800 'may be connected to the communication network 5700' in a wireless cellular communication manner such as 3G or 4G via the communication base station 5600 '.

On the other hand, the server 5400 'connected to the communication network 5700' receives the information collected by the smart engines 5210 'and 5310' mounted on the respective lighting apparatuses 5200 'and 5300' The operating state of the mechanisms 5200 'and 5300', and the like. In order to manage each luminaire 5200 ', 5300' based on the monitoring result of the operating condition of each luminaire 5200 ', 5300', the server 5400 'includes a computer 5500'Lt; / RTI &gt; The computer 5500 'may execute software or the like that can monitor and manage the operational status of each lighting apparatus 5200', 5300 ', particularly the smart engines 5210', 5310 '.

27 is a block diagram for explaining a communication operation between a smart engine and a mobile device of a lighting device by visible light wireless communication.

27, the smart engine 5210 'may include a signal processing unit 5211', a control unit 5212 ', an LED driver 5213', a light source unit 5214 ', a sensor 5215' . The mobile device 5800 'connected to the smart engine 5210' by visible light wireless communication includes a control unit 5801 ', a light receiving unit 5802', a signal processing unit 5803 ', a memory 5804', an input / output unit 5805 '), and the like.

The visible light wireless communication (LiFi) technology is a wireless communication technology that wirelessly transmits information by using visible light wavelength band visible to the human eye. Such visible light wireless communication technology is distinguished from existing wired optical communication technology and infrared wireless communication in that it utilizes light of a visible light wavelength band, that is, a specific visible light frequency from the light emitting package described in the above embodiment, It is distinguished from wired optical communication technology. In addition, unlike RF wireless communication, visible light wireless communication technology has the advantage that it can be freely used without being regulated or licensed in terms of frequency utilization, has excellent physical security, and has a difference in that a user can visually confirm a communication link. And has the characteristic of being a convergence technology that can obtain the intrinsic purpose of the light source and the communication function at the same time.

The signal processing unit 5211 'of the smart engine 5210' can process data to be transmitted / received through visible light wireless communication. In one embodiment, the signal processing unit 5211 'may process the information collected by the sensor 5215' into data and transmit it to the control unit 5212 '. The control unit 5212 'can control the operations of the signal processing unit 5211' and the LED driver 5213 ', and in particular, the operation of the LED driver 5213' based on the data transmitted by the signal processing unit 5211 ' Can be controlled. The LED driver 5213 'can transmit data to the mobile device 5800' by emitting the light source 5214 'according to a control signal transmitted from the controller 5212'.

The mobile device 5800 'includes a control unit 5801', a memory 5804 'for storing data, an input / output unit 5805' including a display, a touch screen, and an audio output unit, a signal processing unit 5803 ' And a light receiving unit 5802 'for recognizing visible light included in the light receiving unit 5802'. The light receiving unit 5802 'can detect visible light and convert it into an electric signal, and the signal processing unit 5803' can decode data included in the electric signal converted by the light receiving unit. The control unit 5801 'may store the decoded data of the signal processing unit 5803' in the memory 5804 ', or may output the decoded data to the user through the input / output unit 5805'.

The present invention is not limited by the above-described embodiment and the accompanying drawings, but is intended to be limited by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

Claims (20)

Forming a buffer layer on the growth substrate;
Forming a plurality of openings in the buffer layer spaced apart from each other through the buffer layer;
Forming a plurality of cavities on the growth substrate under the plurality of openings;
Forming a semiconductor layer growing from the buffer layer and filling the plurality of openings and extending to the top of the buffer layer; And
And separating the buffer layer and the semiconductor layer from the growth substrate by stress acting on the plurality of cavities,
Wherein a diameter of the plurality of openings is smaller than a diameter of the plurality of cavities at a boundary between the growth substrate and the buffer layer.
The method according to claim 1,
And the buffer layer protrudes from the growth substrate in the plurality of cavities to form an undercut region.

The method according to claim 1,
Wherein the plurality of cavities are covered with the semiconductor layer to form closed regions between the semiconductor layer and the growth substrate.
The method according to claim 1,
Wherein cracks are generated in the lateral direction along a boundary between the buffer layer and the growth substrate from the plurality of cavities in the separating step.
The method according to claim 1,
Wherein the plurality of openings are formed by a dry etching process, and the plurality of cavities are formed by a wet etching process.
The method according to claim 1,
Wherein the plurality of openings and the plurality of cavities are formed in a single process.
The method according to claim 1,
Wherein the plurality of cavities are defined by the surfaces along the crystal faces of the growth substrate.
8. The method of claim 7,
Wherein each of the plurality of cavities is defined by seven or more faces.
The method according to claim 1,
Wherein one surface of the growth substrate connected to the buffer layer in the plurality of cavities is a negative inclined surface.
The method according to claim 1,
Wherein the plurality of cavities are formed only in a partial region of the growth substrate.
11. The method of claim 10,
Wherein in the separating step, the semiconductor layer starts to separate from the partial region in which the plurality of cavities are formed.
The method according to claim 1,
And controlling the thickness of the semiconductor layer grown before the semiconductor layer is separated from the growth substrate by adjusting the size and density of the plurality of openings.
The method according to claim 1,
Further comprising forming a growth inhibiting layer on a surface of the growth substrate exposed through the plurality of cavities.
14. The method of claim 13,
Wherein forming the growth inhibiting layer comprises:
And treating the growth substrate with ammonia.
Forming a buffer layer on the growth substrate;
Forming a plurality of openings in the buffer layer spaced apart from each other through the buffer layer;
Forming a plurality of cavities on the growth substrate under the plurality of openings;
Forming a semiconductor layer growing from the buffer layer and filling the plurality of openings and extending to the top of the buffer layer; And
And separating the buffer layer and the semiconductor layer from the growth substrate by stress acting on the plurality of cavities.
16. The method of claim 15,
And the buffer layer protrudes from the growth substrate in the plurality of cavities to form an undercut region.
Providing a stacked structure of a growth substrate and a buffer layer;
Forming a plurality of openings that extend through the buffer layer into the growth substrate and are spaced apart from each other;
Growing a semiconductor layer from the buffer layer such that a plurality of cavities are formed in the growth substrate; And
And separating the buffer layer and the semiconductor layer from the growth substrate by stress acting on the plurality of cavities.
A growth substrate having a plurality of cavities spaced apart from each other on one surface; And
And a buffer layer disposed on the growth substrate and having a plurality of openings arranged to correspond to the plurality of cavities,
Wherein a diameter of the plurality of openings is smaller than a diameter of the plurality of cavities at a boundary between the growth substrate and the buffer layer.
19. The method of claim 18,
Wherein the plurality of cavities are disposed only in a partial region of the growth substrate.
19. The method of claim 18,
Wherein the growth substrate is a silicon wafer, and the buffer layer is a group III nitride.

Images