KR20160112102A - Semiconductor device - Google Patents

Abstract

According to the present invention, a semiconductor device has a plurality of global lines. The global lines are dispersed on a plurality of metal layers divided into an upper part and a lower part by interposing an interlayer insulating film therebetween. The global lines disposed on the lower metal layers are disposed to horizontally overlap a portion of the global lines disposed on the upper metal layers. The global line having a relatively long length among the global lines can be disposed on the upper metal layer, rather than the global line having a relatively short length. The semiconductor device can reduce noise caused by interference between the global lines.

Description

Technical Field [0001] The present invention relates to a semiconductor device,

The present invention relates to semiconductor design techniques.

A semiconductor device includes a global line corresponding to a data transmission path as well as circuits such as a sense amplifier, a comparator, and a driver for data transmission / reception with the outside.

Embodiments of the present invention provide a semiconductor device that can improve layout area efficiency and reduce loading differences between global lines.

A semiconductor device according to an embodiment of the present invention includes a plurality of global lines. The global lines are dispersedly disposed on a plurality of metal layers separated by upper and lower layers under the interlayer insulating film and the global line disposed on the lower metal layer is disposed so as to overlap with a part of the global line arranged on the upper metal layers , And a global line having a relatively long length among the global lines may be arranged in an upper metal layer than a global line having a relatively short length.

The global line disposed on the uppermost layer among the global lines may be disposed in the same metal layer as the pad.

The global lines may be configured such that the global line disposed on the lower metal layer has a smaller line width than the global line disposed on the upper metal layer.

The semiconductor device may further include contact plugs which penetrate the interlayer insulating film and connect local lines formed in the metal layers under the global lines and the global lines.

The global lines may be configured such that one end of a global line disposed on an upper metal layer is offset planarly with respect to global lines disposed on the lower metal layers and the contact plug is connected to the one end have.

The global lines may be arranged such that global lines arranged in upper and lower neighboring metal layers are alternately arranged in a plane.

According to this technology, global lines are distributed over a plurality of metal layers and global lines arranged on different layers are overlapped with each other, so that the area of a region where global lines are arranged can be reduced, .

In addition, by arranging a relatively long global line in the upper metal layer having a large line width and a relatively short global line in the lower metal layer having a small line width, the loading difference due to the difference in the length between the global lines is compensated Skew can be prevented. In addition, it is unnecessary to further form a dunmmy line to compensate for the difference in loading due to the difference in length between the global lines. Therefore, the area loss due to the formation of the dummy line can be reduced and the layout area efficiency of the semiconductor device can be increased.

In addition, in order to secure space for the contact plug connecting the global line and the local line disposed on the upper metal layer, the global line disposed on the lower metal layer is not bent, Since one end portion is offset to one side with respect to the global lines disposed on the lower metal layers to secure a space for the contact plug, space loss due to the formation of the global line can be prevented, Area efficiency can be increased.

In addition, since the global lines arranged in the upper and lower neighboring metal layers can be arranged alternately in a planar manner, the distance between the global lines can be increased, thereby reducing the noise due to the interference between the global lines.

1 is a plan view of a global line according to an embodiment of the present invention.
2 is a cross-sectional view taken along line AA 'of FIG.
3 is a cross-sectional view taken along line BB 'of FIG.
4 is a plan view of a global line according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plan view showing a global line according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A 'of FIG. 1, and FIG. 3 is a sectional view taken along line B-B' of FIG.

1, a semiconductor device may include a memory cell region CELL in which a plurality of memory banks (not shown) are disposed, and a peripheral circuit region PERI disposed outside the memory cell region CELL .

1 to 3, a semiconductor element (not shown) may be formed on the surface portion of the substrate 10 of the memory cell region CELL and the peripheral circuit region PERI. On the substrate 10, A plurality of metal layers M1 to M5 separated upward and downward can be formed with intervening layers ILD1 to ILD5. Hereinafter, a plurality of metal layers M1 to M5 will be defined as first to fifth metal layers.

Local lines SL electrically connected to the semiconductor device may be disposed in the first metal layer M1 and global lines GIO1 through GIO256 may be disposed in the second through fifth metal layers M2 through M5. .

The global lines (GIOl to GIO256) have a relatively long length and may be disposed across a plurality of memory banks and shared by a plurality of memory banks. The local lines SL have a relatively short length and are arranged between a predetermined memory bank and a global line to connect a predetermined memory bank and a global RAM.

A first interlayer insulating film ILD1 covering the semiconductor element is formed on the substrate 10 and a second interlayer insulating film ILD2 covering the local line SL is formed on the first interlayer insulating film ILD1, 193 to 256 global lines (GIO193 to GIO256) may be arranged in the second metal layer M2 formed on the first metal layer ILD2. A third interlayer insulating film ILD3 covering the second metal layer M2 is formed on the second interlayer insulating film ILD2 and a third metal layer M3 formed on the third interlayer insulating film ILD3 is formed on the third interlayer insulating film ILD3, Global lines (GIO 129 to GIO 192) can be arranged. A fourth interlayer insulating film ILD4 covering the third metal layer M3 is formed on the third interlayer insulating film ILD3 and a fourth interlayer insulating film ILD4 is formed on the fourth metal layer M4 formed on the fourth interlayer insulating film ILD4. Global lines (GIO65 to GIO128) can be arranged. A fifth interlayer insulating film ILD5 covering the fourth metal layer M4 is formed on the fourth interlayer insulating film ILD4 and a fifth metal layer M5 formed on the fifth interlayer insulating film ILD5 is formed. The 64th global lines (GIOl to GIO64) may be arranged. The fifth metal layer M5 is the uppermost metal layer. The fifth metal layer M5 of the peripheral circuit region PERI includes data input / output pads for exchanging data with an external device, a power source And a plurality of pads (PADs) including ground pads for inputting a ground voltage and a pad. Although not shown, a protective layer may be formed on the fifth interlayer insulating film ILD5 to cover the first to 64th global lines GIO1 to GIO64 and expose the pads PAD.

Although the global line is arranged in the peripheral circuit area PERI in the embodiment shown in the drawings, the present invention is not limited to this, and the global line may be arranged in the cell area CELL as well as the peripheral circuit area PERI. .

The global line is a data transmission path between a data input / output pad and a local line (SL). The global line is a data transmission path between a data input / output pad and a local line (SL) , 32 lines, 64 lines, 128 lines and 256 lines. The present embodiment shows a case where 256 global lines are configured to support all the operation modes of x8, x16, x32, x64, x128 and x256.

The 65th to 128th global lines GIO65 to GIO128 arranged in the fourth metal layer M4 are divided into a part of the first to 64th global lines GIO1 to GIO64 arranged in the fifth metal layer M5, They can be arranged to overlap. The 129th to 192nd global lines GIO129 to GIO192 arranged in the third metal layer M3 are arranged in the order of the 65th to 128th global lines GIO65 to GIO128 arranged in the fourth metal layer M4 And the 193rd to 256th global lines (GIO193 to GIO256) arranged in the second metal layer (M2) can be arranged so as to overlap with the 129th to 192th global And may overlap with a part of the lines GIO129 to GIO192.

That is, the global lines arranged in the lower metal layer can be arranged so as to overlap with a part of the global lines arranged in the upper metal layer in a plan view. Accordingly, the global lines are distributed over a plurality of metal layers, and the global lines arranged on different layers are overlapped with each other, thereby reducing the area where the global lines are arranged, thereby increasing the layout area efficiency of the semiconductor device .

In the case of the local line SL formed in the first metal layer M1 which is the lowermost metal layer, the local line SL is designed to have a small line width for electrical connection with the semiconductor element patterned at a fine pitch. In order to prevent the signal speed from lowering due to line loading, it is designed to have an increased line width toward the upper metal layer, so that the first through 64th global layers formed in the fifth metal layer M5, which is the uppermost metal layer, The lines GIO1 to GIO64 are designed to have the largest line width. If the line width of the local line SL disposed in the first metal layer M1 is D1 and the line width of the 193rd to 256th global lines GIO193 to GIO256 disposed in the second metal layer M2 is D2 The line widths of the 129th to 192nd global lines GIO129 to GIO192 arranged in the third metal layer M3 are D3 and the 65th to 128th global lines GIO65 to GIO128 arranged in the fourth metal layer M4 D5> D4> D3> D2> D1 where D5 is the line width of the first to seventh global lines GIO1 to GIO64 arranged in the fifth metal layer M5, Can be satisfied.

Since the global lines SL and the data input / output pads PAD are connected to different local lines SL and the data input / output pads PAD are provided for each of the global lines GIO1 through GIO256, The lengths of the global lines GIO1 to GIO256 may not be constant, and thus a loading difference may occur between the global lines.

In order to prevent the loading difference due to the difference in length between the global lines (GIO1 to GIO256), relatively long global lines may be disposed on the upper metal layer and relatively shorter global lines may be disposed on the lower metal layer. That is, the length of the 193rd to 256th global lines (GIO193 to GIO256) disposed in the second metal layer (M2) is L2, the length of the 129th to 192th global lines (GIO129 The length of each of the 65th to 128th global lines GIO65 to GIO128 arranged in the fourth metal layer M4 is L4 and the length of each of the 65th to 128th global lines GIO65 to GIO128 arranged in the fourth metal layer M4 is L4, When the length of 64 global lines (GIO1 to GIO64) is defined as L5, the relationship of L5> L4> L3> L2 can be satisfied.

Accordingly, by arranging a relatively long global line in an upper metal layer having a large line width and a relatively short global line in a lower metal layer having a small line width, a loading difference due to a difference in length between global lines is compensated Skew can be prevented. In addition, since there is no need to additionally form a dummy line to compensate for the loading difference due to the difference in length between the global lines, it is possible to reduce the area loss due to the formation of the dummy line addition, thereby increasing the layout area efficiency of the semiconductor device.

The global lines GIO1 to GIO256 are arranged in a straight line parallel to one direction. In order to secure a space for a contact connecting the global line and the local line SL disposed on the upper metal layer, The lines may be arranged to be offset to one side with respect to the global lines formed in the lower metal layers in a plan view. The contact plugs CNT1, CNT2, CNT3, and CNT4 connecting the global lines and the local lines SL are connected to the interlayer insulating film disposed between the global lines GIO1 to GIO256 and the first metal layer M1, Can be formed.

Specifically, the first to 64th global lines GIO1 to GIO64 arranged in the fifth metal layer M5 are arranged in the order of the 65th to 256th global lines arranged in the fourth to the second metal layers M4 to M2, And the second to fifth interlayer insulating films ILD2 to ILD5 disposed between the fifth metal layer M5 and the first metal layer M1 may be offset to one side with respect to the first to fifth metal layers GIO65 to GIO256. First contact plugs CNT1 may be formed to connect between the offset line of the 64th global lines GIO1 to GIO64 and the local line SL. The 65th to 128th global lines (GIO65 to GIO128) arranged in the fourth metal layer (M4) are arranged in the order from the 129th to 256th global lines arranged in the third to the second metal layers (M3 to M2) And the second to fourth interlayer insulating films ILD2 to ILD4 disposed between the fourth metal layer M4 and the first metal layer M1 may be offset to one side with respect to the first to third metal layers GIO129 to GIO256. The second contact plugs CNT2 may be formed to connect the offset one end of the 128 global lines (GIO65 to GIO128) and the local line (SL). The 129th to 192nd global lines GIO129 to GIO192 arranged in the third metal layer M3 are arranged in the order from the 193rd to 256th global lines GIO193 to GIO256 arranged in the second metal layer M2, And the second to third interlayer insulating films ILD2 to ILD3 disposed between the third metal layer M3 and the first metal layer Ml may be offset to one side with respect to the 129th to 192nd global lines GIO129 Third contact plugs CNT3 may be formed to connect the offset end of the first contact plugs GIO192 and the local line SL. The second interlayer insulating film ILD2 disposed between the second metal layer M2 and the first metal layer M1 is connected to the local lines SL through the 193rd to 256th global lines GIO193 to GIO256, The fourth contact plugs CNT4 may be formed.

Accordingly, in order to secure a space for a contact connecting the global line and the local line SL disposed in the upper metal layer, the global line disposed in the lower metal layer is not bent, Since the space for the contact plug can be ensured by disposing the lines at one side offset from the global lines disposed on the lower metal layers, space loss due to the formation of the global line can be prevented, The layout area efficiency of the device can be increased.

FIG. 4 is a plan view showing a global line according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line C-C 'of FIG. For the sake of convenience of description, the same components as those of FIG. 1 to FIG. 3 are denoted by the same reference numerals, and a duplicated description of the same components will be omitted.

4 and 5, the first to 64th global lines GIO1 to GIO64 may be arranged in one direction in the fifth metal layer M5, and the 65th to 128th The global lines GIO65 to GIO128 may be disposed in a planar fashion to the first to 64th global lines GIO1 to GIO64. The 129th to 192rd global lines (GIO129 to GIO192) may be arranged in the third metal layer (M3) alternately with the 65th to 128th global lines (GIO65 to GIO128), and the second metal layer M2, the 193rd to 256th global lines (GIO193 to GIO256) can be arranged alternately with the 129th to 192th global lines (GIO129 to GIO192) in a plan view.

Therefore, since the global lines disposed in the upper and lower neighboring metal layers can be alternately arranged in a planar manner, the distance between the global lines can be increased, thereby reducing the noise due to the interference between the global lines.

To increase the layout area efficiency, the 129th to 192nd global lines (GIO129 to GIO192) arranged in the third metal layer (M3) are connected to the first to 64th global lines (GIO1 And GIO193 to GIO256 arranged in the second metal layer M2 are arranged to overlap with a part of the 65th to 128th global lines GIO19 to GIO64 arranged in the fourth metal layer M4, Line GIO65 to GIO128.

According to the above-described embodiments, the global lines are distributed over a plurality of metal layers and the global lines arranged in different layers are overlapped with each other, so that the area of the area where the global lines are arranged can be reduced, Area efficiency can be increased.

In addition, by arranging a relatively long global line in the upper metal layer having a large line width and a relatively short global line in the lower metal layer having a small line width, the loading difference due to the difference in the length between the global lines is compensated Skew can be prevented. In addition, it is unnecessary to further form a dunmmy line to compensate for the difference in loading due to the difference in length between the global lines. Therefore, the area loss due to the formation of the dummy line can be reduced and the layout area efficiency of the semiconductor device can be increased.

In addition, in order to secure space for the contact plug connecting the global line and the local line disposed on the upper metal layer, the global line disposed on the lower metal layer is not bent, Since one end portion is offset to one side with respect to the global lines disposed on the lower metal layers to secure a space for the contact plug, space loss due to the formation of the global line can be prevented, Area efficiency can be increased.

In addition, since the global lines arranged in the upper and lower neighboring metal layers can be arranged alternately in a planar manner, the distance between the global lines can be increased, thereby reducing the noise due to the interference between the global lines.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood that the invention can be variously modified and changed without departing from the technical scope thereof.

10: substrate
ILD1 to ILD5: First to fifth interlayer insulating films
SL: Local line
M1 to M5: first to fifth metal layers
GIO1 to GIO256: First to 256th global lines
PAD: Pad
CNT1 to CNT4: First to fourth contact plugs

Claims (6)

1. A semiconductor device comprising a plurality of global lines,
The global lines are distributed and arranged in a plurality of metal layers separated vertically under an interlayer insulating film, and a global line arranged on the lower metal layer is arranged in a plane so as to overlap with a part of a global line arranged on the upper metal layers And a global line having a relatively long length among the global lines is arranged in an upper metal layer than a global line having a relatively short length. The semiconductor device according to claim 1, wherein the global line disposed on the uppermost layer among the global lines is disposed in the same metal layer as the pad. The semiconductor device of claim 1, wherein the global lines are configured such that a global line disposed on a lower metal layer has a line width smaller than a global line disposed on an upper metal layer. The semiconductor device according to claim 1, further comprising contact plugs penetrating the interlayer insulating film and connecting local lines formed in the metal layers under the global lines and the global lines. 5. The semiconductor memory device according to claim 4, wherein the global lines are configured such that one end of a global line disposed on an upper metal layer is offset to one side with respect to global lines arranged in the lower metal layers in a plan view, To the semiconductor device. The semiconductor device according to claim 1, wherein the global lines are arranged so that global lines arranged in upper and lower neighboring metal layers are alternately arranged in a planar manner.

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