KR20160083577A - Display Device - Google Patents

Abstract

A display device of the present invention includes a display panel, a data driving part, a boost convertor, a PWM control part, and a timing controller. A data line is arranged on the display panel. The data driving part provides a data voltage to the data line. The boost convertor includes a switch element and outputs a reference voltage for setting a data voltage according to the turn-on and turn-off ratio of the switch element as an output voltage. The PWM control part changes the frequency of the switch element. The timing controller sets a range of changing a vertical black period into an image display period as a frequency change range, and controls the PWM control part to increase the switching frequency of the switching element during the frequency change range. So, the distortion of a data voltage can be prevented when the load of a current is suddenly changed.

Description

[0001]

The present invention relates to a display device.

The flat panel display includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode (OLED) ). In the flat panel display device, the data lines and the gate lines are arranged to be orthogonal to each other, and the region where the data lines and the gate lines are orthogonal is defined as one pixel. A plurality of pixels are formed in a matrix form in the panel. In order to drive the respective pixels, video data voltages to be displayed are supplied to the data lines and gate pulses are sequentially supplied to the gate lines. The video data voltage is supplied to the pixels of the display line to which the gate pulse is supplied, and all the display lines are sequentially scanned by the gate pulse to display the video data.

The display device displays an image during a video display period of the frame, and has a vertical blank period in which no image is displayed between frames. Therefore, the data driver does not continuously output the data voltage for displaying the image, but has a rest period for outputting the data voltage. The load of the current suddenly changes between the period during which the data driver outputs the data voltage and the period during which the data voltage is not output. The data voltage is also distorted as the load of the current rapidly changes. When the data voltage is distorted, there occurs a problem that the display quality is degraded in displaying an image based on the distorted data voltage.

It is an object of the present invention to provide a display device for improving the distortion of a data voltage when a load of a current is suddenly changed.

A display device of the present invention includes a display panel, a data driver, a boost converter, a PWM controller, and a timing controller. Data lines are arranged in the display panel. The data driver provides the data voltage to the data line. The boost converter includes a switch element, and outputs a reference voltage for setting the data voltage in accordance with the turn-on and turn-off ratios of the switch element to the output voltage. The PWM control unit varies the frequency of the switch element. The timing controller sets the section that changes from the vertical blank period to the video display period to the frequency variable section and controls the PWM control section to increase the switching frequency of the switching element during the frequency variable section.

The present invention can improve the switching speed of the switch element of the boost converter in a period in which the output of the data voltage is rapidly increased, thereby preventing the distortion of the output voltage. Therefore, the present invention can improve the degradation of the display quality due to distortion of the output voltage.

1 is a view showing a display device according to the present invention.
2 and 3 are views showing the configuration of a data driver of the present invention.
4 shows a boost converter according to the invention;
5 and 6 are waveform diagrams showing output voltages according to the switching frequency.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Although the present invention has been described on the basis of an embodiment of a liquid crystal display device, the present invention can be applied to a field emission display (FED), a plasma display panel (PDP) and an organic light emitting diode Organic Light Emitting Diode Device (OLED), and the like.

1 is a view showing a liquid crystal display device according to the present invention. 2 and 3 are views showing the configuration of the source drive IC.

Referring to FIG. 1, the liquid crystal display of the present invention includes a display panel 100, source drive ICs 500, a level shifter 410, a shift register 420, a timing controller 300, and the like.

The display panel 100 includes a pixel array in which pixels arranged in a matrix form are formed to display input image data. The pixel array includes a TFT array formed on the lower substrate, a color filter array formed on the upper substrate, and liquid crystal cells (Clc) formed between the lower substrate and the upper substrate. The TFT array is provided with a data line DL, a gate line GL which intersects the data line DL, TFTs formed at intersections of the data line DL and the gate line GL, pixel electrodes 1 ), A storage capacitor (Cst), and the like are formed. In the color filter array, a color filter array including a black matrix and a color filter is formed. The common electrode 2 may be formed on the lower substrate or the upper substrate. The liquid crystal cells Clc are driven by the electric field between the pixel electrode 1 to which the data voltage is supplied and the common electrode 2 to which the common voltage Vcom is supplied. On the upper substrate and the lower substrate of the display panel 100, a polarizing plate whose optical axis is orthogonal is attached, and an alignment film for setting a pre-tilt angle of the liquid crystal is formed at the interface with the liquid crystal layer. Between the upper substrate and the lower substrate of the display panel 100, a spacer for maintaining a cell gap of the liquid crystal layer is disposed.

The power module 200 starts to operate when the input voltage Vin supplied through the connector 5 is equal to or higher than the UVLO level and generates an output after a predetermined time delay. The output of the power module 200 includes VGH, VGL, VCC, VDD, RST, and the like. VCC may be a voltage of 3.3 V as a logic power supply voltage for driving the timing controller 300, the source drive IC 500, and the like. VDD is a high potential supply voltage to be supplied to the voltage divider circuit of the gamma reference voltage generating circuit that generates the positive / negative gamma reference voltages. The positive / negative gamma reference voltages are supplied to the source drive IC 500. RST is a reset signal for resetting the timing controller 300, and may be 3.3V.

The power module 200 includes a boost circuit for generating the high potential voltage VDD. The boost circuit controls the output voltage of the boost circuit on the basis of the control signal Sf provided from the timing controller 300. A detailed description thereof will be described later.

The timing controller 300 receives the digital video data RGB from an external host through the connector 5 and receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal Data Enable, And receives a timing signal such as the main clock CLK. The timing controller 300 transmits digital video data (RGB) to the source drive ICs 500. The timing controller 300 uses a timing signal Vsync, Hsync, DE, and CLK to control a source timing control signal for controlling the operation timing of the source drive IC 500, a level shifter 410 for a gate drive circuit, And generates gate timing control signals (ST, GCLK, MCLK) for controlling the operation timing of the register 420. [

The timing controller 300 generates the control signal Sf based on the vertical synchronization signal Vsync and provides the control signal Sf to the power module 200. [ The control signal Sf serves as a reference for the power module 200 to select the switching frequency. A detailed description thereof will be described later.

The data driver includes a plurality of source drive ICs (Integrated Circuits) 24. The source drive IC 500 receives the digital video data RGB from the timing controller 300. The source driver IC 500 converts the digital video data RGB into a positive / negative polarity analog data voltage in response to a source timing control signal from the timing controller 300, To the data lines (DL) of the display panel 100 so as to be synchronized with the pulses.

2, each source driver IC 500 includes a register unit 510, a first latch 520, a second latch 530, a digital-to-analog converter (DAC) (540) and an output unit (550). The register unit 510 samples the RGB digital video data bits of the input image using the data control signals SSC and SSP supplied from the timing controller 300 and provides the sampled RGB digital video data bits to the first latch 520. The first latch 520 samples and latches the digital video data bits according to the clocks sequentially supplied from the register unit 510, and simultaneously outputs the latched data. The second latch 530 latches the data provided from the first latch 520 and in response to the source output enable signal SOE synchronously with the second latch 530 of the other source drive ICs 500, Simultaneously output one data. The DAC 540 converts the video data input from the second latch unit 530 into a gamma compensation voltage (GMA) to generate an analog video data voltage. The output section 550 provides the analog data voltage ADATA output from the DAC 540 to the data lines DL during the low logic period of the source output enable signal SOE. The output unit 550 may be implemented as an output buffer that outputs a data voltage using a driving voltage, which is input through a low potential GND and a high potential input terminal.

Referring to FIG. 3, the gamma reference voltage generating circuit includes a resistor string and first to ninth voltage followers GMA1 to GMA9. The resistor string includes first to eighth resistors R1 to R8. The resistor string divides the low potential voltage (GND) and the high potential voltage (VDD). The high-potential voltage VDD is an output voltage Vout output from the output terminal Nout of the power module 200. The first to ninth voltage followers GMA1 to GMA9 enhance first to ninth gamma voltages gamma1 to gamma9 by enhancing the distributed voltages output from the nodes between the resistors.

The GIP type gate drive circuit includes a level shifter 410 and a shift register 420 mounted on a printed circuit board (PCB).

The level shifter 410 receives a start pulse ST, a first clock GCLK, a second clock MCLK, and the like from the timing controller 300. The level shifter 410 is also supplied with driving voltages such as the gate high voltage VGH and the gate low voltage VGL. The start pulse (ST), the first clock (GCLK), and the second clock (MCLK) swing between 0V and 3.3V. The level shifter 410 receives the gate high voltage VGH and the gate low voltage VGL in response to the start pulse ST, the first clock GCLK and the second clock MCLK input from the timing controller 300, And outputs the start pulse VST and the clock signals CLK1 to CLK6. The clock signals CLK output from the level shifter 410 are sequentially shifted in phase and transferred to the shift register 420 formed on the display panel 100. [

The shift register 420 is connected to the gate lines GL of the display panel 100. [ The shift register 420 includes a plurality of stages that are connected in a dependent manner. The shift register 420 shifts the start pulse VST input from the level shifter 410 according to the clock signal CLK to sequentially supply gate pulses to the gate lines GL.

4 is a view showing a power module of the present invention.

Referring to FIG. 2, the power module 200 includes a boost circuit 211, a voltage distribution unit 213, and a PWM control unit 215.

The boost circuit 211 outputs a DC voltage obtained by adding the input voltage VIN. The boost circuit 211 includes a boost inductor L, a switch element SW1, a rectifier diode D, and an output capacitor C.

The switch element SW1 is turned on or off by the control signal Sf supplied from the PWM controller 215. [ The switch element SW1 controls the output voltage in accordance with the ratio of the turn-on period and the turn-off period. When the switch element SW1 is turned on, the rectifier diode D becomes reverse biased, and current flows through the boost inductor L and the switch element SW1 so that the voltage of the boost inductor L increases. The current flowing in the boost inductor L and the switch element SW1 linearly increases to form an electromagnetic field. The current path via the rectifier diode D is cut off while the switch element SW1 is turned on and the voltage stored in the output capacitor C is outputted as the output voltage Vout. When the switch element SW1 is turned off, a current flows from the boost inductor L to the output terminal Nout via the rectifier diode D. [

The voltage distribution unit 213 provides the PWM control unit 215 with the feedback voltage 213 obtained by dividing the output voltage Vout of the boost circuit 211. [ The voltage divider 213 may be implemented as a resistor string connected in series between the output terminal Nout and the base power supply. The feedback voltage VFB divided by the first and second resistors R1 and R2 of the resistor string is output through the node between the first and second resistors R1 and R2.

The PWM controller 215 outputs the first or second switching signals PWM1 and PWM2 based on the feedback voltage Vfb supplied from the voltage distributor 213. [ The PWM control unit 215 outputs the first switching signal PWM1 while the control signal Sf is not supplied from the timing controller 300 and outputs the second switching signal PWM2 when receiving the control signal Sf Output. The first switching signal PWM1 and the second switching signal PWM2 control the switch element SW1 to be turned on and turned off at regular intervals, respectively. The second switching signal PWM2 has a higher frequency than the first switching signal PWM1. The control signal Sf is outputted in the vertical blank period Tb and consequently the PWM control unit 215 controls the switching element SW1 at a higher frequency in the vertical blank period Tb than the video display period Tdp.

The second switching signal PWM2 having a high frequency in contrast to the first switching signal PWM1 can improve the occurrence of the voltage drop phenomenon in the vertical blank period Tb. Referring to FIGS. 5 and 6, a description will be made as follows.

5 is a diagram showing a change in the output voltage in the process of controlling the boost circuit by using the first switching signal PWM1 having the frequency of the switching signal unchanged, for example, the first switching frequency fs1 .

The voltage output through the output terminal Nout of the power module 200 shown in FIG. 4 is provided to the gamma reference voltage generating circuit shown in FIG. The gamma reference voltage generating circuit generates the gamma reference voltage gamma by using the output voltage Vout as the high potential voltage. The gamma reference voltage gamma becomes a reference voltage for generating a data voltage output from the data line DL.

The data line DL outputs the data voltage during the video display period Tdp and does not output the data voltage during the vertical blank period Tb. Therefore, the power consumption increases at a moment when the display period is changed from the vertical blank period Tb to the video display period Tdp. The amount of charge stored in the capacitor C of the boost circuit 211 is drastically reduced when the power consumption surges. Since the amount of charge stored in the capacitor C and the output voltage Vout are proportional to each other, a voltage drop phenomenon Vdrop occurs in which the output voltage Vout decreases as the amount of charge stored in the capacitor C decreases.

As a result, the output voltage Vout sharply decreases at the instant of changing from the vertical blank period to the image display period. Since the output voltage Vout is used as the reference voltage of the data voltage, the data voltage is also distorted in a period in which the output voltage Vout rapidly varies. As a result, the voltage drop phenomenon causes a deterioration of the image display quality.

6 is a diagram illustrating a method for varying the switching frequency according to the present invention. 6, the first switching frequency fs1 represents the switching frequency of the first switching signal PWM1 and the second switching frequency fs2 represents the switching frequency of the second switching signal PWM2. That is, the display device of the present invention increases the switching frequency in order to alleviate the decrease of the output voltage Vout at the moment of changing from the vertical blank period Tb to the image display period Tdp.

As the switching frequency of the switch element SW1 increases, the amount of current supplied from the boost inductor L to the capacitor C increases. Since the amount of charge charged in the capacitor C is proportional to the amount of change in the amount of current, when the amount of current supplied to the capacitor C increases, the amount of charge charged in the capacitor C also increases.

That is, when the second switching frequency fs2 having a higher frequency than the first switching frequency fs1 is used, the amount of charge charged in the capacitor C increases. Therefore, even if the charge discharge rapidly increases from the capacitor C to the output terminal Nout, the amount of charge on the capacitor C does not decrease sharply. The switching element SW1 is controlled using the second switching frequency fs2 having a high switching frequency so that the voltage drop phenomenon Vdrop in which the output voltage Vout decreases due to the decrease in the amount of charge stored in the capacitor C, .

The frequency variation section Tfc using the second switching frequency fs2 will be described below. As described above, the voltage drop phenomenon Vdrop occurs at the moment when the vertical blank period Tb is changed to the image display period Tdp. Therefore, the frequency variable section Tfc starts before the vertical blank period Tb ends. The period in which the vertical synchronization signal Vsync is output is included in the vertical blank period Tb. Based on this, the timing controller 300 sets the time point at which the vertical synchronization signal Vsync is output for the first predetermined time? 1 as the start of the frequency variable section Tfc. If the first predetermined time? 1 is too long, since the start time of the frequency variable section Tfc may be after the vertical blank section Tb has passed, the first predetermined time? Vsync) is set to be shorter than the period corresponding to the pulse width of Vsync.

The frequency variable section Tfc must be maintained until the end of the voltage drop phenomenon Vdrop. The voltage drop phenomenon Vdrop occurs at the start time of the image display period Tdp and is maintained for a predetermined time. That is, the frequency variable section Tfc is maintained until the second predetermined time? 2 after the vertical blank period Tb ends. Therefore, the second predetermined time? 2 is set to a range including a period during which the voltage drop phenomenon can occur.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (5)

A display panel on which data lines are arranged;
A data driver for providing a data voltage to the data line;
A boost converter including a switch element and outputting a reference voltage for setting the data voltage according to a turn-on and turn-off ratio of the switch element to an output voltage;
A PWM controller for varying the frequency of the switching element; And
And a timing controller for setting the period from the vertical blank period to the video display period to a frequency variable section and controlling the PWM control section to increase the switching frequency of the switching element during the frequency variable section.
The method according to claim 1,
The timing controller outputs a signal for setting the period from the time when the vertical synchronization signal Vsync is input and the first predetermined time elapses to the time when the vertical synchronization signal Vsync is terminated and the second predetermined time has elapsed, Device.
3. The method of claim 2,
Wherein the timing controller sets the first predetermined time shorter than a period corresponding to a pulse width of the vertical synchronization signal.
3. The method of claim 2,
Wherein the timing controller provides a control signal to the PWM control unit during the frequency variable period,
And the PWM control unit sets the frequency of the switching frequency higher in response to the control signal.
The method according to claim 1,
The boost converter
An inductor disposed between an input terminal and a node to which the switch element is connected;
A rectifier diode connected in series with the inductor; And
And a capacitor for smoothing the output voltage between the diode and the output terminal.

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