KR20160023542A - Method of designing layout of integrated circuit and method of manufacturing the integrated circuit - Google Patents

Abstract

The present disclosure relates to a method of designing an integrated circuit, the method comprising: designing a first layout by arranging and wiring a plurality of standard cells defining an integrated circuit; in a process of preparing mask data for the first layout, 2 layout by connecting the first and second patterns of the first layer patterns to each other so that the number of masks necessary for forming the first layer patterns corresponding to the first layer of the first layout is reduced, Create a layout.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of designing an integrated circuit and a method of manufacturing the integrated circuit,

Technical aspects of the present invention relate to an integrated circuit, and more particularly, to a method of designing an integrated circuit including at least one standard cell and a method of manufacturing the integrated circuit.

The design of a semiconductor integrated circuit is the task of transforming a behavioral model for a chip that describes an operation to be obtained from a semiconductor system into a concrete structural model that describes the connections between the required components. In the process of designing such a semiconductor integrated circuit, when a library of cells included in the semiconductor integrated circuit is generated and a semiconductor integrated circuit is implemented using the generated library, the time required for designing and implementing the semiconductor integrated circuit There is an advantage that the cost can be reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a layout design method of an integrated circuit capable of reducing the number of masks required to form an integrated circuit and a method of manufacturing the integrated circuit.

A method of designing an integrated circuit layout according to the technical idea of the present invention includes the steps of: designing a first layout by arranging and wiring a plurality of standard cells defining an integrated circuit; and preparing mask data for the first layout And generating a second layout by changing the first layout, wherein the second layout is formed by changing the first layout so that the number of masks necessary for forming the first layer patterns corresponding to the first layer of the first layout is reduced, 1 and the second patterns to each other to generate the second layout.

In some embodiments, the first and second patterns may be disposed parallel to one another along a first direction and extend in a second direction substantially perpendicular to the first direction.

In some embodiments, the step of creating the second layout further comprises: merging the first and second patterns to form a first layout having a first width greater than a width along a first direction of each of the first and second patterns, The second layout having a width and a new pattern that can be formed with one mask can be generated.

In some embodiments, the step of generating the second layout may have an H shape including a bridge pattern connecting the first and second patterns and the first and second patterns, The second layout including the new pattern that can be formed can be generated.

In some embodiments, the step of creating the second layout may include: reducing the height of the first and second patterns, respectively, in the second direction; 2 patterns, and a second layer commonly connected to the new first and second patterns.

In some embodiments, the first layout further comprises a plurality of conductive lines disposed in parallel with the first and second patterns, and the second layer includes at least one of the plurality of conductive lines, And may be a contact to be formed on the new first and second patterns.

In some embodiments, the step of generating the second layout may include the step of: comparing the first pattern with the third pattern so that the distance between the first pattern and the third pattern is equal to or greater than a critical distance, Wherein the height of the first pattern is smaller than the height of the first pattern and the height of the second pattern is smaller than the height of the second pattern. Can be generated.

In some embodiments, the first layout further comprises a plurality of conductive lines disposed in parallel with the first and second patterns, and the second layer includes at least one of the plurality of conductive lines, And may be a contact to be formed on the new first pattern and the second pattern.

In some embodiments, the first layer may be a contact that is electrically connected to and formed on the active region of the integrated circuit.

In some embodiments, the first and second patterns may correspond to the first and second power contact patterns, respectively.

In some embodiments, the first and second power contact patterns are included in a first standard cell, and patterns of the first layer patterns other than the first and second power contact patterns are included in the first standard And may be included in a second standard cell disposed adjacent to the cell in the second direction.

In some embodiments, the first power contact pattern is included in a first standard cell and the second power contact pattern is included in a second standard cell disposed adjacent to the first standard cell in the first direction Patterns of the first layer patterns other than the first and second power contact patterns may be included in a third standard cell disposed adjacent to the first and second standard cells in the second direction have.

Further, a method of manufacturing an integrated circuit according to the technical idea of the present invention includes: providing a standard cell library including information on a plurality of standard cells defining an integrated circuit; Designing a first layout by arranging and wiring the plurality of standard cells; Determining whether the number of masks necessary for forming the first layer patterns corresponding to the first layer of the first layout is equal to or greater than a threshold value in the step of preparing mask data for the first layout; Generating a second layout by changing the first layout when the number of masks necessary for forming the first layer patterns is equal to or larger than the threshold value; And forming the integrated circuit based on the second layout.

In some embodiments, the step of forming the integrated circuit includes the steps of: modifying the second layout by performing an OPC based on the second layout; modifying the plurality of masks based on the modified second layout And forming the integrated circuit using the plurality of masks.

In some embodiments, the method may further comprise forming the integrated circuit based on the first layout if the number of masks needed to form the first layer patterns is less than the threshold have.

According to the technical idea of the present invention, by designing the first layout using the layout and wiring tool and changing the first layout in the mask data preparation step to generate the second layout, the number of masks required to form the first layer Can be reduced. Thus, by manufacturing the integrated circuit on the basis of the second layout, the manufacturing cost of the integrated circuit can be reduced.

1 is a flowchart illustrating a method of manufacturing an integrated circuit according to an embodiment of the present invention.
2 is a layout showing an example of a standard cell.
3 is a perspective view showing an example of a semiconductor element having the layout of FIG.
4 is a cross-sectional view taken along line III-III 'of FIG.
5 is a perspective view showing another example of a semiconductor element having the layout of FIG.
6 is a sectional view taken along the line VV 'in Fig.
Figures 7A-7D are exemplary layouts for a portion of an integrated circuit including two adjacent standard cells.
8 is an example of a second layout changed from the first layout by data polishing according to an embodiment of the present invention.
Figs. 9A and 9B are examples of cross-sectional views taken along line IX-IX 'of the second layout of Fig.
10 is another example of a second layout modified from the first layout by data polishing according to an embodiment of the present invention.
11 is another example of a second layout changed from the first layout by data polishing in accordance with an embodiment of the present invention.
12 is an example of a cross-sectional view taken along the line XII-XII 'of the second layout in Fig.
13 is another example of a second layout changed from the first layout by data polishing according to an embodiment of the present invention.
14 is a flowchart showing a layout design method of an integrated circuit according to an embodiment of the present invention.
15 is a block diagram illustrating a storage medium according to one embodiment of the present disclosure;
16 is a block diagram illustrating a memory card including an integrated circuit according to one embodiment of the present disclosure;
17 is a block diagram illustrating a computing system including an integrated circuit in accordance with one embodiment of the present disclosure;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises" or "having", etc. are intended to specify the presence of stated features, integers, steps, operations, elements, parts, or combinations thereof, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Also, the terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

The integrated circuit can be defined as a plurality of cells, and specifically, can be designed using a cell library including characteristic information of a plurality of cells. Here, the cell library may be defined with a cell name, a dimension, a gate width, a pin, a delay characteristic, a leakage current, a threshold voltage, and a function. A typical cell library set includes basic cells such as AND, OR, NOR, and inverters, complex cells such as OAI (OR / AND / INVERTER) and AOI (AND / OR / INVERTER) And may include a storage element such as a simple master-slave flip-flop and a latch.

In the embodiments of the present invention described below, the cell library may be a standard cell library. In the standard cell method, a logic circuit block (or cell) having various functions is prepared in advance, and these cells are arbitrarily combined to design a dedicated large-scale integrated circuit (LSI) adapted to the specification of a customer or user. Cells are pre-designed and verified and registered on a computer. Logic design, layout, and wiring are done using a combination of cells using Computer Aided Design (CAD).

Specifically, when a large-scale integrated circuit is designed / manufactured, if standardized logic circuit blocks (or cells) of a certain size are already stored in the library, a logic circuit block suited to the current design purpose is taken out of the library, And the entire circuit can be made by performing the optimum wiring in which the wiring length is the shortest in the wiring space between the cell and the cell. The more kinds of cells stored in the library, the more flexible the design and the more likely the optimum design of the chip.

As such, an integrated circuit using a standard cell is implemented by arranging cells so as to use standard cells stored in a standard cell library and to minimize wiring between them. Therefore, the development cost can be reduced and the development period can be shortened as compared with the fully custom integrated circuit.

1 is a flowchart illustrating a method of manufacturing an integrated circuit according to an embodiment of the present invention.

Referring to FIG. 1, a manufacturing method of an integrated circuit according to the present embodiment can be divided into a design S100 of an integrated circuit and a manufacturing process S200 of an integrated circuit. The design of the integrated circuit (S100) includes steps S110 and S130, and may be performed in a tool for designing the integrated circuit as a step of designing the layout for the integrated circuit. At this time, the tool for designing the integrated circuit may be a program including a plurality of instructions executed in the processor. On the other hand, the manufacturing process (S200) of the integrated circuit includes steps S210 to S270, and can be performed in the semiconductor process module as a step of manufacturing an integrated circuit based on the designed layout. Hereinafter, each step included in the designing step (S100) of the integrated circuit and the step (S200) of manufacturing the integrated circuit will be described in detail.

In step S110, a standard cell library is provided. Here, the standard cell library may include information on a plurality of standard cells, and may be stored in a computer-readable storage medium. The standard cell library may include layout information and timing information of a standard cell. The details of the standard cell will be described in more detail with reference to FIG. 2 below.

In step S130, a first layout is designed by placing and routing (P & R) standard cells using a standard cell library. Specific embodiments for designing the first layout by arranging and wiring the standard cells will be described in more detail below with reference to FIGS. 7A to 7D.

Specifically, first, input data defining an integrated circuit is received. Here, the input data may be an abstract form of behavior of the integrated circuit, for example, data generated by synthesis using standard cell library from data defined in RTL (Register Transfer Level). For example, the input data may be a bitstream or a netlist generated by synthesizing integrated circuits defined as HDL (Hardware Description Language) such as VHDL (VHSIC Hardware Description Language) and Verilog.

Then, a storage medium storing a standard cell library is accessed, and standard cells selected and arranged according to input data among a plurality of standard cells stored in the standard cell library are arranged. Here, the placement and wiring refers to the operation of placing the selected standard cells and connecting the arranged standard cells. By completing layout and wiring, an initial layout or an original layout for an integrated circuit can be generated. Hereinafter, this will be referred to as a first layout.

The design of the integrated circuit (S100) may include the above-described steps S110 and S130. However, the present invention is not limited to this, and may further include various steps according to a general integrated circuit design method such as generation of a standard cell library, modification of a standard cell library, layout verification, post simulation, and the like.

In step S210, it is determined whether the number of masks necessary for forming the patterns corresponding to the first layer of the first layout is equal to or greater than a threshold value. Specifically, step S210 may be performed during a mask data preparation process for the first layout. Here, the mask data preparation process is a process of preparing overall performance data of the first layout designed in the designing process S100 of the integrated circuit, and preparing OPC (Optical Proximity Correction) performance. If it is determined that the number of masks required to form the patterns corresponding to the first layer is greater than or equal to the threshold value, step S230 is performed. Otherwise, step S270 is performed.

In step S230, a second layout is created by changing the first layout. Specifically, step S230 may be performed during the mask data preparation for the first layout together with step S210. As such, the operation of creating the second layout by changing the first layout in the mask data preparation can be referred to as data polishing. The details of the data polishing will be described in more detail with reference to FIGS. 8 to 13 below.

In step S250, an integrated circuit is formed based on the second layout. Specifically, first, OPC is performed based on the second layout to change the second layout. Here, the OPC refers to a step of changing the second layout in accordance with the error due to the optical proximity effect. If a photolithography process is carried out using the mask prepared by using the second layout as it is, another pattern can be formed by the optical proximity effect. Therefore, the second layout is changed in accordance with the error due to the optical proximity effect, the mask is formed based on the changed second layout, and the photolithography process is performed, so that the same pattern as the second layout can be formed.

Subsequently, a mask is fabricated in accordance with the changed second layout in accordance with the result of the OPC, and an integrated circuit is formed using the fabricated mask. At this time, it is possible to manufacture a mask using a graphic design system (GDS) in which a layout reflecting OPC, for example, OPC is reflected, and an integrated circuit can be formed on the wafer using a photolithography process using the manufactured mask have.

In step S270, an integrated circuit is formed based on the first layout. Step S270 may be performed substantially similar to step S250. That is, the OPC is performed on the basis of the first layout to change the first layout, the mask is fabricated in accordance with the first layout changed according to the OPC execution result, and the integrated circuit is formed using the fabricated mask.

Fig. 2 is a layout showing an example (SC) of a standard cell.

2, the standard cell SC is defined by a cell boundary (C_BD) and includes a plurality of fins FIN, first and second active areas AR1 and AR2, a plurality And may include conductive lines CL and a plurality of first contacts CA. The cell boundary C_BD can be an outline defining the standard cell SC and the placement and wiring tool can recognize the standard cell SC using the cell boundary C_BD. The cell boundary (C_BD) consists of four cell boundary lines.

The plurality of pins FIN extend in a first direction (e.g., the X direction) and may be disposed parallel to each other along a second direction (e.g., Y direction) perpendicular to the first direction. The first active area AR1 and the second active area AR2 may be arranged in parallel with each other and may have different conductivity types. In this embodiment, three fins FIN may be disposed in each of the first and second active areas AR1 and AR2. However, the present invention is not limited to this, and the number of fins FIN disposed in each of the first and second active areas AR1 and AR2 may be variously changed.

At this time, the plurality of pins FIN disposed in the first and second active areas AR1 and AR2 may be referred to as active pins. 2, the present invention is not limited to this. The standard cell SC includes a cell boundary C_BD, a first active region AR1, first and second active regions AR1 and AR2 , Or dummy pins disposed in a region between the second active region AR2 and the cell boundary C_BD.

The plurality of conductive lines CL may extend in a second direction (e.g., Y direction) and may be disposed parallel to each other along a first direction (e.g., X direction). At this time, the conductive lines CL may be made of any material having electrical conductivity, and may include, for example, polysilicon, metal, metal fitting, and the like.

In one embodiment, the conductive lines CL may correspond to the gate electrodes. However, the present invention is not limited thereto, and the conductive lines CL may be a trace having any conductivity or the like. Although the standard cell SC is shown as including three conductive lines CL in FIG. 2, this is only an example, and the standard cell SC extends in the second direction, And may include four or more conductive lines arranged parallel to each other.

A plurality of first contacts CA may be disposed on the first and second active regions AR1 and AR2 and may be electrically connected to the first and second active regions AR1 and AR2. In one embodiment, a plurality of first contacts CA may be source / drain contacts, and in other embodiments, a plurality of first contacts CA may be power contacts have. Although not shown, the standard cell SC may further include a second contact disposed on the plurality of conductive lines CL and electrically connected to the plurality of conductive lines CL.

3 is a perspective view showing an example of a semiconductor element having the layout of FIG. 4 is a cross-sectional view taken along line III-III 'of FIG.

Referring to FIGS. 3 and 4, the semiconductor device 100a may be a bulk type pin transistor. The semiconductor device 100a includes a substrate SUB, a first insulating layer IL1, a second insulating layer IL2, first to third pins FIN, and a conductive line CL ).

The substrate SUB may be a semiconductor substrate, for example, the semiconductor substrate may comprise any one of silicon, silicon-on-insulator, silicon-on-sapphire, germanium, silicon-germanium and gallium arsenide. Here, the substrate SUB may be a P-type substrate and may be used as the first active region AR1.

The first to third pins FIN may be arranged to be connected to the substrate SUB. In one embodiment, the first to third fins FIN may be active regions doped with n + or p + portions protruding from the substrate SUB to the vertical portion.

The first and second insulating layers IL1 and IL2 may include an insulating material, for example, the insulating material may include any one of an oxide layer, a nitride layer, and an oxynitride layer. The first insulating layer IL1 may be disposed on the first to third pins FIN. The first insulating layer IL1 is disposed between the first to third pins FIN and the gate electrode CL, so that it can be used as a gate insulating film. The second insulating layer IL2 may be arranged to have a predetermined height in the space between the first to third pins FIN. The second insulating layer IL2 is disposed between the first to third fins FIN so that it can be used as an element isolation film.

The gate electrode CL may be disposed on top of the first and second insulating layers IL1 and IL2. Thus, the gate electrode CL may have a structure surrounding the first to third pins FIN, the first insulating layer IL1, and the second insulating layer IL2. In other words, the first to third pins FIN may have a structure disposed inside the gate electrode CL. The gate electrode CL may include a metal material such as W, Ta, etc., a nitride thereof, a silicide thereof, a doped polysilicon, or the like, and may be formed using a deposition process.

5 is a perspective view showing another example of a semiconductor element having the layout of FIG. 6 is a cross-sectional view taken along the line V-V 'in Fig.

5 and 6, the semiconductor device 100b may be an SOI type pin transistor. The semiconductor device 100b includes a substrate SUB ', a first insulating layer IL1', a second insulating layer IL2 ', first to third pins FIN' Quot; CL "). Since the semiconductor device 100b according to the present embodiment is a modified embodiment of the semiconductor device 100a shown in Figs. 3 and 4, the following description will focus on the difference from the semiconductor device 100a, The description of which will be omitted.

The first insulating layer IL1 'may be disposed on the substrate SUB'. The second insulating layer IL2 'is disposed between the first to third pins FIN' and the gate electrode CL ', so that it can be used as a gate insulating film. The first to third fins FIN 'may be a semiconductor material, for example, silicon or doped silicon.

The gate electrode CL 'may be disposed on the upper portion of the second insulating layer IL2'. Thus, the gate electrode CL 'may have a structure surrounding the first to third pins FIN' and the second insulating layer IL2 '. In other words, the first and second fins FIN 'may have a structure disposed inside the gate electrode CL'.

7A-7D are exemplary first layouts 10a-10d for a portion of an integrated circuit comprising two adjacent standard cells.

7A-7D illustrate exemplary embodiments of step S130 of FIG. 1 in which first and second standard cells SC1, SC2 are moved by a placement and routing tool along a second direction (e.g., the Y direction) Can be disposed adjacent to each other. Concretely, by arranging the selected first and second standard cells SC1 and SC2 using arrangement and wiring tools, and then connecting the disposed first and second standard cells SC1 and SC2 to each other, The first layouts 10a to 10d shown in Figs. 7A to 7D can be designed. For the sake of convenience, the first layouts 10a to 10d of Figs. 7A to 7D do not show the pins FIN of Fig.

Referring to FIG. 7A, the first layout 10a may include a first standard cell SC1 and a second standard cell SC2 disposed adjacent to each other along the second direction. In this embodiment, the first contact CA of the first standard cell SC1 may include first and second power contact patterns CA_P1 and CA_P2, and the first contact CA of the first standard cell SC1 may include the first and second power contact patterns CA_P1 and CA_P2. The contact CA may also include first and second power contact patterns CA_P1 and CA_P2.

The first power contact patterns CA_P1 included in the first and second standard cells SC1 and SC2 can be connected to each other by the placement and wiring tool and similarly the first and second standard cells SC1 and SC2 The second power contact patterns CA_P2 may be connected to each other. Accordingly, the first layout 10a may include one first power contact pattern CA_P1 and one second power contact pattern CA_P2.

One first power contact pattern CA_P1 and one second power contact pattern CA_P2 in the first layout 10a can constitute the first contact CA. The distance D0 between the first and second power contact patterns CA_P1 and CA_P2 may be less than or equal to the patterning resolution limit as the semiconductor process is miniaturized, (CA_P1, CA_P2) can not be formed by one mask. Therefore, two masks are required to form the first contact CA including the first and second power contact patterns CA_P1 and CA_P2.

Referring to FIG. 7B, the first layout 10b may include a first standard cell SC1 and a second standard cell SC2 disposed adjacent to each other along the second direction. In this embodiment, the first contact CA of the first standard cell SC1 may include a first power contact pattern CA_P1 and a first source / drain contact pattern CA_SD1, SC2 may include first and second power contact patterns CA_P1, CA_P2.

The first power contact patterns CA_P1 included in the first and second standard cells SC1 and SC2 may be connected to each other by the placement and wiring tool. However, the first source / drain contact pattern CA_SD1 included in the first standard cell SC1 and the second power contact pattern CA_P2 included in the second standard cell SC2 are connected to each other because different voltages are applied thereto I can not. Thus, the first layout 10b may include a first power contact pattern CA_P1, a first source / drain contact pattern CA_SD1, and a second power contact pattern CA_P2.

In the first layout 10b, one first power contact pattern CA_P1, a first source / drain contact pattern CA_SD1, and a second power contact pattern CA_P2 may constitute a first contact CA. The distance D0 between the first and second power contact patterns CA_P1 and CA_P2 may be less than the patterning resolution limit due to the miniaturization of the semiconductor process and accordingly the first and second power contact patterns CA_P1 and CA_P2 Can not be formed by a single mask.

The distance D1 between the first source / drain contact pattern CA_SD1 and the second power contact pattern CA_P2 may be less than the patterning resolution limit and thus the first source / drain contact pattern CA_SD1, 2 power contact pattern CA_P2 can not be formed by one mask. Therefore, three masks are required to form the first contact CA comprising the first power contact pattern CA_P1, the first source / drain contact pattern CA_SD1, and the second power contact pattern CA_P2.

Referring to FIG. 7C, the first layout 10c may include a first standard cell SC1 and a second standard cell SC2 disposed adjacent to each other along the second direction. In this embodiment, the first contact CA of the first standard cell SC1 may include first and second source / drain contact patterns CA_SD1 and CA_SD2, The first contact CA may include third and fourth source / drain contact patterns CA_SD3 and CA_SD4.

The first and second source / drain contact patterns CA_SD1 and CA_SD2 included in the first standard cell SC1 and the third and fourth source / drain contact patterns CA_SD3 and CA_SD3 included in the second standard cell SC2, , CA_SD4 can not be connected to each other since different voltages may be applied. Thus, the first layout 10c may include first through fourth source / drain contact patterns CA_SD1 through CA_SD4.

In the first layout 10c, the first to fourth source / drain contact patterns CA_SD1 to CA_SD4 may constitute a first contact CA. The distance D0 between the first and second source / drain contact patterns CA_SD1 and CA_SD2 may be less than the patterning resolution limit due to the miniaturization of the semiconductor process, so that the first and second source / (CA_SD1, CA_SD2) can not be formed by one mask. Likewise, the distance D0 between the third and fourth source / drain contact patterns CA_SD3 and CA_SD4 may be less than the patterning resolution limit and thus the third and fourth source / drain contact patterns CA_SD3 and CA_SD4 Can not be formed by a single mask.

In addition, the distance D2 between the first source / drain contact pattern CA_SD1 and the fourth source / drain contact pattern CA_SD4 may be less than the patterning resolution limit, and thus the first source / drain contact pattern CA_SD1, And the fourth source / drain contact pattern CA_SD4 can not be formed by one mask. On the other hand, the distance D3 between the first source / drain contact pattern CA_SD1 and the third source / drain contact pattern CA_SD3 may be greater than the patterning resolution limit and thus the first source / drain contact pattern CA_SD1, And the third source / drain contact pattern CA_SD3 may be formed using one mask. Therefore, three masks are required to form the first contact including the first to fourth source / drain contact patterns CA_SD1 to CA_SD4.

Referring to FIG. 7D, the first layout 10d may include a first standard cell SC1 and a second standard cell SC2 disposed adjacent to each other along the second direction. In this embodiment, the first contact CA of the first standard cell SC1 may include first and second source / drain contact patterns CA_SD1 and CA_SD2, The first contact CA may include first and second power contact patterns CA_P1 and CA_P2.

The first and second source / drain contact patterns CA_SD1 and CA_SD2 included in the first standard cell SC1 and the third and fourth source / drain contact patterns CA_SD3 and CA_SD3 included in the second standard cell SC2, , CA_SD4 can not be connected to each other since different voltages may be applied. Thus, the first layout 10d may include first and second source / drain contact patterns CA_SD1 and CA_SD2 and first and second power contact patterns CA_P1 and CA_P2.

In the first layout 10d, the first and second source / drain contact patterns CA_SD1 and CA_SD2 and the first and second power contact patterns CA_P1 and CA_P2 may constitute a first contact CA . The distance D0 between the first and second source / drain contact patterns CA_SD1 and CA_SD2 may be less than the patterning resolution limit due to the miniaturization of the semiconductor process, so that the first and second source / (CA_SD1, CA_SD2) can not be formed by one mask. Likewise, the distance D0 between the first and first power contact patterns CA_P1 and CA_P2 may be less than the patterning resolution limit, so that the first and second power contact patterns CA_P1 and CA_P2 may be one It can not be formed by a mask.

The distance D1 between the first source / drain contact pattern CA_SD1 and the second power contact pattern CA_P2 may be less than the patterning resolution limit and thus the first source / drain contact pattern CA_SD1, 2 power contact pattern CA_P2 can not be formed by one mask. Further, the distance D4 between the first source / drain contact pattern CA_SD1 and the first power contact pattern CA_P1 may be less than the patterning resolution limit, and thus the first source / drain contact pattern CA_SD1 and the first power contact pattern CA_P1 may be less than the patterning resolution limit. 1 power contact pattern CA_P1 can not be formed by one mask. Therefore, in order to form the first contact CA including the first and second source / drain contact patterns CA_SD1 and CA_SD2 and the first and second power contact patterns CA_P1 and CA_P2, need.

As described above, the first layout 10a of Fig. 7A includes two first contact patterns CA_P1 and CA_P2, so that two masks are required. Since the first layout 10b of Fig. 7B includes three first contact patterns CA_P1, CA_P2, and CA_SD1, three masks are required. The first layout 10c of FIG. 7C includes four first contact patterns CA_SD1 through CA_SD2, but the distance between the first source / drain contact pattern CA_SD1 and the third source / drain contact pattern CA_SD3 (D3) is above the patterning resolution limit, three masks are required. However, since the first layout 10d of Fig. 7D includes four first contact patterns CA_P1, CA_P2, CA_SD1, CA_SD2, and the distance between each contact pattern is below the patterning resolution limit, need.

The manufacturing cost of the integrated circuit increases as the number of masks for forming the first contact CA increases. However, in the designing stage of the integrated circuit, specifically, in the preparation stage of the standard cell library (S110 in FIG. 1), the standard cell to be placed adjacent can not be predicted. Therefore, it is impossible to design the layout of each standard cell by reflecting the number of masks.

As described above with reference to Figs. 7A-7D, one layer, e.g., a first contact CA, included in the designed integrated circuit may include a plurality of patterns, for example, first and second power contacts Patterns CA_P1 and CA_P2 or first and second source / drain contact patterns CA_SD1 and CA_SD2. Accordingly, one layer included in the designed integrated circuit may be formed by patterning using a plurality of masks corresponding to the plurality of patterns. In the case of a layer patterned using a plurality of masks as described above, in the designing stage of the integrated circuit, specifically, in the layout design stage of the standard cell, a plurality of colors each corresponding to a plurality of masks through color decomposition, A plurality of patterns can be designed.

Since the first contact CA included in the first layout 10d of FIG. 7D includes four patterns CA_SD1, CA_SD2, CA_P1, and CA_P2, four masks are required. In this case, A color violation occurs between the four patterns CA_SD1, CA_SD2, CA_P1, and CA_P2, which are designed in four different colors. Color conflict problems can arise from the same color violation in the placement and wiring of standard cells that define such integrated circuits.

According to this embodiment, the number of masks for forming the first layer, for example, the first contact CA, which is one of the plurality of layers constituting the integrated circuit, is a threshold value (for example, four) , It is possible to perform design polishing to change the first layout to the second layout in order to reduce the number of masks in the mask data preparing step. Therefore, design polishing can be performed in the mask data preparation step for the first layout 10d in Fig. 7D. Hereinafter, specific embodiments of data polishing will be described in more detail with reference to FIGS. 8 to 13. FIG.

Figure 8 is an example (20a) of a second layout modified from the first layout by data polishing in accordance with an embodiment of the present invention.

8, a second layout 20a can be generated by merge the first and second power contact patterns CA_P1, CA_P2 of the first layout 10d with each other in the mask data preparation step . At this time, since the first and second power contact patterns CA_P1 and CA_2 can be applied with the same voltage, the first and second power contact patterns CA_P1 and CA_2 can be connected.

Specifically, the first and second power contact patterns CA_P1 and CA_P2 designed in different colors in the first layout 10d are formed in one power contact pattern CA_P). Accordingly, when an integrated circuit is fabricated on the basis of the second layout 20a, it corresponds to three patterns of the first and second source / drain contact patterns CA_SD1 and CA_SD2 and the power contact pattern CA_P, respectively The first contact CA may be patterned using the three masks.

The power contact pattern CA_P included in the second layout 20a has a first width W in a first direction (for example, X direction) and a second width (for example, 1 < / RTI > height (H). In the second layout 20a, as in the first layout 10d, two vias V may be disposed on the power contact patterns CA_P.

At this time, the first width W is a width of each of the first and second power contact patterns CA_P1 and CA_P2 in the first layout 10d and a width of each of the first and second power contact patterns CA_P1 and CA_P2 May be substantially the same as the sum of the distances. However, the present invention is not limited to this, and the first width W may be a width of each of the first and second power contact patterns CA_P1 and CA_P2 in the first layout 10d and a width of each of the first and second power contact patterns CA_P1 and CA_P2, May be less than or greater than the sum of the distances between CA_P1 and CA_P2.

On the other hand, the first height H may be substantially equal to the height of each of the first and second power contact patterns CA_P1 and CA_P2 in one layout 10d. However, the present invention is not limited to this, and the first height H may be smaller or larger than the height of each of the first and second power contact patterns CA_P1 and CA_P2 in the first layout 10d.

Therefore, according to the present embodiment, the second layout 20a can reduce the number of masks required to form the first contact CA compared to the first layout 10d by one. In other words, when the integrated circuit is formed using the second layout 20a, the first contacts CA can be formed using three masks.

Figs. 9A and 9B are examples of cross-sectional views taken along line IX-IX 'of the second layout of Fig.

9A, the semiconductor device 200a may include a substrate SUB, a conductive line CL, a contact plug CP, and a power contact CA_Pa. Although not shown, a metal line for providing a power supply voltage or a ground voltage, for example, and a via for connecting the metal line and the power contact CA_Pa may be formed on the power contact CA_Pa, .

The substrate SUB may be a semiconductor substrate, for example the semiconductor substrate may comprise any one of silicon, silicon-on-insulator (SOI), silicon-on-sapphire, germanium, silicon-germanium and gallium arsenide. have. For example, the substrate SUB may be a P-type substrate. Further, although not shown, the substrate SUB may include an active region doped with an impurity.

The conductive line CL may be disposed on the substrate SUB. In one embodiment, the conductive line CL may be used as a gate electrode, in which case a gate insulating layer may be further disposed between the conductive line CL and the active region in the substrate SUB.

In one embodiment, the conductive line CL may be a dummy conductive line. As described above, when the conductive line CL is a dummy conductive line, there is a cell boundary between the first power contact pattern CA_P1 and the second power contact pattern CA_P2 in the first layout 10d of Fig. 8 . Here, the first power contact pattern CA_P1 and the second power contact pattern CA_P2 may be included in different standard cells.

The contact plug CP may be disposed on the substrate SUB and may be formed to have substantially the same height as the conductive line CL. Thereby, the power contact CA_Pa can be connected to the conductive line CL. The contact plug CP may be disposed in a part of the substrate SUB to electrically connect the power contact CA_Pa and the substrate SUB.

The power contact CA_Pa may be disposed on the contact plug CP and may be electrically connected to the contact plug CP. As a result, the power contact CA_Pa can provide, for example, a power supply voltage or a ground voltage to the active region in the substrate SUB.

9B, the semiconductor device 200b may include a substrate SUB, a conductive line CL, a contact plug CP ', and a power contact CA_Pb. Although not shown, a metal line for providing a power supply voltage or a ground voltage, for example, and a via connecting a metal line and a power contact CA_Pb may be further disposed on the power contact CA_Pb.

The substrate SUB may be a semiconductor substrate, for example the semiconductor substrate may comprise any one of silicon, silicon-on-insulator (SOI), silicon-on-sapphire, germanium, silicon-germanium and gallium arsenide. have. For example, the substrate SUB may be a P-type substrate. Further, although not shown, the substrate SUB may include an active region doped with an impurity.

The conductive line CL may be disposed on the substrate SUB. In one embodiment, the conductive line CL may be used as a gate electrode, in which case a gate insulating layer may be further disposed between the conductive line CL and the active region in the substrate SUB. In one embodiment, the conductive line CL may be an active conductive line.

The contact plug CP 'may be disposed on the substrate SUB and may be formed higher than the conductive line CL. As a result, the power contact CA_Pb may not be connected to the conductive line CL. The contact plug CP 'is disposed in a partial region of the substrate SUB to electrically connect the power contact CA_Pb and the substrate SUB.

The power contact CA_Pb may be disposed on the contact plug CP 'and may be electrically connected to the contact plug CP. As a result, the power contact CA_Pb can provide, for example, a power supply voltage or a ground voltage to the active region in the substrate SUB.

10 is another example 20b of the second layout modified from the first layout by data polishing according to an embodiment of the present invention.

10, by adding a bridge pattern BR between the first and second power contact patterns CA_P1 and CA_P2 of the first layout 10d in the mask data preparing step, the second layout 20b Can be generated. At this time, since the first and second power contact patterns CA_P1 and CA_P2 can be applied with the same voltage, the first and second power contact patterns CA_P1 and CA_P2 can be connected.

Specifically, the first and second power contact patterns CA_P1 and CA_P2 designed in different colors in the first layout 10d are formed in one power contact pattern CA_P '). Accordingly, when the integrated circuit is fabricated on the basis of the second layout 20b, the three patterns of the first and second source / drain contact patterns CA_SD1 and CA_SD2 and the power contact pattern CA_P ' The first contact CA may be patterned using the corresponding three masks.

The power contact pattern CA_P'included in the second layout 20b may include first and second power contact patterns CA_P1 and CA_P2 and a bridge pattern BR and may be formed as a single mask have. Thus, the second layout 20b may include an H-shaped power contact CA_P '. The vias V may be disposed on the first and second power contact patterns CA_P1 and CA_P2, respectively, as in the first layout 10d, in the second layout 20b. As described above, the power contact CA_P 'including the first and second power contact patterns CA_P1 and CA_P2 and the bridge pattern BR can be formed using a single mask.

Therefore, according to the present embodiment, the second layout 20b can reduce the number of masks required to form the first contact by one compared to the first layout 10d. In other words, when the integrated circuit is formed using the second layout 20b, the first contact can be formed using three masks.

11 is another example 20c of the second layout modified from the first layout by data polishing according to an embodiment of the present invention.

11, in the mask data preparing step, the height of the first and second power contact patterns CA_P1 and CA_P2 of the first layout 10d is decreased in the second direction, and the height of the first and second power contact patterns CA_P1 and CA_P2, It is possible to generate the second layout 20c by arranging the second contact CB1 connected to the patterns CA_P1 and CAP_2. At this time, since the first and second power contact patterns CA_P1 and CA_P2 can be applied with the same voltage, the first and second power contact patterns CA_P1 and CA_P2 can be connected.

Specifically, the first and second power contact patterns CA_P1 and CA_P2 designed in different colors in the first layout 10d are connected to the first and second power contact patterns CA_P1 and CA_P2 designed in the same color in the second layout 20c, Can be changed to the contact patterns CA_P1 ', CA_P2'. Thus, when an integrated circuit is fabricated based on the second layout 20c, two masks corresponding to the first and second source / drain contact patterns CA_SD1 and CA_SD2, respectively, and first and second power It is possible to pattern the first contact CA using one mask corresponding to the contact patterns CA_P1 'and CA_P2'.

The second layout 20c may include first and second power contact patterns CA_P1 ', CA_P2' and a second contact CB1 having a second height H2 along a second direction. At this time, the first and second power contact patterns CA_P1 'and CA_P2' included in the second layout 20c may be formed using a single mask. A second contact CB1 connected in common to the first and second power contact patterns CA_P1 'and CA_P2' is formed on the first and second power contact patterns CA_P1 'and CA_P2' in the second layout 20c. May be disposed, and two vias V may be disposed on the second contact CB1.

Therefore, according to the present embodiment, the second layout 20c can reduce the number of masks required to form the first contact by one compared to the first layout 10d. In other words, when the integrated circuit is formed using the second layout 20c, the first contacts can be formed using three masks.

12 is an example of a cross-sectional view taken along the line XII-XII 'of the second layout in Fig.

12, the semiconductor device 200c may include a substrate SUB, a conductive line CL, first and second power contact patterns CA_P1 ', CA_P2' and a second contact CB have. Although not shown, a metal line for providing a power supply voltage or a ground voltage, for example, and a via connecting the metal line and the second contact CB1 may be further disposed on the second contact CB1 .

The substrate SUB may be a semiconductor substrate, for example the semiconductor substrate may comprise any one of silicon, silicon-on-insulator (SOI), silicon-on-sapphire, germanium, silicon-germanium and gallium arsenide. have. For example, the substrate SUB may be a P-type substrate. Further, although not shown, the substrate SUB may include an active region doped with an impurity.

The conductive line CL may be disposed on the substrate SUB. In one embodiment, the conductive line CL may be used as a gate electrode, in which case a gate insulating layer may be further disposed between the conductive line CL and the active region in the substrate SUB.

In one embodiment, the conductive line CL may be a dummy conductive line. Thus, when the conductive line CL is a dummy conductive line, a cell boundary is present between the first power contact pattern CA_P1 and the second power contact pattern CA_P2 in the first layout 10d of FIG. 11, . Here, the first power contact pattern CA_P1 and the second power contact pattern CA_P2 may be included in different standard cells.

The first and second power contacts CA_P1 ', CA_P2' may be disposed on the substrate SUB and may be formed at substantially the same height as the conductive line CL. Thus, the second contact CB1 can be connected to the conductive line CL. The first and second power contacts CA_P1 ', CA_P2' may be disposed in a portion of the substrate SUB, specifically, in the second active region AR2.

The second contact CB1 may be disposed on the first and second power contacts CA_P1 ', CA_P2' and may be connected in common to the first and second power contacts CA_P1 ', CA_P2'. Thereby, the second contact CB1 can provide, for example, a power supply voltage or a ground voltage to the second active region AR2 in the substrate SUB.

13 is another example (10d) of the second layout changed from the first layout by data polishing according to an embodiment of the present invention.

13, in the mask data preparing step, the height of the first power contact CA_P1 of the first layout 10d along the second direction is decreased and the height of the first and second power contact patterns CA_P1 and CA_P2 is reduced. The second layout 20d can be generated by disposing the second contact CB2 connected to the second layout 20d. At this time, since the first and second power contact patterns CA_P1 and CA_P2 can be applied with the same voltage, the first and second power contact patterns CA_P1 and CA_P2 can be connected.

Specifically, in the first layout 10d, the first power contact pattern CA_P1 is designed in a different color from the first source / drain contact pattern CA_SD1, but in the second layout 20d, CA_P1 may be changed to the same color as the first source / drain contact pattern CA_SD1. Accordingly, when an integrated circuit is manufactured based on the second layout 20d, the first power contact pattern CA_P1 and the first source / drain contact pattern CA_SD1 can be patterned with the same mask. Therefore, when manufacturing an integrated circuit based on the second layout 20d, it is possible to pattern the first contact CA using three masks.

The second layout 20d may include a first power contact CA_P1 ', a second power contact CA_P2 and a second contact CB2 having a second height H2 along a second direction. At this time, the distance D4 'between the first source / drain contact CA_SD1 and the first power contact CA_P1' may be greater than the patterning resolution limit and thus the first source / drain contact CA_SD1 and the first The power contact CA_P1 'can be formed using one mask.

A second contact (CA_P ', CA_P2) having a bridge pattern on the first and second power contact patterns CA_P1', CA_P2 in the second layout 20d and connected to the first and second power contact patterns CA_P ' CB2 may be disposed. As the height of the first power contact CA_P1 'in the second layout 20d decreases, the via V can be placed only on the second power contact CA_P2.

Therefore, according to the present embodiment, the second layout 20d can reduce the number of masks required to form the first contact by one compared to the first layout 10d. In other words, when the integrated circuit is formed using the second layout 20d, the first contacts can be formed using three masks.

14 is a flowchart showing a layout design method of an integrated circuit according to an embodiment of the present invention.

14, the layout design method of the integrated circuit according to the present embodiment does not include the step of forming an integrated circuit as compared with the method of manufacturing the integrated circuit illustrated in FIG. 1, and the contents of steps S110 to S230 are But can also be applied to the embodiment. Therefore, the above-described contents with reference to Figs. 2 to 13 can also be applied to this embodiment.

In step S310, a first layout is designed by arranging and wiring a plurality of standard cells defining an integrated circuit.

In step S320, in the mask data preparation for the first layout, the second layout is generated by changing the first layout. Specifically, a second layout can be generated by connecting the first and second patterns of the first layer patterns to each other so that the number of masks required for forming the first layer patterns corresponding to the first layer of the first layout is reduced have.

In one embodiment, the first layer may be a contact (e.g., a first contact (CA)) that is electrically connected to the active area of the integrated circuit and is to be formed on the active area. In one embodiment, the first and second patterns may be arranged parallel to one another along the first direction and extend in a second direction substantially perpendicular to the first direction. For example, the first and second patterns may be the first and second power contact patterns CA_P1, CA_P2 of the first layout 10d illustrated in FIG. 7D. In one embodiment, the first layer patterns may further include a third pattern. For example, the third pattern may be the first source drain contact pattern CA_SD1 of the first layout 10d illustrated in Fig. 7D.

In one embodiment, by merging the first and second power contact patterns CA_P1 and CA_P2, the first and second power contact patterns CA_P1 and CA_P2 are formed by merging the first and second power contact patterns CA_P1 and CA_P2, A second layout (e.g., 20a in Fig. 8) including a new pattern CA_P having a width W1 of 1 and being capable of being formed with one mask can be generated.

In another embodiment, the first and second power contact patterns CA_P1 and CA_P2 have an H shape including a bridge pattern BR connecting the first and second power contact patterns CA_P1 and CA_P2 and the first and second power contact patterns CA_P1 and CA_P2, A second layout (e.g., 20b in Fig. 10) including a new pattern CA_P 'that can be formed with one mask can be generated.

In another embodiment, the heights along the second direction are reduced relative to the first and second power contact patterns CA_P1, CA_P2, and the first and second power contact patterns CA_P1 ' (E.g., 20_c of FIG. 11) that includes a second layer that is commonly connected to the first and second power contact patterns CA_P2 ', CA_P2', and the new first and second power contact patterns CA_P1 ', CA_P2' . At this time, the second layer may be a second contact CB1 to be formed on at least one of the plurality of conductive lines CL and the new first and second power contact patterns CA_P1 ', CA_P2'.

In another embodiment, the first and second power contact patterns CA_P1 and CA_P2 may have a second, third, and fourth contact pattern CA_P1 and CA_P2, such that the distance from the third pattern, e.g., the first source / drain contact pattern CA_SD1, A new first power contact pattern CA_P1 'and a new first power contact pattern CA_P2' which are reduced in height along the direction and can be formed with the same mask as the first source / drain contact pattern CA_SD1, (E. G., 20d in Fig. 13) that includes a second layer in the form of a bridge connecting two power contact patterns. At this time, the second layer may be a second contact CB2 to be formed on at least one of the plurality of conductive lines CL, a new first power contact pattern CA_P1 'and a second power contact pattern CA_P2 have.

In one embodiment, the first and second power contact patterns are included in a first standard cell and patterns other than the first and second power contact patterns of the first layer patterns are arranged in a first direction And may be included in a second standard cell arranged adjacent to the first standard cell.

In another embodiment, the first power contact pattern is included in a first standard cell, the second power contact pattern is included in a second standard cell disposed adjacent to a first standard cell in a first direction, Patterns other than the first and second power contact patterns may be included in a third standard cell disposed adjacent to the first and second standard cells in a second direction.

15 is a block diagram illustrating a storage medium 500 according to one embodiment of the present disclosure.

15, storage medium 500 is a computer-readable storage medium, which may include any storage medium that can be read by a computer while it is being used to provide instructions and / or data to a computer . For example, the computer-readable storage medium 500 may be a magnetic or optical medium such as a disk, a tape, a CD-ROM, a DVD-ROM, a CD-R, a CD-RW, a DVD- Volatile or nonvolatile memory such as ROM, flash memory, etc., nonvolatile memory accessible through a USB interface, and microelectromechanical systems (MEMS). The computer readable storage medium can be embedded in a computer, integrated into a computer, or coupled to a computer via a communication medium such as a network and / or a wireless link.

15, a computer-readable storage medium 500 may include a placement and routing program 510, a library 520, an analysis program 530, and a data structure 540. The placement and routing program 510 may include a plurality of instructions to perform a method of designing an integrated circuit using a standard cell library according to an exemplary embodiment of the present invention. For example, the computer-readable storage medium 500 may include any arrangement for designing an integrated circuit using a standard cell library including standard cells shown in one or more of the preceding figures, and The wiring program 510 can be stored. The library 520 may include information on a standard cell that is a unit constituting an integrated circuit.

The analysis program 530 may include a plurality of instructions that perform a method of analyzing an integrated circuit based on data defining the integrated circuit. For example, the computer-readable storage medium 500 may include an arbitrary number of masks to determine whether the number of masks required to form the first layer of the first layout designed by placing and wiring standard cells defining the integrated circuit is greater than or equal to a threshold value Lt; RTI ID = 0.0 > 530 < / RTI > The data structure 540 may be generated by using the standard cell library included in the library 520 or by extracting specific information from the generic standard cell library included in the library 520 or by analyzing the properties of the integrated circuit And a storage space for managing data generated in the process of analyzing the data.

16 is a block diagram illustrating a memory card including an integrated circuit according to one embodiment of the present disclosure;

Referring to FIG. 16, the memory card 1000 may be arranged such that the controller 1100 and the memory 1200 exchange electrical signals. For example, when the controller 1100 issues a command, the memory 1200 can transmit data.

The controller 1100 and the memory 1200 may include an integrated circuit according to embodiments of the present invention. Specifically, the pin transistor included in at least one of the semiconductor elements of the plurality of semiconductor elements included in the controller 1100 and the memory 1200 can be selected from the first layout designed by the layout and wiring tool And may be formed on the basis of the changed second layout. The second layout may be generated by connecting first and second patterns of the first layer patterns corresponding to the first layer of the first layout, in order to reduce the number of masks required to form the first layer.

The memory card 1000 may include various types of cards such as a memory stick card, a smart media card (SM), a secure digital card (SD), a mini-secure digital card a mini-secure digital card (mini SD), and a multimedia card (MMC).

17 is a block diagram illustrating a computing system including an integrated circuit in accordance with one embodiment of the present disclosure;

17, a computing system 2000 may include a processor 2100, a memory device 2200, a storage device 2300, a power supply 2400, and an input / output device 2500. 17, the computing system 2000 may further include ports capable of communicating with, or communicating with, video cards, sound cards, memory cards, USB devices, and the like .

As described above, the processor 2100, the memory device 2200, the storage device 2300, the power supply 2400, and the input / output device 2500 included in the computing system 2000 can be implemented in the embodiment according to the technical idea of the present invention Lt; RTI ID = 0.0 > IC < / RTI > Specifically, in at least one of the plurality of semiconductor elements included in the processor 2100, the memory device 2200, the storage device 2300, the power supply 2400, and the input / output device 2500, The pin transistor included in the semiconductor element can be formed based on the second layout changed from the first layout designed by the layout and wiring tool in the mask data preparation. The second layout may be generated by connecting first and second patterns of the first layer patterns corresponding to the first layer of the first layout, in order to reduce the number of masks required to form the first layer.

Processor 2100 may perform certain calculations or tasks. According to an embodiment, the processor 2100 may be a micro-processor, a central processing unit (CPU). The processor 2100 is coupled to the memory device 2200, the storage device 2300, and the input / output device 2500 via a bus 2600, such as an address bus, a control bus, and a data bus, Lt; / RTI > In accordance with an embodiment, the processor 2100 may also be coupled to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device 2200 may store data necessary for operation of the computing system 2000. For example, the memory device 2200 may be implemented as a DRAM, a mobile DRAM, an SRAM, a PRAM, an FRAM, an RRAM, and / or an MRAM. have. The storage device 2300 may include a solid state drive, a hard disk drive, a CD-ROM, and the like.

The input / output device 2500 may include input means such as a keyboard, a keypad, a mouse, etc., and output means such as a printer, a display, and the like. The power supply 2400 may supply the operating voltage required for operation of the computing system 2000.

The integrated circuit according to the embodiments of the present invention described above can be implemented in various types of packages. For example, at least some configurations of an integrated circuit may be implemented using a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC), plastic dual in- , Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package Package (WSP) or the like.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

SC, SC1, SC2: standard cell
10a, 10b, 10c, 10d: a first layout
20a, 20b, 20c, 20d: a second layout
100a, 100b, 200a, 200b, 200c:

Claims (10)

Designing a first layout by arranging and wiring a plurality of standard cells defining an integrated circuit; And
Generating a second layout by modifying the first layout in a mask data preparation process for the first layout, the method comprising: forming first layer patterns corresponding to a first layer of the first layout Generating the second layout by connecting first and second patterns of the first layer patterns to each other such that the number of masks required for the second layer patterns is reduced. The method according to claim 1,
Wherein the first and second patterns are arranged parallel to each other along a first direction and extend in a second direction perpendicular to the first direction. 3. The method of claim 2,
Wherein the generating the second layout comprises:
And a second pattern having a first width larger than the width along the first direction of each of the first and second patterns by merging the first and second patterns, 2 layout of the integrated circuit is generated. 3. The method of claim 2,
Wherein the generating the second layout comprises:
The second layout having an H shape including a bridge pattern connecting the first and second patterns and the first and second patterns and including a new pattern that can be formed with one mask, A layout design method for an integrated circuit. 3. The method of claim 2,
Wherein the generating the second layout comprises:
The first and second patterns are reduced in height relative to the first and second patterns in the second direction and can be formed with a single mask and the first and second patterns are formed in common to the new first and second patterns And the second layout including the second layer to be connected is generated. 6. The method of claim 5,
Wherein the first layout further comprises a plurality of conductive lines disposed in parallel with the first and second patterns,
Wherein the second layer is a contact to be formed on at least one of the plurality of conductive lines and the new first and second patterns. 3. The method of claim 2,
Wherein the generating the second layout comprises:
A height of the first layer pattern in the second direction is reduced relative to the first and second patterns so that a distance between the first and second patterns is greater than a critical distance, The second layout including a new first pattern and a second layer in the form of a bridge connecting the new first pattern and the second pattern are generated. 8. The method of claim 7,
Wherein the first layout further comprises a plurality of conductive lines disposed in parallel with the first and second patterns,
Wherein the second layer is a contact to be formed on at least one of the plurality of conductive lines, the new first pattern, and the second pattern. The method according to claim 1,
Wherein the first layer is a contact to be formed on the active region and electrically connected to the active region of the integrated circuit,
Wherein the first and second patterns correspond to the first and second power contact patterns, respectively. Providing a standard cell library containing information about a plurality of standard cells defining an integrated circuit;
Designing a first layout by arranging and wiring the plurality of standard cells;
Determining whether the number of masks necessary for forming the first layer patterns corresponding to the first layer of the first layout is equal to or greater than a threshold value in the step of preparing mask data for the first layout;
Generating a second layout by changing the first layout when the number of masks necessary for forming the first layer patterns is equal to or larger than the threshold value; And
And forming the integrated circuit on the basis of the second layout.

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