KR20160009845A - Shift register and display device using the same - Google Patents

Abstract

The present invention relates to a shift register for enhancing reliability by outputting a complex waveform having different period with simple circuit and a display device using the same. The shift register comprises clusters, and each of the clusters includes output stages for outputting respectively output signals and one carry stage for outputting a carry signal. Each of the output stages and the carry stage comprise an output unit for outputting a clock or a first low voltage according to logic of a first node and a second node and a first node control unit for setting the first node to set state or resetting the first node to reset state according to a carry signal outputted from previous cluster or a set signal supplied from an external device, and a carry signal outputted from next cluster or a reset signal supplied from an external device. At least one of the output stages includes a second node control unit for controlling its second node contrary to a first node of any one of the output stages. Second nodes of two or more stages in each of the clusters are connected each other.

Description

[0001] SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register, and more particularly, to a shift register capable of improving reliability by outputting composite waveforms having different periods with a simple structure and a display using the shift register.

2. Description of the Related Art [0002] Flat panel display devices that have recently become popular as display devices include liquid crystal displays (LCDs) using liquid crystals, OLED display devices using organic light emitting diodes (OLEDs) Display devices (ElectroPhoretic Display; EPD), and the like.

A flat panel display device includes a display panel for displaying an image through a pixel array in which each pixel is independently driven by a thin film transistor (TFT), a panel driver for driving the display panel, a timing controller And the like. The panel driver includes a gate driver for driving the gate lines of the display panel and a data driver for driving the data lines of the display panel.

Recently, a gate driver is formed together with a TFT array of a pixel array to mainly use a gate-in-panel (GIP) method built in a panel. The gate driver outputs scan pulses for driving the gate lines using a shift register.

In general, each gate line is supplied with a scan pulse having the same period as another scan pulse and having a different output timing. However, when control of each pixel circuit is complicated, such as an OLED display device, scan pulses having different periods Combined composite waveforms may be required.

A structure may be considered in which a plurality of stage outputs are multiplexed and output to each gate line in order to output a plurality of scan pulses having different pulse widths or timings to each gate line. In this case, however, since the structure of the shift register becomes too complicated, There is a problem that it is difficult to realize a built-in driver of a display device due to an increase in circuit size.

To solve this problem, there is a demand for a shift register capable of outputting a scan pulse of a composite waveform in a simple circuit configuration.

  SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a shift register capable of improving reliability by outputting composite waveforms of different periods with a simple structure and a display device using the shift register will be.

According to an aspect of the present invention, there is provided a shift register including a plurality of clusters, each of the plurality of clusters including a plurality of output stages for outputting a plurality of output signals, Lt; / RTI > stage. Each of the plurality of output stages and the carry stage generating an output as a clock or a first undervoltage according to a logic state of a first node and a second node; And a first node controller for setting the first node to a set state or resetting the first node to a reset state according to a set signal, a carry signal output from the next stage cluster, or a reset signal supplied from the outside. Wherein at least one of the plurality of output stages includes a second node control unit controlling a second node of the plurality of output stages in opposition to a first node of any one of the plurality of output stages, The second nodes belonging to at least two stages of the stages are connected to each other.

Wherein the first node controller includes a set transistor for supplying a first high voltage to the first node under the control of the set signal and a second reset transistor for supplying a second low voltage to the first node in accordance with the control of the reset signal, Or a reset section for supplying a third low voltage to the first node under the control of the second node together with the set transistor and the first reset transistor.

Wherein the reset unit includes a second reset transistor for supplying the third low voltage to the first node under the control of the second node, or the second reset transistor is connected in series with the second reset transistor, A third reset transistor for supplying the third low voltage to the second reset transistor under the control of the second node, and a second reset transistor for supplying the high voltage to the connection point between the second and third reset transistors under the control of the first node And a fourth reset transistor.

Wherein the second node control unit controls the second node such that the second node is in a logical state opposite to the first node of any one of the plurality of output stages, And a reset transistor which, together with the inverter, supplies the fourth low voltage to the second node under the control of the set signal.

The output nodes belonging to each cluster and the first node of the carry stage are separated from each other, while the second nodes are connected to each other.

And the second node control unit is provided in one of the output stages belonging to each cluster and the carry stage.

The output stages belonging to each cluster and the set signals supplied to the carry stage are the same or different from each other, and the output stages belonging to each cluster and the reset signal supplied to the carry stage are the same or different from each other.

Wherein the first and second high voltages are equal to or different from each other, the first to fourth low voltages are equal to or different from each other, and the first low voltage supplied to the output portion of the output stage belonging to each cluster, The first undervoltage supplied to the output portion of the carry stage is equal to or different from each other.

Wherein when each of the clusters includes m (m is a natural number) output stages, the clock includes at least an m-phase circulating clock, the m-phase clocks are supplied to the m output stages, a clock identical to any one of the m-phase clocks is supplied, or a carry clock having a phase different from that of the m-phase is supplied.

Wherein each of the m-phase clocks includes a plurality of pulses in a clock output period, the clock output interval including a first period and a second period is repeated, and the m-phase clocks in the respective clock output periods have different pulse widths Respectively.

Wherein the m-phase clock includes a first pulse that overlaps with each other in the first period, and a second pulse that does not overlap with each other in the second period or partially overlaps with an adjacent clock, Each output stage outputs a different clock including the first and second pulses in a clock output period corresponding to the cluster. The carry stage belonging to each cluster outputs a carry clock that does not overlap with the first and second pulses in the clock output period.

The display device according to the present invention drives the gate line of the display panel using the shift register.

Since the shift register according to the present invention has a simple structure based on a basic shift register while outputting complex waveforms having different periods, it is possible to improve the reliability, and also to provide a display device requiring a complex waveform such as an OLED display It is suitable to be implemented as a built-in driver.

The display device using the shift register according to the present invention can drive the gate lines of the display panel into a composite waveform by applying the shift register to the GIP type gate driver incorporated in the display panel and the circuit configuration is simple, Suitable.

1 is a block diagram showing a basic structure of a shift register according to the present invention.
Fig. 2 is a circuit diagram showing a basic configuration of an output section applied to one stage shown in Fig. 1. Fig.
3 is a circuit diagram showing, for example, an output portion of one cluster shown in Fig.
FIG. 4 is a circuit diagram showing another example of the third output stage shown in FIG. 3 and the output portion applied to the carry stage.
5 is a circuit diagram showing another example of the output portion of one cluster shown in Fig.
FIG. 6 is a circuit diagram showing a first node controller of one cluster shown in FIG. 1, for example.
FIG. 7 is a circuit diagram showing a second node controller of one cluster shown in FIG. 1, for example.
8 is a circuit diagram showing a stage according to an embodiment of the shift register shown in FIG.
9 is a circuit diagram showing various embodiments of the inverter shown in Fig.
10 is a circuit diagram showing various examples of the reset unit added to the first node control unit of the stage shown in FIG.
11 is a circuit diagram showing a stage according to another embodiment in the shift register shown in FIG.
12 is a circuit diagram showing a cluster in a shift register according to an embodiment of the present invention.
13 is a driving waveform diagram of the cluster shown in Fig.
14 is another driving waveform diagram of the cluster shown in Fig.
15 is a diagram showing a simulation result of the drive waveform shown in Fig.
FIG. 16 is a diagram showing only the scan signal among the drive waveforms shown in FIG.

1 is a block diagram showing a basic structure of a shift register according to an embodiment of the present invention.

The shift register shown in FIG. 1 is used as a built-in gate driver of an active matrix display device and has a plurality of clusters CT1, CT2,... Including a plurality of stages.

Each cluster CT has m output stages ST1 to STm for outputting m scan signals G1 to Gm to m (m is a natural number not less than 3) gate lines, And a carry stage CS for outputting the carry signal CR to the carry stage CS.

Specifically, the first cluster CT1 includes first through m-th output stages ST1 through STm for outputting scan signals G1 through Gm to m gate lines of the first group, (CR1) to the next stage cluster (CT2). The second cluster CT2 includes the (m + 1) th to (2m) th output stages STm + 1 to ST2m for outputting the scan signals Gm + 1 to G2m to the m gate lines of the second group, And a second carry stage CS2 for outputting the carry signal CR2 to the next stage cluster. Here, the second carry signal CR2 may be output to the previous stage cluster CT1 or not output.

Each of the output stages ST1 to STm and the carry stage CS belonging to each cluster CT are connected to the logic of the first node (hereinafter Q node) and the second node (hereinafter, QB node) And an output section for outputting a clock (CLKn) or a low potential voltage (VSS) to the output node in accordance with the voltage (voltage) state.

The low-potential voltage VSS can be expressed by a gate-low voltage or a gate-off voltage.

M output stages ST1 to STm belonging to each cluster CT output scan signals G1 to Gm to m gate lines, respectively. The scan signal G supplied to each gate line has a complex waveform in which a plurality of scan pulses having different periods are combined.

The carry stage CS belonging to each cluster CT does not drive the gate line and is used as a set signal to set the Q node of the stages included in the next stage cluster to a high state, And is used as a reset signal for resetting the Q node to the low state.

Hereinafter, a set state indicating a high state of the corresponding node may be expressed as a gate-on state, and a reset state indicating a low state of the node may also be expressed as a gate-off state.

The output stage ST and the carry stage CS belonging to each cluster CT set the Q node to the high state in response to the start signal Vst from the outside or the carry signal from the carry stage belonging to the previous stage cluster , And resets the Q node to the low state in response to the carry signal from the carry stage belonging to the next-stage cluster.

Alternatively, the reset signal for resetting the Q node may be supplied separately from the external circuit. The external circuit may be a timing controller that generates and supplies the start signal Vst and the clocks CLKs or a reset circuit included in the built-in gate driver and generates and supplies a reset signal using the input / output signal of the shift register.

Each of the output stage ST and the carry stage CS belonging to each cluster CT is connected to at least one of a plurality of clock lines supplying a plurality of clocks CLKs. When each cluster CT includes m output stages ST1 to STm, the plurality of clocks CLKs include circulating clocks of m-phase or more, and clocks CLKs of m-phase or more are included in each cluster CT . M-phase clocks, that is, different clocks are supplied to the m output stages ST1 to STm belonging to each cluster CT, and m-phase clocks may partially overlap each other. A carry clock different from the m-phase clock is supplied to the carry stage CS belonging to each cluster CT or a clock identical to any one of the m output stages ST1 to STm belonging to the cluster CT is supplied .

At least two of m output stages ST1 through STm and one carry stage CS belonging to each cluster CT may share at least one of the Q node and the QB node. At least two of the m output stages (ST1 to STm) belonging to each cluster (CT) can share the QB node. A carry stage (CS) belonging to each cluster (CT) can share a Q node with any one of the m output stages.

2 is a circuit diagram showing a basic configuration of an output section applied to each stage shown in Fig.

2, the output unit includes a pull-up transistor Tup for outputting one of the clocks CLKn to the output node in accordance with the logic state of the Q node, and a pull-up transistor Tup for outputting a low potential voltage VSS according to the logic state of the QB node. Down transistor (Tdn) for outputting the pull-down signal to the output node. The pull-up transistor Tup supplies the clock CLKn to the output node when the Q node is in the high state and the pull-down transistor Tdn supplies the low potential And supplies the voltage VSS to the output node.

3 is a circuit diagram showing an output unit according to the first embodiment of each cluster shown in FIG.

3 illustrates a case where one cluster CT1 includes three output stages ST1 to ST3 and one carry stage CS1 and outputs the outputs of the output stages ST1 to ST3 and the carry stage CS1 .

The first to third output stages ST1 to ST3 respectively output scan signals G1 to G3 to the first to third gate lines and the first carry stage CS1 outputs the first And outputs a carry signal CR1. The first to third clocks CLK1 to CLK3 of three phases are supplied to the first to third output stages ST1 to ST3 respectively and the carry clock CLKc is supplied to the first carry stage CS1.

The pull-up transistor Tup1 of the first output stage ST1 outputs the first clock CLK1 to the scan signal G1 of the first gate line through the output node when the node Q1 is in a high state, The pull-up transistor Tup2 of the output stage ST2 outputs the second clock CLK2 through the output node to the scan signal G2 of the second gate line when the node Q2 is in the high state, Up transistor Tup3 in the third stage ST3 outputs the third clock CLK3 to the scan signal G3 of the third gate line through the output node when the node Q3 is in the high state, The pull-up transistor Tup-C outputs the carry clock CLKc to the first carry signal CR1 through the output node when the Qr node is in a high state.

The pull-down transistors Tdn1 to Tdn3 of the first to third output stages ST1 to ST3 are turned on when the nodes QB1 to QB3 are respectively in a high state and the low potential voltage VSS0 is applied to the scan signals G1- G3. The pull-down transistor Tdn-C of the carry stage CS1 outputs the low potential voltage VSS1 to the carry signal CR1 through the corresponding output node when the QBr node is in a high state.

The carry stage CS1 belonging to one cluster (CTI) shares at least one of the Qr node and the QBr node with at least one of the output stages ST1 to ST3 belonging to the cluster CT1, or shares the clock CLK3 can do.

For example, the QB1 to QB3 nodes of the output stages ST1 to ST3 belonging to one cluster CT1 and the QBr nodes of the carry stage CS1 may be connected to each other as shown in Fig.

Alternatively, as shown in FIG. 4, the Qr node of the carry stage CS1 belonging to one cluster CT1 may share the Q3 node of the adjacent output stage ST3, or the QBr node of the carry stage CS1 may be adjacent to the output The QB3 node of the stage ST3 is shared or the pull-up transistor Tup-C of the carry stage CS1 shares the clock CLK3 supplied to the pull-up transistor Tup3 of the adjacent output stage ST3 can do.

The low potential voltage VSS0 supplied to the output stages ST1 through ST3 belonging to one cluster CT1 and the low potential voltage VSS1 supplied to the carry stage CS1 may be different or the same, The low potential power lines can be shared with each other. When the carry signal CR is used as the reset signal of the previous stage cluster, the low potential voltage VSS1 used for the low voltage of the carry signal CR is set to the low voltage of the scan signal May be lower than the low potential voltage VSS0 used.

5 is a circuit diagram showing another example of the output portion of one cluster shown in Fig.

5, the output stages ST1 to ST3 belonging to one cluster CT1 and the carry stage CS1 are different from those of FIG. 3 in that they each include at least two QB nodes. At least two QB nodes provided in each stage alternately operate in a high state every predetermined period, and a QB node not operating in a high state maintains a low state.

For example, the output part of the first output stage ST1 belonging to one cluster CT1 includes a first pull-down transistor Tdn11 switched by the control of the QB11 node, and a second pull- And a second pull-down transistor Tdn12 switched by control of the QB12 node. The output of the second output stage ST2 includes a first pull-down transistor Tdn21 switched by the control of the QB21 node and a second pull-down transistor Tdn21 switched by control of the QB22 node, - down transistor Tdn22. The output of the third output stage ST3 includes a first pull-down transistor Tdn31 that is switched under the control of the QB31 node and a second pull-down transistor Tdn31 that is switched by control of the QB 32 node, - down transistor Tdn32. The output of the carry stage CS1 includes a first pull-down transistor Tdn-C1 switched under the control of the QBr1 node and a second pull-down transistor Tdn-C1 switched by control of the QBr2 node, - down transistor Tdn-C2.

The Qr node of the carry stage CS1 belonging to one cluster CT1 may share the Q3 node of the adjacent third output stage ST3. The pull-up transistor Tup-C of the carry stage CS1 shares a clock CLK3 supplied to the pull-up transistor Tup3 of the adjacent third output stage ST3, or a separate carry clock CLKc, Can be input.

6 is a circuit diagram showing an example of a node controller of one cluster shown in FIG.

6, each of the output stages ST1 to ST3 and the carry stage CS1 belonging to a cluster CT1 has a node control unit for controlling the nodes Q1 to Q3 and the node Qr to a set state or a reset state, respectively do. The node controller of each of the stages ST1 to ST3 and CS1 sets the Q node to the high state using the high potential voltage VD under the control of the set signal Vs (i), i = 1, 2, (I = 1, 2, 3, 4) and the low potential voltage VSS2 according to the control of the reset signal Vrs And a reset transistor Ti2 (i = 1, 2, 3, 4) for resetting to a low state. The set signal Vs uses the external set signal or the carry signal of the previous stage cluster, and the reset signal Vrs uses the external reset signal or the carry signal of the next stage cluster. The high-potential voltage VDD can be expressed by a gate-on voltage, a gate high voltage, or the like. VSS2 may be equal to or higher than VSS1, VSS0.

Specifically, the node control section of the output stage ST1 responds to the control of the set signal Vs1 by providing a set transistor T11 for supplying the high potential voltage VD to the node Q1 to set the node Q1 to a high state, And a reset transistor T12 for supplying the low potential voltage VSS2 to the node Q1 in response to the control of the signal Vrs1 to reset the node Q1 to the low state. The node control section of the output stage ST2 responds to the control of the set signal Vs2 by setting the set transistor T21 to supply the high potential voltage VD to the node Q2 to set the node Q2 to the high state, And a reset transistor T22 for supplying the low potential voltage VSS2 to the node Q2 in response to the control of the reset transistor Vrs2 to reset the node Q2 to the low state. The node control section of the output stage ST3 includes a set transistor T31 for supplying the high potential voltage VD to the node Q3 in response to the control of the set signal Vs3 to set the node Q3 to the high state, And a reset transistor T32 for supplying the low potential voltage VSS2 to the node Q3 in response to the control of the reset transistor T32 to reset the node Q3 to the low state. The node control section of the carry output stage CS1 responds to the control of the set signal Vs3 by a set transistor T41 which supplies the high potential voltage VD to the node Qr to set the node Qr to a high state, And a reset transistor T42 for supplying the low potential voltage VSS2 to the Qr node in response to the control of the reset transistor T42 to reset the Qr node to the low state.

The set signals Vs1 to Vs3 may use an external set signal or a carry signal from the previous stage cluster. The reset signals Vrs1 to Vrs3 may use an external reset signal or a carry signal from the next stage cluster. The same signals can be used for the set signals Vs1 to Vs3 belonging to one cluster CT1 or the same signals can be used for the reset signals Vrs1 to Vrs3 belonging to the cluster CT1. In this case, the number of input lines in each cluster can be reduced.

FIG. 7 is a circuit diagram showing a second node controller of one cluster shown in FIG. 1, for example.

Referring to FIG. 7, one cluster CT1 includes a QB reset unit for resetting the QB node to a low state to smooth the set operation of the Q node. The QB reset section responds to the control signal Vpr and supplies the power supply voltage VSSn to the nodes QB1 to QB3 and QBr nodes of the output stage ST1 to ST3 belonging to one cluster CT1 and the carry stage CS1 in common And a reset transistor Tr3 for supplying the reset transistor Tr3.

The control signal Vpr can use an external reset signal or a carry signal from the front cluster. The power supply voltage VSSn may be the low potential voltage VSS3 of the DC power supply maintaining the low level or alternatively may be an AC power supply having the high level and the low level alternately applied at regular intervals. At least two clusters may share the power supply voltage VSSn.

8 is a circuit diagram showing one stage in the shift register shown in FIG.

The stage shown in Fig. 8 is applied to each of the output stages ST1 to STm and the carry stage CS of each cluster CT shown in Fig. 1, in which one stage controls the output node and the Q node of the output node And a second node control unit for controlling the QB node of the output unit.

The output section includes a pull-up transistor (Tup) for outputting a clock (CLKn) through an output node in response to the control of the Q node and a pull-up transistor (Tup) for outputting a low potential - down transistor Tdn. When the Q node is in the set (high) state, the pull-up transistor Tup outputs the clock CLKn through the output node, and when the QB node is in the set (high) And outputs the low potential voltage VSS1 through the output node.

The first node control unit includes a set transistor T1 for setting the Q node to a high state to a high potential voltage VD in response to the control of the set signal Vs, And a reset transistor T2 for resetting the Q node to a low state by a reset signal VSS2.

The second node control unit includes an inverter (INV) controlling the QB node in contradiction with the Q node. The inverter INV resets the QB node to a low state with the low potential voltage VL when the Q node is in the set (high) state and the QB node with the high potential voltage VH when the Q node is in the reset (low) State. The high-potential voltage VH supplied to the inverter INV may be equal to or different from the high-potential voltage VD supplied to the set transistor Tl. The low potential voltage VL supplied to the inverter INV may be equal to or different from the potential voltage VSS2 supplied to the reset transistor T2 and the low potential voltage VSS1 supplied to the pull-down transistor Tdn .

9 is a circuit diagram showing various embodiments of the inverter shown in Fig.

The inverter shown in FIG. 9A includes a first transistor Ta connected in a diode structure between a supply line of a high-potential voltage (VH) and a QB node, and a first transistor (Ta) And a second transistor (Tb) for supplying the second transistor (Tb) to the QB node.

When the second transistor Tb is turned off by the low state of the Q node, the QB node is charged to the high-potential voltage VL through the first transistor Ta that is turned on, and is set. If the second transistor Tb is turned on by the high state of the Q node even though the first transistor Ta of the diode structure is in the turned-on state, the QB node is turned on via the second transistor Tb VL) to be reset. For this, the second transistor Tb is formed to have a larger channel width than the first transistor Ta.

The inverter shown in Fig. 9 (b) differs from the inverter shown in Fig. 9 (a) in that the first transistor Ta is not controlled by a diode structure but is controlled by a separate control signal CL . As the control signal CL, a clock can be used.

The inverter shown in FIG. 9 (c) includes a first transistor Ta to a fourth transistor Td.

The first transistor Ta supplies the high potential voltage VH to the node A in response to the control signal CL and the second transistor Tb supplies the low potential voltage VL The third transistor Tc supplies the high potential voltage VH to the QB node in response to the control of the A node and the fourth transistor Td supplies the high voltage VH to the QB node in response to the control of the Q node. And supplies the potential voltage VL.

When the Q node is in the low state, the second and fourth transistors Tb and Td are turned off and the node A is turned on when the first transistor Ta is turned on by the control signal CL. VH), and the QB node charges the high-potential voltage (VH) through the third transistor (Tc) turned on under the control of the charged A node, and is set to the high state. The second and fourth transistors Tb and Td are turned on when the Q node is in a high state and the A node is turned on when the first transistor Ta is turned on by the control signal CL, The third transistor Tc is turned off under the control of the discharged A node and the QB node is turned on via the fourth transistor Td to the low potential voltage VL ) And is reset to the low state.

The inverter shown in Fig. 9 (d) differs from the inverter shown in Fig. 9 (c) in that the first transistor Ta has a diode structure.

The inverter shown in FIG. 9 (e) includes a second transistor Tb, a fifth transistor Te, and a capacitor C.

The capacitor C supplies any one of the clocks CLKn to the QB node. The second transistor Tb supplies the low potential voltage VL to the QB node in response to the control of the Q node. The fifth transistor Te couples the Q node and the output node in response to the control of the QB node. The clock CLKn is a clock that overlaps with the output signal out.

The inverter shown in Fig. 9 (f) is different from the inverter shown in Fig. 9 (b) in that a clock CLK1 is supplied as the control signal CL of the first transistor Ta, There is a difference in that a third transistor Tc controlled by another clock CLK2 is additionally connected between the potential supply line VL. The third transistor Tc supplies the low potential voltage VL to the QB node in response to control of the other clock CLK2.

The inverter shown in Fig. 9 (g) differs from the inverter shown in Fig. 9 (f) in that the first transistor Ta is connected in a diode structure to the clock (CLK1) input line.

The inverter shown in FIG. 9H is supplied with one clock CLK1 as the control signal CL of the first transistor Ta, and the second and the third clocks CLK1 and CLK2 are supplied as compared with the inverter shown in FIG. There is a difference in that the other clock CLK2 is supplied to the control signals of the four transistors Tb and Td. The first transistor Ta is turned on every time a clock CLK1 is in a high state to turn on the third transistor T3 through the node A to charge the QB node to the high potential VH And the second and fourth transistors Tb and Td discharge the QB node to the low potential voltage VL whenever the clock CLK2 is in the high state.

The inverter shown in Fig. 9 (i) is different from the inverter shown in Fig. 9 (d) in that the clock CLKn is supplied to the first and third transistors Ta and Tc in place of the high-potential voltage VH .

10 is a circuit diagram showing various examples of the additional reset unit added to the first node control unit of the stage shown in FIG.

10A has a reset transistor Tx and the reset transistor Tx supplies a low potential voltage VSS2 to the Q node in response to the control of the QB node to cause the Q node to be in a low state Lt; / RTI >

The additional reset portion shown in FIG. 10 (b) includes first to third reset transistors Tx1 to Tx3. The first and second reset transistors Tx1 and Tx2 are connected in series between the Q node and the low potential voltage supply line VSS2 and commonly controlled by the QB node to supply the low potential voltage VSS2 to the Q node. The third reset transistor Tx3 supplies the high potential voltage VD to the node between the first and second reset transistors Tx1 and Tx2 in response to the control of the Q node.

When the Q node is in the high state and the QB node is in the low state, the first and second reset transistors Tx1 and Tx2 are turned off so that the Q node maintains the floating state at the high state. When the QB node is in the high state, the first and second reset transistors Tx1 and Tx2 are turned on to supply the low potential voltage VSS2 to the Q node to maintain the Q node in the reset state.

The third reset transistor Tx3 is turned on when the Q node is in the high state and the QB node is in the low state to switch the high potential voltage VD to the connection point of the first and second reset transistors Tx1 and Tx2, 1 to the source electrode of the reset transistor Tx1 and the drain electrode of the second reset transistor Tx2. Accordingly, even when the threshold voltage of the first reset transistor Tx1 is shifted to the negative value, the gate-source voltage of the first reset transistor Tx1 is always kept at the threshold value when the first reset transistor Tx1 is turned off. The first reset transistor Tx1 can be kept in a completely turned-off state.

2. Description of the Related Art Oxide semiconductor transistors (hereinafter, referred to as oxide transistors), which have higher mobility than amorphous silicon transistors and are easier to apply for applications in a low temperature process than poly-silicon transistors, However, the oxide transistor is sensitive to light, and has a weak point that the threshold voltage (Vth) varies depending on the passage of light. However, even if the threshold voltage of the first reset transistor Tx1 shifts to a negative value due to the application of light, the third reset transistor Tx3 is turned off by the third reset transistor Tx3 when the first reset transistor Tx1 is turned off, Tx1 is higher than the gate voltage, the first reset transistor Tx1 can be kept in a completely turned-off state.

Thus, leakage current can be prevented when the Q node is in the high (set) state, and the high (set) state can be stably maintained. A different direct current voltage may be applied instead of the high potential voltage VD.

11 is a circuit diagram showing a stage according to another embodiment in the shift register shown in FIG.

11 is the same as the stage shown in Fig. 8 except that the set transistor T1, the reset transistor T2 (first reset transistor) and the pull-up transistor Tup are the same, and the QB node and the pull- Down transistors Tdn1 and Tdn2 which are controlled by nodes QB1 and QB2 respectively instead of the pull-down transistors Tdn and the first and second inverters INV1 and INV2 instead of the inverter INV, INV2, and further includes second and third reset transistors T3 and T4 respectively controlled by the QB1 and QB2 nodes to reset the Q node.

The QB1 and QB2 nodes alternately operate at regular intervals, for example, at least one frame, while the non-operational QB nodes maintain a low.

The first pull-down transistor Tdn1 is turned on when the QB1 node is in the high state to output the low potential voltage VSS1 through the output node.

The second pull-down transistor Tdn1 is turned on when QB2, which operates alternately with the QB1 node every predetermined period, is in the high state to output the low potential voltage VSS1 through the output node.

The first inverter INV1 causes the QB1 node to go to a low state using the low potential voltage VL when the Q node is in the high state and the QB1 node QB1 when the Q node is in the low state using the first power source voltage VH1. Makes the node high.

The second inverter INV2 causes the QB2 node to go to a low state by using the low potential voltage VL when the Q node is in the high state and the QB2 node by using the second power source voltage VH2 when the Q node is in the low state. Makes the node high.

The first power supply voltage VH1 and the second power supply voltage VH2 are alternating voltages alternately repeating a high voltage and a low voltage every fixed period.

The second reset transistor T3 supplies the low potential voltage VSS3 when the QB1 node is in a high state to maintain the Q node in a low (reset) state.

The third reset transistor T4 supplies the low potential voltage VSS3 when the QB2 node is in a high state to maintain the Q node in a low (reset) state.

The low potential voltages VSS1, VSS2, VSS3, and VL may be the same or different from each other.

If the low potential voltages are different, VSS2> VSS1, or VSS2> VSS3, and VSS3 may be greater than or equal to VL. Normally, VSS is expressed as negative, so even if VSS2> VSS1, abs (VSS2) <abs (VSS3) (abs is the absolute value). When VSS1 is a low voltage of a carry signal used as a reset signal Vrs, when the voltage is lower than VSS2, the first reset transistor T2 is completely turned off and the current leakage of the Q node through the first reset transistor T2 . If VSS3 is lower than VSS2, the second and third reset transistors T3 and T4 can keep the Q node in a low (reset) state with a voltage lower than that of the first reset transistor T2. When VL is lower than VSS3, when VL is supplied to the nodes QB1 and QB2 at a low voltage, the third and fourth transistors T3 and T4 are turned off completely and the second and third reset transistors T3 and T4 are turned off It is possible to prevent leakage of the current through the Q node.

12 is a circuit diagram showing a cluster representing a shift register according to an embodiment of the present invention.

The cluster CT shown in Fig. 12 has three output stages ST1 to ST3 and one carry stage CS.

Each of the output stages ST1 to ST3 and the carry stage CS includes an output unit Tup including a pull-up transistor Tup and a pull-down transistor Tdn, each of which is controlled by a corresponding Q node and a corresponding QB node, And a first node control unit (Ts, Tr1 to Tr4) for controlling the corresponding Q node. The first node control section Ts, Tr1 to Tr4 includes a set transistor Ts as a set, a first reset transistor Tr1 as a first reset section, and a second reset transistor Tr2 including a second to a fourth reset transistor Tr2 to Tr4. And a reset unit RS2.

The pull-up transistor Tup outputs one of the clocks CLK to its corresponding output (Tup, Tdn) in accordance with the logic state of the corresponding Q node at each of the output stages Tup and Tdn of the output stages ST1 to ST3 and the carry stage CS And the pull-down transistor Tdn outputs the low potential voltage VSS2 or VSS1 through the corresponding output node according to the logic state of the corresponding QB node. The low potential voltage VSS2 supplied to the pull-down transistor Tdn of the carry stage CR is equal to the low potential voltage VSS1 supplied to the pull-down transistor Tdn of each of the output stages ST1 to ST3 Or lower.

In each of the first node control sections Ts and Tr1 to Tr4 of the output stages ST1 to ST3 and the carry stage CS, the set transistor Ts, which is a set subtracter, The first reset transistor Tr1 supplies a low potential voltage VSS1 to the corresponding Q node according to the logic state of the reset signal Vrs, Thereby resetting the corresponding Q node. The output stages ST1 to ST3 and the carry stage CS receive the same set signal Vs and receive the same reset signal Vrs. An external signal or a carry signal from the previous stage cluster may be used as the set signal Vs and an external signal or a carry signal from the next stage cluster may be used as the reset signal Vrs.

In each of the first node control units Ts and Tr1 to Tr4, the second reset unit RS2 includes the second to fourth reset transistors Tr2 to Tr4, and the reset transistors RS1 and RS2 of the second reset unit RS2 Tr2 to Tr4 correspond to the reset transistors Tx1 to Tx3 shown in Fig. 10 (b), respectively. The second and third reset transistors Tr2 and Tr3 supply the low potential voltage VSS2 to the corresponding Q node according to the logic state of the QB node to reset the corresponding Q node to the low state. The fourth reset transistor Tr4 supplies the high potential voltage VD to nodes connected between the second and third reset transistors Tr2 and Tr3 according to the logic state of the Q node. The fourth reset transistor Tr4 applies a voltage VD higher than the gate electrode (QB node) to the source electrode of the second reset transistor Tr2 when the corresponding Q node is in the high state and the corresponding QB node is in the low state Causing the second reset transistor Tr2 to be completely turned off.

One of the output stages ST1 to ST3 and the carry stage CS shown in FIG. 12 includes an inverter INV for controlling the QB nodes QB1 to QB3 and QBr in a manner opposite to any one of the Q nodes, And a fifth reset transistor Tr5 which is a third resetting unit for resetting the QB nodes QB1 to QB3 and QBr.

The second node control unit INV and Tr5 are connected to any one of the Q stages of the output stages ST1 to ST3 and are connected to the output stages ST1 to ST3 belonging to one cluster CT and the QB nodes of the carry stage CS, (QB1 to QB3, QBr). In other words, each of the Q nodes (Q1 to Q3, Qr) of the three output stages (ST1 to ST3) and the carry stage (CS) belonging to one cluster (CT) The nodes QB1 to QB3 and QBr are connected to each other.

For example, the second node control unit (INV, Tr5) is located in the third output stage (ST3) adjacent to the carry stage (CS) as shown in Fig. 12 and the Q3 node of the third output stage QB3 node and the QB1 node and the QB2 node of the first and second output stages ST1 and ST2 and the QBr node of the carry stage CS are connected to the third output stage ST3 QB3 node. However, the second node control unit INV, Tr5 may be connected to the Q1 node of the first output stage ST1 or the Q2 node of the second output stage ST2.

The inverter INV turns the QB3 node into a logic state opposite to the Q3 node according to the logic state of the Q3 node of the third output stage ST3. In this way, the first to fourth transistors &lt; RTI ID = 0.0 &gt; (Ta to Td).

When the Q3 node is in a high state, the low potential voltage (VL = VSS3) is supplied to the node A by the turned-on first and second transistors Ta and Tb to turn off the third transistor Tc, Since the low potential voltage (VL = VSS3) is supplied to the node QB3 through the turned-on fourth transistor Td, the node QB3 is reset to the low state. The second and fourth transistors Tb and Td are turned off and the first and third transistors Ta and Tc are turned on when the Q3 node is in a low state. ), The high-potential voltage (VH) is supplied to the node QB3, so that the node QB3 is set to the high state.

The fifth reset transistor Tr5 which is the third reset section supplies the low potential voltage VSS3 = VL to the node QB3 according to the logic state of the set signal Vs so that the Q node is set to the high state by the set transistor Ts When set, the QB3 node is reset to the low state.

In the cluster CT shown in Fig. 12, any one output stage ST3 is connected between the node Q3 which is the gate electrode of the pull-up transistor Tup and the output node which is the source electrode of the pull-up transistor Tup And may further include a first capacitor C1 for bootstrapping and amplifying the voltage of the node Q3 according to the high state of the clock CLK3.

One of the output stages ST3 is connected to the node A which is the gate electrode of the third transistor Tc which is the output transistor of the inverter INV and the output node of the inverter INV which is the source electrode of the third transistor Tc. And a second capacitor C2 connected between the second node QB2 and the second node QB3 for bootstrapping and amplifying the voltage of the node A according to the high-potential voltage VH. The second capacitor C2 suppresses the voltage drop of the node A through the second transistor Tb in a period in which the voltage of the node Q3 transitions from high to low. Therefore, the second capacitor C2 raises the voltage of the node A and the high-potential voltage VH is stably applied to the node QB3, so that the pull-down transistor Tdn can output a stable low voltage. The stabilization of the QB3 node by the second capacitor C2 is more effective when the threshold voltage of the third transistor Tc is increased.

One of the output stages ST3 is connected between the source electrode of the second reset transistor Tr2 and the supply line of the low-potential voltage VSS2 in the second reset section RS2, and the fourth transistor Tr4 And a third capacitor C3 for stably maintaining the high-potential voltage VD supplied to the source electrode of the second reset transistor Tr2.

The carry stage CR is also connected between the Qr node which is the gate electrode of the pull-up transistor Tup and the output node which is the source electrode of the pull-up transistor Tup and is driven in accordance with the high state of the clock CLKc And a fourth capacitor C4 for bootstrapping and amplifying the voltage of the Qr node.

The output stages ST1 to ST3 belonging to one cluster CT and the carry stage CS are set so that the Q nodes Q1 to Q3 and Qr are all set to a high state by the set transistor Ts responding to the same set signal Vs . The pull-up transistor Tup of the first output stage ST1 outputs the first clock CLK1 as the scan signal G1 in the set period of the Q nodes Q1 to Q3 and Qr, The pull-up transistor Tup of the third output stage ST2 outputs the second clock CLK2 as the scan signal G2 and the pull-up transistor Tup of the third output stage ST3 outputs the third clock CLK3, And the pull-up transistor Tup of the carry stage CR outputs the carry clock signal CLKc as the carry signal CR. QB nodes QB1, QB2, QB3 and QBr are reset by the fifth reset transistor Tr5 and the inverter INV when the Q nodes Q1 to Q3 and Qr are in the set state.

The output stages ST1 to ST3 belonging to one cluster CT and the carry stage CS are connected to the Q nodes Q1 to Q3 and Qr by the first reset transistor Tr1 responding to the same reset signal Vrs QB2, QB3, and QBr connected to each other are set to the high state by the inverter INV. The pull-down transistor Tdn of the output stages ST1 to ST3 outputs the low potential voltage VSS1 to the scan signals G1 to G3 in the set period of the QB nodes QB1, QB2, QB3 and QBr , The pull-down transistor Tdn of the carry stage CS outputs the low potential voltage VSS2 as the carry signal CR. When the QB nodes QB1, QB2, QB3 and QBr are in the set state, the Q nodes Q1 to Q3 and Qr maintain the reset state by the second reset section RS2. The reset period of the QB nodes QB1, QB2, QB3, QBr is maintained until the set signal Vs becomes a high state.

The shift register according to the embodiment of the present invention may be composed of an oxide transistor.

Since the shift register according to the embodiment of the present invention has a simple structure as shown in FIG. 12, it can be applied as a built-in driver to a display device requiring a complex waveform such as an OLED display. In other words, the OLED display according to the embodiment of the present invention can drive the gate lines of the display panel into a composite waveform by applying the shift register shown in FIG. 12 as a GIP type gate driver embedded in the display panel, Because of its simple configuration, it is also suitable for narrow bazel implementations.

FIG. 13 shows driving waveforms of the shift register shown in FIG. 12 by way of example, and shows signals necessary for driving gate lines in a flat panel display device including an OLED display device.

When one cluster CT includes three output stages ST1 to ST3 and one carry stage CS as shown in FIG. 12, the clocks are three-phase clocks CLK1 To CLK3 and a carry clock CLKc. The three-phase clocks CLK1 to CLK3 are respectively supplied to the pull-up transistors Tup of the three output stages ST1 to ST3. The carry clock CLKc is supplied to the pull-up transistor Tup of the carry stage CS. .

Each of the three-phase clocks CLK1 to CLK3 includes a period output as a scan signal in the output stages ST1 to ST3 belonging to each cluster CT, that is, a clock output period A, A) is repeated. Each clock output section A has a complex waveform form consisting of a first pulse P1 belonging to the first section A1 and a second pulse P2 belonging to the second section A2. In one output period A of the three-phase clocks CLK1 to CLK3, the first pulses P1 belonging to the first period A1 overlap each other and the second pulses P1 belonging to the second period A2 P2 do not overlap each other, or the adjacent second pulses P2 may partially overlap each other. The pulses of the carry clock CLKc may not overlap or partially overlap with the three-phase clocks CLK1 to CLK3.

Since the scan signals G1 to G9 supplied to the gate lines of the display device are each output from the three-phase clocks CLK1 to CLK3 in the corresponding clock output period A, The first scan pulse SP1 belonging to the first section A1 in the period A and the second scan pulse SP2 belonging to the second period A2. The gate lines are grouped and driven by the respective clusters CT, and the three-phase clocks CLK1 to CLK3 are output to the three gate lines of the group in each clock output period A, respectively. The clock output interval A of each group does not overlap with the clock output interval A of the other group. The first scan pulse SP1 is simultaneously supplied to the three gate lines of the corresponding group in the first period A1 of each clock output period A so that the gate lines of the corresponding group are simultaneously driven. The second scan pulse SP2 is sequentially supplied to the three gate lines of the corresponding group in the second period A2 of each output period A so that the gate lines of the corresponding group are sequentially driven. The second scan pulse SP2 in the second period A2 may not overlap with or overlap with another second scan pulse SP2 of the corresponding group as shown in FIG. Lt; RTI ID = 0.0 &gt; 3 &lt; / RTI &gt;

For example, the Q nodes (Q1, Q2, Q3, and Qr) of the cluster CT shown in FIG. 12 are set to the first clock output period A shown in FIG. 13, The pull-up transistor Tup of the second output stage ST2 outputs the first clock CLK1 as the first scan signal G1 and the pull-up transistor Tup of the second output stage ST2 outputs the second clock CLK2, The pull-up transistor Tup of the third output stage ST3 outputs the third clock CLK3 as the third scan signal G3, and the carry stage CS Pull-up transistor Tup outputs a carry clock CLKc to a first carry signal (not shown).

 Each of the plurality of pixels constituting the OLED display device includes an OLED element composed of an organic light emitting layer between the anode and the cathode and a pixel driving circuit independently driving the OLED element. The pixel driving circuit basically includes a switching transistor for charging a capacitor with a data signal in response to a scan pulse and a driving transistor for driving the OLED element by supplying a driving current proportional to a voltage charged in the capacitor. In addition, the pixel driving circuit may include a reset transistor for resetting at least one of a gate and a source of the driving transistor, a light emission control transistor for controlling the light emission period of the OLED element for improving contrast, And a sensing transistor for sensing and compensating the voltage.

Accordingly, in order to drive a pixel driving circuit including a plurality of transistors, the OLED display device includes a composite waveform (e.g., a scan pulse) having scan pulses SP1 and SP2 having different periods in each gate line, May be required.

14, a pulse belonging to the first section A1 and a pulse belonging to the second section A2 are connected and supplied in each clock output section A of the three-phase clocks CLK1 to CLK3, The scan signals G1 to G9 supplied to the gate lines in the clock output period A are also connected to the scan pulses belonging to the first period A1 and the scan pulses belonging to the second period A2, . As a result, the scan signals G1 to G3 supplied to the gate lines of the corresponding group in the respective clock output periods A may sequentially have an increased pulse width.

FIGS. 15 and 16 are diagrams showing the results of simulation of the driving waveform shown in FIG. 14 using the shift register shown in FIG.

15 and 16, the three-phase clocks CLK1 to CLK3, the two-phase carry clocks CLKc1 and CLKc2, and the reset signal Vrs having sequentially increased pulse widths as shown in FIG. 15 (a) The shift registers including three clusters CT shown in Fig. 12 are driven to sequentially output three-phase clocks CLK1 to CLK3 in the first cluster as shown in Figs. 15 (b) and 16 The first to third scan signals G1 to G3 and the first carry signal CR1 using the first carry clock CLKc1 are output and the three clocks CLK1 to CLK3 are used in the second cluster, The second carry signal CR2 is output using the fourth to sixth scan signals G4 to G6 and the second carry clock signal CLKc2 and the second carry signal CR2 is output using the third carry clock signal CLK1, 7 to the ninth scan signals G7 to G9 and the third carry signal CR3 using the first carry clock CLKc1 are output.

As described above, the shift register according to the present invention has a simple structure based on a basic shift register while outputting composite waveforms having different periods, so that not only reliability can be improved, but also a composite waveform such as an OLED display device It is suitable to be implemented as a built-in driver in a display device.

The display device using the shift register according to the present invention can drive the gate lines of the display panel into a composite waveform by applying the shift register to the GIP type gate driver incorporated in the display panel and the circuit configuration is simple, Suitable.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

CT1 and CT2: clusters ST1 to ST3: output stage
CS1, CS2, CS: Carry stages CR1 to CR3, CR: Carry signal
G1 to Gm: scan signals VSS0 to VSS3, VL: low potential voltage
VD, VH: High potential voltage INV: Inverter
CLKs, CLK1 to CLK3, CLKc, CLKc1, CLKc2: Clock
Vs, Vs1 to Vs3: set signal Vrs, Vrs1 to Vrs3: reset signal

Claims (8)

In a shift register including a plurality of clusters,
Each of the plurality of clusters including a plurality of output stages each outputting a plurality of output signals, and a carry stage outputting a carry signal,
Each of the plurality of output stages and the carry stages
An output for generating a clock or a first undervoltage to an output in accordance with a logic state of the first node and the second node,
The first node is set to the set state in accordance with the carry signal output from the previous stage cluster or the set signal supplied from the outside, the carry signal output from the next stage cluster, or the externally supplied reset signal, A first node control unit for controlling the first node,
Wherein at least one of the plurality of output stages
And a second node control unit controlling the second node of the first node in a manner opposite to the first node of the one of the plurality of output stages,
And the second nodes belonging to at least two of the stages belonging to each cluster are connected to each other. Claim 1
The first node control unit
A set transistor for supplying a first high voltage to the first node under the control of the set signal and a first reset transistor for supplying a second low voltage to the first node under the control of the reset signal,
And a reset section for supplying a third low voltage to the first node under the control of the second node together with the set transistor and the first reset transistor,
The reset unit
And a second reset transistor for supplying the third low voltage to the first node under the control of the second node,
A third reset transistor connected in series with the second reset transistor to supply the third low voltage to the second reset transistor under the control of the second node together with the second reset transistor, And a fourth reset transistor for supplying said high voltage to a connection point between said second and third reset transistors in accordance with said second reset transistor. The method of claim 2,
The second node controller
And an inverter to supply a second high voltage or a fourth undervoltage to the second node under the control of the first node such that the second node is in a logic state opposite to the first node of either one of the plurality of output stages do or,
And a reset transistor which, together with the inverter, supplies the fourth low voltage to the second node under the control of the set signal. The method of claim 3,
Wherein the output nodes belonging to each cluster and the first node of the carry stage are separated from each other, while the second nodes are connected to each other,
Wherein the second node controller is provided in one of the output stages and the carry stage belonging to each cluster,
The output stages belonging to each cluster and the set signals supplied to the carry stage are the same or different from each other,
Wherein the output stages belonging to each cluster and the reset signal supplied to the carry stage are the same or different from each other. The method of claim 3,
Wherein the first and second high voltages are equal to or different from each other,
The first to fourth low voltages may be the same or different from each other,
Wherein the first low voltage supplied to the output part of the output stage belonging to each cluster and the first low voltage supplied to the output part of the carry stage belonging to the cluster are the same or different from each other. The method according to claim 1,
When each of the clusters includes m (m is a natural number) output stages,
Wherein the clock comprises at least an m phase clock,
The m-phase clocks are respectively supplied to the m output stages,
Wherein the carry stage is supplied with a clock equal to either one of the m-phase clocks, or a carry clock having a phase different from that of the m-phase,
Wherein each of the m-phase clocks includes a plurality of pulses in a clock output period, the clock output interval including a first period and a second period is repeated, and the m-phase clocks in the respective clock output periods have different pulse widths And a shift register. The method of claim 6,
Wherein the m-phase clock includes a first pulse that overlaps with each other in the first period, and a second pulse that does not overlap with each other in the second period or partially overlaps with an adjacent clock,
Wherein each of the plurality of output stages belonging to each cluster outputs different clocks including the first and second pulses in a clock output period corresponding to the cluster,
Wherein the carry stage belonging to each cluster outputs a carry clock that does not overlap with the first and second pulses in the clock output period. The method according to any one of claims 1 to 7,
And the gate line of the display panel is driven by using the shift register.

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