KR20160006870A - Display device and method of manufacturing the same - Google Patents

Abstract

The display device according to the present invention is arranged in a display region of a base substrate and is arranged in a non-display region of a pixel including a pixel transistor including the first active layer and a base substrate to apply an electrical signal to the pixel, And the first active layer and the second active layer are made of the same material, and the second active layer has a higher charge mobility than the first active layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device and a method of manufacturing the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a method of manufacturing the same, and more particularly to a display device having excellent operation characteristics and a method of manufacturing the same.

The display device includes a plurality of thin film transistors. Some of the thin film transistors may be used as a pixel transistor arranged in a display region of a display device to drive a pixel. Or some of the thin film transistors may be used as a driving transistor constituting a driving circuit portion disposed in a non-display region of the display device. The pixel and the driving circuit portion have different functions, and the electrical characteristics required for the pixel transistor and the driving transistor may be different from each other.

Each of the thin film transistors includes an active layer in which a channel which is a movement path of charges is formed. The active layer may be composed of various kinds of semiconductor materials. The electric field effect of the thin film transistor varies depending on the electrical properties of the active layer.

Accordingly, it is an object of the present invention to provide a display device including a driving transistor and a pixel transistor which are made of the same material but have different mobility.

It is still another object of the present invention to provide a display device manufacturing method for simultaneously forming a driving transistor and a pixel transistor having different mobility.

A display device according to an embodiment of the present invention includes a pixel disposed in a display region of a base substrate, the pixel including a pixel transistor including a first active layer, and a non-display region disposed in the non-display region of the base substrate, Wherein the first active layer and the second active layer are made of the same material and the second active layer has a higher charge mobility than the first active layer, I have.

The plurality of pixels are provided, and the driving circuit portion sequentially applies a gate signal to each of the pixels, and includes a gate driving circuit including a plurality of transistors, and the transistors may include the driving transistor.

Wherein the pixel transistor includes a first electrode layer disposed below the first active layer and a second electrode layer disposed over the first active layer with an insulating film interposed therebetween and the driving transistor is disposed on the same layer as the first electrode layer A third electrode layer, and a fourth electrode layer disposed on the same layer as the second electrode layer, and the first active layer and the second active layer may be disposed on the same layer.

The display device according to an embodiment of the present invention may further include a display electrode connected to the pixel transistor, and the display electrode may be disposed on the second electrode layer.

The charge mobility of the driving transistor may be about 130% or more of the charge mobility of the pixel transistor.

The first active layer and the second active layer may be formed of an amorphous oxide semiconductor material.

The oxide semiconductor material may include indium tin zinc oxide.

A method of manufacturing a display device according to an embodiment of the present invention includes a pixel disposed in a display region of a base substrate and a driver circuit portion disposed in a non-display region adjacent to the display region, wherein the pixel includes a pixel transistor, The driving circuit portion including a driving transistor, the method comprising the steps of: forming a first oxide semiconductor pattern and a second oxide semiconductor pattern made of the same oxide semiconductor material in the display region and the non-display region, Patterning the first oxide semiconductor pattern and the second oxide semiconductor pattern; and selectively etching the first oxide semiconductor pattern and the second oxide semiconductor pattern to form a first active layer of the pixel transistor and a second active layer of the driving transistor, The second oxide semiconductor pattern subjected to the plasma treatment is subjected to heat treatment .

Forming the first oxide semiconductor pattern and the second oxide semiconductor pattern may include forming a semiconductor layer including the oxide semiconductor material on the display region and the non-display region of the base substrate, Forming a first photoresist pattern corresponding to the first oxide semiconductor pattern and a second photoresist pattern corresponding to the second oxide semiconductor pattern and having a thickness lower than that of the first photoresist pattern, Etching the photoresist film using a halftone mask so as to form a semiconductor layer, and etching the exposed region of the semiconductor layer with the etched photoresist film, wherein in the step of etching the semiconductor layer, 2 photoresist pattern is removed, and two A reduced third photoresist pattern can be formed.

Wherein the step of selectively plasma-treating the first oxide semiconductor pattern includes the steps of: forming the first oxide semiconductor pattern covered with the third photoresist pattern and the second oxide semiconductor pattern exposed from the second photoresist pattern, And removing the third photoresist pattern.

The plasma may be generated from nitrogen or nitrogen oxide gas.

The step of forming the first semiconductor pattern and the second semiconductor pattern and the step of selectively plasma-treating the first semiconductor pattern may proceed in the same chamber.

The step of heat-treating the first oxide semiconductor pattern and the plasma-treated second oxide semiconductor pattern may be performed at a temperature lower than a crystallization temperature of the oxide semiconductor material.

A method of manufacturing a display device according to an embodiment of the present invention includes the steps of forming a first electrode layer on the base substrate before forming the first oxide semiconductor pattern and the second oxide semiconductor pattern, And forming a second electrode layer on the first active layer and the second active layer after the step of annealing the first oxide semiconductor pattern and the plasma-treated second oxide semiconductor pattern, wherein the first electrode layer is formed on the same layer And a second electrode pattern overlapping with the second active layer, wherein the second electrode layer is disposed on the same layer, and the third electrode pattern overlapped with the first active layer and the third electrode pattern overlapping the first active layer, An electrode pattern, and a fourth electrode pattern overlapping the second active layer.

The method of manufacturing a display device according to an embodiment of the present invention may further include forming a display electrode connected to the pixel transistor in the display region, and the display electrode may be formed on the second electrode pattern.

A method of manufacturing a display device according to an embodiment of the present invention includes forming gate signal lines connected to the pixel transistor in the display region and forming data signal lines connected to the gate signal lines, The gate signal lines may be formed simultaneously with the first electrode layer.

The driving transistor of the display device further includes a plasma processing step in the manufacturing process so that the active layer constituting the driving transistor has a lower defect density than the active layer constituting the pixel transistor and is energetically more stabilized. Accordingly, the driving characteristics of the driving transistor can be improved without changing the constituent materials.

The driving transistor may have the same carrier concentration as the pixel transistor and have an improved mobility. In addition, the on-off characteristic of the driving transistor is higher than that of the pixel transistor.

Further, the driving transistor and the pixel transistor of the display device may be formed of the same material and formed simultaneously in the same chamber. As a result, the manufacturing cost can be reduced.

1 is a plan view schematically showing a display device according to an embodiment of the present invention.
2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
3 is a cross-sectional view of a pixel according to an embodiment of the present invention.
4 is a block diagram of a gate driving circuit according to an embodiment of the present invention.
5 is a circuit diagram of a driving stage of any one of the driving stages shown in Fig.
6 is an input / output signal waveform diagram of the driving stage shown in FIG.
7 is a cross-sectional view illustrating a driving transistor according to an embodiment of the present invention.
8A to 8L are cross-sectional views illustrating a method of manufacturing a display device according to an embodiment of the present invention.
9A is a graph showing current-voltage characteristics of a pixel transistor according to an embodiment of the present invention.
9B is a graph showing current-voltage characteristics of a driving transistor according to an embodiment of the present invention.
9C is a graph comparing electrical characteristics of a pixel transistor and a driving transistor according to an embodiment of the present invention.

Hereinafter, a detailed description will be given with reference to the drawings.

1 is a plan view schematically showing a display device according to an embodiment of the present invention. 2 is an equivalent circuit diagram of a pixel PX _ij according to an embodiment of the present invention. 1, a display device according to an embodiment of the present invention includes a display panel 100, a gate driving circuit 200, and a data driving circuit 300. [

The display panel 100 is not particularly limited and may be, for example, a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, An electrowetting display panel, and the like. In the present embodiment, the display panel 100 is described as the liquid crystal display panel. Meanwhile, the liquid crystal display device including the liquid crystal display panel may further include a polarizer, a backlight unit, and the like not shown.

The display panel 100 includes a first substrate DS1, a second substrate DS2 and a liquid crystal layer (not shown) disposed between the first substrate DS1 and the second substrate DS2 . On the plane, the display panel 100 includes a display area DA for displaying an image and a non-display area NDA adjacent to the display area DA. The second substrate DS2 may expose the non-display area NDA of the first substrate DS1.

The display panel 100 includes a plurality of pixels PX ₁₁ to PX _nm disposed in the display area DA, a plurality of gate lines GL 1 to GLn, and a plurality of gate lines GL 1 to GLn, And a plurality of data lines DL1 to DLm. The gate lines (GL1 ~ GLn) and the gate lines (GL1 ~ GLn) are respectively connected to a corresponding pixel of the pixels (PX PX ~ _{11 nm).} Only a portion is shown in Figure 1, the part, and the pixels (PX PX ~ _{11 nm)} of the part, the data lines (DL1 ~ DLm) of said gate lines (GL1 ~ GLn).

The gate driving circuit 200 is connected to the gate lines GL1 to GLn. The gate driving circuit 200 may sequentially output gate signals to the gate lines GL1 to GLn. The gate driving circuit 200 is formed directly on the non-display area NDA of the first substrate DS1 through a thin film process for forming the pixels PX ₁₁ to PX _nm .

FIG. 1 illustrates an example of one gate driving circuit 200 connected to the left ends of the gate lines GL1 to GLn. In one embodiment of the present invention, the display device may include two gate drive circuits.

One of the two gate driving circuits may be connected to the left ends of the gate lines GL1 to GLn and the other may be connected to the right ends of the gate lines GL1 to GLn. In addition, one of the two gate driving circuits may be connected to the odd gate lines and the other to the even gate lines.

As such, when the gate driving circuit 200 is integrated on the first substrate DS1, the driving chips for embedding the gate driving circuit 200 can be removed. Accordingly, the productivity of the display device according to the present invention can be improved, and the overall size of the display device can be reduced.

The data driving circuit 300 is connected to the data lines DL1 to DLm. The data driving circuit 300 may include a plurality of data driving chips 310 and a flexible circuit board 320 on which the data driving chips 310 are mounted. The data driving chips 310 are electrically connected to corresponding data lines of the data lines DL1 to DLm to output the data signals to the data lines DL1 to DLm.

FIG. 1 exemplarily shows a data carrier circuit 300 of a tape carrier package (TCP) type. Although not shown, in an embodiment of the present invention, the data driving circuit 300 may be arranged in the non-display area NDA of the first substrate DS1 in a chip on glass (COG) manner have.

The display device may further include a main circuit board (MCB) for controlling driving of the gate driving circuit 200 and the data driving circuit 300. The main circuit board MCB outputs a gate side control signal for controlling the driving of the gate driving circuit 200, a data side control signal for controlling the driving of the data driving circuit 300, and image data.

The gate driving circuit 200 receives the gate side control signal and sequentially outputs the gate signal to the gate lines GL1 to GLn in response to the gate side control signal. The gate side control signal may be received via a signal line not shown. The signal line may connect the main circuit board MCB and the gate drive circuit 200 through the tape gap package.

In addition, the data driving circuit 300 converts the image data into the data signal in response to the data-side control signal and outputs the data signal.

In FIG. 2, one pixel PX _ij among the pixels PX ₁₁ to PX _nm is exemplarily shown. As shown in FIG. 2, the pixel PX _ij includes a pixel thin film transistor TR-P (pixel transistor), a liquid crystal capacitor Clc, and a storage capacitor Cst. Hereinafter, the transistor means a thin film transistor.

The pixel transistor TR-P is electrically connected to the i-th gate line GLi and the j-th data line DLj. The pixel transistor TR-P outputs a data voltage corresponding to the data signal received from the j-th data line DLj in response to the gate signal received from the i-th gate line GLi.

The liquid crystal capacitor Clc charges the data voltage output from the pixel transistor TR-P. The transmittance of the liquid crystal layer (not shown) is controlled according to the amount of charges charged in the liquid crystal capacitor Clc, and as a result, a desired image is displayed in the display area DA.

The storage capacitor Cst is connected to the liquid crystal capacitor Clc in parallel. The storage capacitor Cst maintains the transmittance of the liquid crystal layer for a predetermined time.

3 is a cross-sectional view of a pixel PX _ij according to an embodiment of the present invention. The pixel transistor TR-P includes a control electrode GE-P connected to the i-th gate line GLi (see FIG. 2), a first active layer AL-P overlapping the control electrode GE- An input electrode SE-P connected to the jth data line DLj, and an output electrode DE-P spaced apart from the input electrode SE-P.

The liquid crystal capacitor Clc includes a pixel electrode PE and a common electrode CE. The storage capacitor Cst includes a portion of the storage line STL overlapping the pixel electrode PE and the pixel electrode PE.

The first substrate DS1 includes a first base substrate BS1, the pixel transistor TR-P, the pixel electrode PE, and the storage line STL. The i-th gate line GLi and the storage line STL are disposed on the first base substrate BS1. The control electrode GE is branched from the i-th gate line GLi.

The control electrode GE, the i-th gate line GLi and the storage line STL may be formed of a metal such as Al, Ag, Cu, Mo, Cr, (Ta), and titanium (Ti), alloys thereof, and the like. The control electrode GE, the i-th gate line GLi, and the storage line STL may include a multilayer structure, for example, a titanium layer and a copper layer.

A first insulating layer 10 covering the control electrode GE, the i-th gate line GLi, and the storage line STL is disposed on the first base substrate BS1. The first insulating layer 10 may be an organic film or an inorganic film. For example, the first insulating layer 10 may include a silicon nitride layer or a silicon oxide layer. In addition, the insulating layer 10 may have a multi-layer structure in which an organic layer and / or an inorganic layer are stacked.

A first active layer (AL-P) is disposed on the first insulating layer (10). The first active layer AL-P overlaps the control electrode GE. The first active layer AL-P may be formed of an amorphous oxide semiconductor material.

The first active layer AL-P may include a channel not shown. The channel is a path for transferring charges in the first active layer AL-P. This will be described later.

The input electrode SE-P and the output electrode DE-P are disposed on the first active layer AL-P. The input electrode SE-P and the output electrode DE-P are disposed apart from each other by exposing a part of the first active layer AL-P. The input electrode SE-P and the output electrode DE-P partially overlap the control electrode GE.

At this time, the first active layer AL-P may further include an unshown ohmic contact layer. The ohmic contact layer may be formed in the first active layer AL-P in a region in contact with the input electrode SE-P and in an area in contact with the output electrode DE-P. The ohmic contact layer reduces the resistance between the first active layer AL-P and the input electrode SE-P and the output electrode DE-P.

A second insulating layer 20 may be disposed on the first insulating layer 10. The second insulating layer 20 covers the pixel transistor TR-P. The second insulating layer 20 may overlap the storage line STL.

The second insulating layer 20 may include at least one of an inorganic material and an organic material. For example, the second insulating layer 20 may include a silicon nitride layer or a silicon oxide layer. The second insulating layer 20 may have a multi-layer structure in which an organic layer and / or an inorganic layer are stacked.

A third insulating layer (30) is disposed on the second insulating layer (20). The third insulating layer 30 provides a flat surface on the upper side. The third insulating layer 30 may include an organic material.

The pixel electrode PE is disposed on the third insulating layer 30. The pixel electrode PE may be connected to the output electrode DE-P through a contact hole TH through the second insulating layer 20 and the third insulating layer 30. Although not shown, an alignment layer that covers the pixel electrode PE may be further disposed on the third insulating layer 30.

The second substrate DS2 is disposed opposite to the first substrate DS1. The second substrate DS2 includes a second base substrate BS2, a color filter layer CF, and a common electrode CE.

The color filter layer CF is disposed on one surface of the second base substrate BS2. The common electrode CE is disposed on the color filter layer CF. A common voltage is applied to the common electrode CE.

The common voltage and the pixel voltage have different potential values. An alignment layer (not shown) covering the common electrode CE may be further disposed on the common electrode CE. Further, an insulating film may be further disposed between the color filter layer CF and the common electrode CE.

The liquid crystal layer LCL is disposed between the first substrate DS1 and the second substrate DS2. The liquid crystal capacitor Clc (see FIG. 2) is formed by the pixel electrode PE and the common electrode CE disposed with the liquid crystal layer LCL therebetween.

The liquid crystal layer (LCL) includes liquid crystal molecules. The liquid crystal molecules are aligned according to an electric field formed by a potential difference between the pixel electrode PE and the common electrode CE. The transmittance of the liquid crystal layer (LCL) is determined according to the alignment of the liquid crystal molecules.

On the other hand, the cross section of the pixel PX _ij shown in Fig. 3 is only one example. 3, at least one of the color filter layer CF and the common electrode CE may be disposed on the first substrate DS1. In other words, the liquid crystal display panel according to the present embodiment can be used in a VA (Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, IPS (in-plane switching) mode or Fringe- And a switching mode.

4 is a block diagram of a gate drive circuit 200 according to an embodiment of the present invention. As shown in FIG. 4, the gate driving circuit 200 includes a plurality of driving stages SRC1 to SRCn. The driving stages SRC1 to SRCn are connected to each other. At this time, the gate driving circuit 200 may further include a dummy stage SRC-D connected to the n-th driving stage SRCn.

The driving stages SRC1 to SRCn are connected to the gate lines GL1 to GLn, respectively. Accordingly, the driving stages SRC1 to SRCn provide gate signals to the gate lines GL1 to GLn, respectively.

Each of the driving stages SRC1 to SRCn includes an output terminal OUT, an input terminal IN, a carry terminal CR, a first control terminal CT1, a second control terminal CT2, a clock terminal CK, An inverter voltage output terminal INV, a first voltage input terminal C1, and a second voltage input terminal C2.

The output terminal OUT is connected to a corresponding one of the gate lines GL1 to GLn. Gate signals generated from the driving stages SRC1 to SRCn are provided to the gate lines GL1 to GLn through the output terminal OUT.

The carry terminal CR is electrically connected to the input terminal IN of the driving stage next to the driving stage. The input terminal IN receives a carry signal of the driving stage before the corresponding driving stage.

For example, the input terminal IN of the third driving stage SRC3 receives the carry signal of the second driving stage SRC2. The input terminal IN of the first driving stage SRC1 of the driving stages SRC1 to SRCn is connected to the input terminal IN of the first driving stage SRC1 in response to the start signal STV ).

The clock terminal CK receives either the first clock signal CLK or the second clock signal CLKB. The first clock signal CLK and the second clock signal CLKB are clock signals whose phases are opposite to each other.

The first clock signal CLK and the second clock signal CLKB are alternately input to adjacent ones of the driving stages SRC1 through SRCn. For example, the clock terminal CK of each of the odd-numbered driving stages SRC1 and SR3 among the driving stages SRC1 to SRCn may receive the first clock signal CLK. At this time, the clock terminal CK of each of the even-numbered driving stages SRC2 among the driving stages SRC1 to SRCn may receive the second clock signal CLKB.

The first control terminal CT1 is connected to the inverter signal output terminal IV of the driving stage before the corresponding driving stage to receive the inverter signal INV of the previous driving stage. At this time, the first control terminal CT1 of the first driving stage SRC1 may receive a signal generated separately or receive a signal generated in the dummy stage SCR-D so that the timing is suitable have. The second control terminal CT2 receives the carry signal CRi + 1 of the driving stage next to the driving stage.

The first voltage input terminal V1 receives the first voltage VSS1 and the second voltage input terminal V2 receives the second voltage VSS2 having a potential lower than the first voltage VSS1 . In an embodiment of the present invention, the first voltage VSS1 may be a gate-off voltage.

As shown in FIG. 4, the gate driving circuit 200 may further include a plurality of discharge transistors ND1 to NDn. Each of the discharge transistors ND1 to NDn includes a control electrode connected to a next gate line of a corresponding one of the gate lines GL1 to GLn, an input electrode for receiving the first voltage VSS1, And an output electrode connected to the gate line. Each of the discharge transistors ND1 to NDn may discharge the corresponding gate line to the first voltage VSS1 in response to a gate signal applied to the next gate line of the corresponding gate line.

In one embodiment of the present invention, each of the driving stages SRC1 to SRCn is connected to the output terminal OUT, the input terminal IN, the carry terminal CR, One of the first and second control terminals CT1 and CT2, the clock terminal CK and the first and second voltage input terminals V1 and V2 may be omitted or other terminals may be further included. Also, the connection relationship of the driving stages SRC1 to SRCn may be changed.

5 is a circuit diagram of one of the driving stages SRC1 to SRCn shown in FIG. 4, and FIG. 6 is an input / output signal waveform diagram of the driving stage shown in FIG. Fig. 5 exemplarily shows a third driving stage SRC3 of the driving stages SRC1 to SRCn shown in Fig. Each of the driving stages SRC1 to SRCn shown in FIG. 4 may have the same circuit as the third driving stage SRC3.

The third driving stage SRC3 includes a first output unit 211, an inverter unit 212, a control unit 213, a second output unit 214, a stabilization unit 215, and a pull down unit 216 do. On the other hand, the circuit of the third driving stage SRC3 is merely an example, and this can be changed.

The first output unit 211 includes a control electrode connected to the control node N10, an input electrode connected to the clock terminal CK to receive the clock signal CK, and an output electrode connected to the output terminal OUT. And a first output transistor T4. The first output unit 211 outputs a gate signal GS3 to the gate line GL3 (see FIG. 4).

The control node N10 may be a node connected to the control terminal of the output transistor of the gate driver 200. [ In this embodiment, the control node N10 may be defined as a node connected to a control terminal of the first output unit 211 and a control terminal of the second output unit 212, which will be described later.

The period during which the first output transistor T4 is turned on, that is, during which the control node N10 is at the first high voltage VQ1 or the second high voltage VQ2, ) ≪ / RTI > The period after the on period Ton of the first output unit 211 is defined as the off period Toff of the first output unit 211.

The second output unit 212 includes a second output transistor N2 having a control electrode coupled to the control node N10, an input electrode coupled to the clock terminal CK, and an output electrode coupled to the carry terminal CR, T15). The second output unit 212 outputs a carry signal CRS3 to a fourth driving stage (not shown).

The clock terminal CK of each of the driving stages SRC1 to SRCn receives the first clock signal CLK or the second clock signal CLKB. For example, the odd-numbered driving stages SRC1 and SRC3 of the driving stages SRC1 to SRCn receive the first clock signal CLK and the odd-numbered driving stages SRC1 to SRCn of the driving stages SRC1 to SRCn, The stages SRC2 receive the second clock signal CLKB. The first clock signal CLK and the second clock signal CLKB may have a phase difference of 180 °.

Each of the first clock signal CLK and the second clock signal CLKB includes low intervals having a low level and high intervals having a relatively high level. Although not shown, the second clock signal CLKB includes low and high periods alternating with the first clock signal CLK.

The third driving stage SRC3 receives the first clock signal CLK. The first clock signal CLK has a first level VL1 during a low interval. The first level VL1 may be at the same level as the first voltage VSS1. The first clock signal CLK has a second level VL2 higher than the first level VL1 during a high period.

The control unit 213 controls the operation of the first output unit 211 and the second output unit 212. The control unit 213 responds to the carry signal CRS2 output from the second driving stage SRC2 during the ON period Ton of the first output unit 211 so that the potential of the control node N10 1 < / RTI > voltage VQ1. Accordingly, the first output unit 211 and the second output unit 212 are turned on.

The potential of the control node N10 of the control unit 213 is boosted up as the potential of the output terminal OUT and the carry terminal CR rises. By this bootstrapping operation, the control node N10 is boosted from the first high voltage VQ1 to the second high voltage VQ2. When the control node N10 is boosted to the second high voltage VQ2, the gate signal GS3 is output.

The gate signal GS3 has a first level VL10 during a row interval and a second level VL20 higher than the first level VL10 during a high interval. The first level (VL10) may have the same voltage as the first voltage (VSS1).

The first output unit 211 and the second output unit 212 may be maintained in a turned-on state during the ON period (Ton) of the first output unit 211. Also, the gate signal GS3 and the carry signal CRS3 may be generated in a high state during the high period of the first clock signal CLK.

The control unit 213 may decrease the potential of the first terminal N10 to the second voltage VSS2 during the off period Toff of the first output unit 211 and turn on the first output unit 211, And the second output unit 212 are turned off. For example, the control unit 213 turns off the first output unit 211 and the second output unit 212 in response to the carry signal CRS4 output from the fourth driving stage. The control unit 213 turns off the first output unit 211 and the second output unit 212 in response to the first clock signal CLK.

The holding unit 214 holds the potential of the output terminal OUT at the first voltage VSS1 during the off period Toff of the first output unit 211. [ For example, the holding unit 214 may receive the carry signal CRS4 or the first clock signal CLK output from the fourth driving stage during the off period Toff of the first output unit 211, And holds the potential of the output terminal OUT at the first voltage VSS1. The holding unit 214 may be connected to the output terminal OUT in response to the inverter signal IVS2 output from the second driving stage SRC2 during the off period Toff of the first output unit 211, And holds the potential at the first voltage VSS1.

The inverter unit 215 controls the operation of the holding unit 214. The inverter unit 215 includes the first to fourth inverter transistors T12, T7, T13, and T8.

The first inverter transistor T12 includes a first electrode and a second electrode commonly connected to the clock terminal CK and a third electrode connected to the first electrode of the second inverter transistor T7. The second inverter transistor T7 includes the first electrode, a second electrode connected to the clock terminal CK, and a third electrode connected to the inverter voltage output terminal IV.

The third inverter transistor T13 includes a first electrode for receiving the carry signal CR3, a first electrode connected to the third electrode of the first inverter transistor T12, and a second electrode connected to the second voltage output terminal V2. And a third electrode connected to the second electrode. The fourth inverter transistor T8 includes a first electrode connected to the first electrode of the third inverter transistor T13, a second electrode connected to the second voltage output terminal V2, and a second electrode connected to the second inverter transistor T7 And a third electrode connected to the third electrode of the second electrode. Hereinafter, the operation of the inverter unit 215 will be described.

The inverter unit 215 outputs an inverter signal IVS3 corresponding to the first clock signal CLK during the off period Toff of the first output unit 211 and outputs the inverter signal IVS3 corresponding to the first clock signal CLK, And supplies the second voltage VSS2 to the holding unit 214 in response to the carry signal CRS3 of the driving stage SRC3 during the turn-on period Ton of the driving stage SRC3. And the holding part 214 is turned off in response to the second voltage VSS2.

The first inverter transistor T12 may be turned on in response to the first clock signal CLK. The third and fourth inverter transistors T13 and T8 are turned on by the carry signal CR3, respectively. As the third inverter transistor T13 is turned on, the voltage output from the first inverter transistor T12 is reduced to the second voltage VSS2.

Also, the third inverter transistor T13 may be turned on to block the first clock signal CLK from being applied to the second inverter transistor T7. Accordingly, the second inverter transistor T7 is turned off by the second voltage VSS2, and the first clock signal CLK is not transferred to the second terminal N20.

The fourth inverter transistor T8 is turned on by the carry signal CRS3. The second voltage VSS2 is transferred to the second terminal N20 by the fourth inverter transistor T8. The second voltage VSS2 is transferred to the holding part 214 to turn off the holding part 214. [

In addition, the inverter voltage output terminal IV outputs an inverter signal IVS3 corresponding to the second voltage VSS2. Therefore, the inverter signal IVS3 may be a signal whose phase is inverted from the first clock signal CLK. The inverter signal IVS3 includes low and high periods alternating with the first clock signal CLK.

The pull down portion 216 lowers the potential of the carry terminal CR so that the carry signal CRS3 has one high period. The pulldown portion 216 includes first and second pull-down transistors T11 and T17.

The first pull-down transistor T11 includes a first electrode connected to the holding part 214, a second electrode connected to the second voltage terminal V2, and a third electrode connected to the carry terminal CR . The second pull-down transistor T17 includes a first electrode connected to the second control terminal CT2, a second electrode connected to the second voltage terminal V2, and a third electrode connected to the carry terminal CR .

Down section 216 responds to the carry signal CRS4 output from the fourth driving stage SRC4 via the second pull down transistor T17 to the potential of the carry terminal CR to the second voltage VSS2 ). The pull-down unit 216 may be connected to the carry terminal CR in response to the first clock signal CLK through the first pull-down transistor T11 during the off period Toff of the first output unit 211, ) Voltage to the second voltage VSS2.

7 is a cross-sectional view illustrating a driving transistor according to an embodiment of the present invention. The driving stage shown in Fig. 6 may include the driving transistor TR-D. Hereinafter, the driving transistor TR-D will be described in more detail. On the other hand, for ease of explanation of the layer structure, the description will be made with reference to the pixel transistor TR-P shown in FIG.

The third driving stage SRC3 includes a first electrode layer, a second electrode layer, and an active layer disposed on different layers. The first electrode layer and the second electrode layer may include a plurality of electrodes and wirings patterned. The active layer includes a plurality of patterned portions. The active layer includes a plurality of patterned portions.

The driving transistor TR-D is disposed in the non-display area NDA of the first base substrate BS1. The driving transistor TR-D includes a control electrode GE-D, a second active layer AL-D, an input electrode DE-D, and an output electrode SE-D. A part of the first electrode layer constitutes the control electrode GE-D and a part of the second electrode layer constitutes the input electrode DE-D and the output electrode SE-D. Some of the portions of the active layer constitute the second active layer AL-D.

A first insulating layer 10 is disposed between the control electrode GE-D and the second active layer AL-D, and the first insulating layer 10 is disposed on the input electrode DE-D and the output electrode SE- A second insulating layer 20 covering the driving transistor TR-D is disposed. The first insulating layer 10 and the second insulating layer 20 are the same layer as the first insulating layer 10 and the second insulating layer 20 of the pixel transistor TR-P.

Therefore, the control electrode GE-D is disposed on the same layer as the control electrode GE-P of the pixel transistor TR-P. The control electrode GE-D of the driving transistor TR-D may be formed of the same material as the control electrode GE-P of the pixel transistor TR-P and may have the same layer structure. Although not shown in the figure, the control electrode GE-D of the driving transistor TR-D and the control electrode GE-P of the pixel transistor TR- A third insulating layer (not shown) may be further disposed between the first base substrate BS1.

The input electrode DE-D and the output electrode SE-D of the driving transistor TR-D are connected to the input electrode DE-P and the output electrode SE-P of the pixel transistor TR- ) On the same layer. The input electrode DE-D and the output electrode SE-D of the driving transistor TR-D are connected to the input electrode DE-P and the output electrode SE-P of the pixel transistor TR- They may be made of the same material and have the same layer structure.

The second active layer AL-D may be disposed on the first insulating layer 10. The second active layer AL-D is disposed on the same layer as the first active layer AL-P.

The second active layer AL-D includes a metal oxide semiconductor material. The second active layer AL-D has an amorphous crystal structure. For example, the second active layer AL-D may include amorphous indium tin zinc oxide. The second active layer AL-D may be formed of the same material as the first active layer AL-P.

When an electric field is formed in the driving transistor TR-D, a channel is formed in the second active layer AL-D. The second active layer AL-D has a second mobility. Charges in the second active layer AL-D move along the channel at a speed corresponding to the second mobility.

In this embodiment, the second mobility is greater than the first mobility. In other words, the charge mobility of the second active layer AL-D is greater than the charge mobility of the first active layer AL-P. The second active layer AL-D is made of the same material as the first active layer AL-P and has the same crystal structure but has a higher charge mobility than the first active layer AL-P have. A detailed description thereof will be described later.

8A to 8L are cross-sectional views illustrating a method of manufacturing a display device according to an embodiment of the present invention. Hereinafter, a method of manufacturing the display device including the driving transistor and the pixel transistor will be described in detail with reference to FIGS. 8A to 8L. FIG. In the meantime, the same reference numerals are assigned to the same components as those described in Figs. 1 to 7, and a detailed description thereof will be omitted.

As shown in FIG. 8A, a first electrode layer is formed on the first base substrate BS1. In this embodiment, the first electrode layer includes a plurality of electrodes and a plurality of wirings. 8A shows the input electrodes of the driving transistor and the pixel transistor of the first electrode layer. Although not shown, the first electrode layer may include gate lines not shown.

The first and second control electrodes GE-D and GE-P are formed in the non-display area NDA and the display area DA of the first base substrate BS1, respectively, as shown in FIG. 8A do. In the present embodiment, the first and second control electrodes GE-D and GE-P may be formed at the same time.

For example, the first and second control electrodes GE-D and GE-P may be formed by forming a conductive layer on the first base substrate BS1, patterning the conductive layer through a photolithography process, . Alternatively, the first and second control electrodes GE-D and GE-P may be formed through a deposition method using a patterned mask.

Thereafter, the first insulating layer 10 is formed on the first and second control electrodes GE-D and GE-P. The first insulating layer 10 covers the first and second control electrodes GE-D and GE-P. The first insulating layer 10 may be formed by vapor deposition or sputtering.

Then, as shown in FIG. 8B, a semiconductor layer SL is formed on the first insulating film 10. The semiconductor layer SL includes a metal oxide semiconductor material. In this embodiment, the semiconductor layer SL may illustratively include indium titanium zinc oxide or indium gallium zinc oxide. The semiconductor layer SL may be formed by a patterning, sputtering, or vapor deposition method.

Thereafter, as shown in FIGS. 8C to 8E, the semiconductor layer SL is patterned. In this embodiment, the semiconductor layer SL may be patterned by a photoresist process.

As shown in FIG. 8C, a photoresist film PR is formed on the semiconductor layer SL. The photoresist film PR may include a positive photosensitive material. However, this is exemplarily described, and in another embodiment, the photoresist film PR may include a negative photosensitive material.

A mask HM is disposed on the photoresist film PR and irradiated with light LS. The mask HM may be a halftone mask. For example, the mask HM may include a first region AR1 for blocking incident light, a second region AR2 for transmitting incident light, and a second region AR2 which is higher than the transmittance of the first region AR1, AR2 that is lower than the transmittance of the second region AR2.

The mask HM overlaps the first input electrode GE-D so that the first region AR1 overlaps the second input electrode GE-P and the third region AR3 overlaps the first input electrode GE- And is disposed on the photoresist film PR. The light LS is irradiated to the photoresist film PR in a different amount of light for each region by the mask HM.

Thereafter, as shown in FIG. 8D, the photoresist film PR is developed to form a first photoresist pattern PP-1 and a second photoresist pattern PP-2. The first photoresist pattern PP-1 overlaps with the first input electrode GE-D and the second photoresist pattern PP-2 overlaps with the second input electrode GE-P. do. The first photoresist pattern PP-1 has a lower thickness than the second photoresist pattern PP-2.

Thereafter, as shown in FIG. 8E, the semiconductor layer SL is etched to form the first semiconductor pattern SL-D and the second semiconductor pattern SL-P. The etching process of the semiconductor layer SL may include dry etching or wet etching, but in this embodiment, the dry etching process is exemplified.

The semiconductor layer SL is exposed to an etching gas (not shown) and etched. The portion of the first photoresist pattern PP-1 covered with the second photoresist pattern PP-2 is not exposed by the etching gas, and the first semiconductor pattern SL- And the second semiconductor pattern SL-P are formed.

At this time, the etching gas can etch the second photoresist pattern PP-1 from the first photoresist pattern PP-1. Accordingly, the first photoresist pattern PP-1 may be removed and the first semiconductor pattern SL-D may be exposed.

The second photoresist pattern PP-2 is partially etched due to the difference in thickness from the first photoresist pattern PP-1 to form the third photoresist pattern PP-3. The third photoresist pattern PP-3 has a lower thickness than the second photoresist pattern PP-2.

Then, as shown in FIGS. 8F and 8G, the first semiconductor pattern SL-D is subjected to plasma processing to form a plasma-processed first semiconductor pattern SL-T. In the plasma processing, a plasma (PT) is provided on the first base substrate BS1.

At this time, the second semiconductor pattern SL-P is covered with the third photoresist pattern PP-3. Therefore, the plasma treatment is selectively performed on only the first semiconductor pattern SL-D among the first semiconductor pattern SL-D and the second semiconductor pattern SL-P. The third photoresist pattern PP-3 may be removed from the second semiconductor pattern SL-P after the plasma process or the plasma process.

The plasma (PT) can be generated by applying a high electric field to a reactive gas in a state of a highly reactive substance separated by electrons and ions. The plasma processing step according to an embodiment of the present invention may use a plasma generated from nitrogen or nitrogen oxide.

 The temperature of the first base substrate BS1 is maintained at a predetermined process temperature and nitrogen gas or nitrogen oxide gas is injected into the reaction chamber and a high electric field corresponding to the process power is applied to the plasma, (PT). Accordingly, the plasma (PT) may be a nitrogen plasma or a nitrogen oxide plasma. The plasma PT reacts with the first semiconductor pattern SL-D to reduce internal defects of the first semiconductor pattern SL-D.

Each of the first semiconductor pattern SL-D and the second semiconductor pattern SL-P may include a plurality of defects such as a point defect therein. These defects are formed by capturing the charges moving in the first semiconductor pattern SL-D and the second semiconductor pattern SL-P and forming the first semiconductor pattern SL-D and the second semiconductor pattern SL- -P) may be a cause of lowering the charge mobility.

In the plasma processing step, the plasma PT is provided to the first semiconductor pattern SL-D to deactivate the defects by reducing or neutralizing defects in the first semiconductor pattern SL-D. Accordingly, the defect density of the plasma-treated first semiconductor pattern SL-T is reduced as compared with that of the first semiconductor pattern SL-D.

The second semiconductor pattern SL-P may correspond to the first semiconductor pattern SL-D not subjected to plasma processing. Therefore, the plasma-treated first semiconductor pattern SL-T may be disposed on the same layer and have a higher charge mobility than the second semiconductor pattern SL-P formed of the same material.

Then, as shown in FIGS. 8H and 8I, the plasma-treated first semiconductor pattern SL-T and the second semiconductor pattern SL-P are thermally treated to form a first active layer AL-D, 2 active layer AL-P are formed. The heat treatment step is a step of providing heat (HT) to the plasma-treated first semiconductor pattern SL-T and the second semiconductor pattern SL-P to substantially heat the temperature of the first base substrate BS1 And heat-treats the plasma-treated first semiconductor pattern SL-T and the second semiconductor pattern SL-P.

The annealing step includes annealing. Defects remaining in the plasma-treated first semiconductor pattern SL-T can be uniformly diffused by the heat treatment. The diffusion of the defects proceeds in the direction of lowering the entropy of the plasma-processed first semiconductor pattern SL-T energetically.

That is, the heat treatment energetically stabilizes the plasma-treated first semiconductor pattern SL-T and the second semiconductor pattern SL-P. In addition, the heat treatment improves the uniformity of the inner surface of the plasma-treated first semiconductor pattern SL-T and the second semiconductor pattern SL-P.

Defects existing in each of the first semiconductor pattern SL-T and the second semiconductor pattern SL-P subjected to the plasma treatment by the heat HT are removed or locally integrated defects are removed It can move uniformly.

The heat treatment is performed at a temperature lower than the crystallization temperature of the semiconductor material constituting the plasma-treated first semiconductor pattern SL-T and the second semiconductor pattern SL-P. Thus, the first active layer AL-D and the second active layer AL-P may be formed of amorphous silicon such as the plasma-treated first semiconductor pattern SL-T and the second semiconductor pattern SL- Of the crystal structure.

The first active layer AL-D and the second active layer AL-P have different charge mobilities. In this embodiment, the charge mobility of the first active layer AL-D is higher than the charge mobility of the second active layer AL-P.

The first active layer AL-D becomes a metastable state through the plasma treatment step and the heat treatment step. The metastable state may be more stable than the crystalline semiconductor layer, but may be more stable than the amorphous semiconductor layer that is not plasma treated. The first semiconductor pattern (SL-D: see FIG. 8E) further includes the plasma treatment step, so that the metastable state can be reached at a temperature lower than the crystallization temperature.

The electric charge moving inside the predetermined material layer improves as the material layer reaches the stable state. Stable material layers have higher charge mobility and faster response to the electric field. Therefore, the first active layer AL-D may further include the plasma treatment step to have a higher charge mobility than that of the second active layer AL-P composed of the same material.

Also, the first active layer AL-D may have a lower threshold voltage swing than the second active layer AL-P. The threshold voltage slope is a factor that affects the response speed together with the charge mobility, and a detailed description thereof will be described later.

Next, as shown in FIG. 8J, first and second protective films ES-D and ES-P are formed on the first active layer AL-D and the second active layer AL-P, respectively can do. The first and second protective layers ES-D and ES-P may be an etch stopper covering the first active layer AL-D and the second active layer AL-P.

The first and second protective films ES-D and ES-P include an inorganic material. The first and second protective layers ES-D and ES-P may be formed by applying an inorganic layer on the first active layer AL-D and the second active layer AL-P, . Meanwhile, in another embodiment of the present invention, the first and second protective films ES-D and ES-P may be omitted.

8K, a second electrode layer is formed on the first active layer AL-D and the second active layer AL-P to form the non-display area NDA and the display area The driving transistor TR-D and the pixel transistor TR-P are formed. In the present embodiment, the second electrode layer includes a first input electrode SE-D and a first output electrode DE-D disposed on the first active layer AL-D and spaced apart from each other, And a second input electrode SE-P and a second output electrode DE-P disposed on the active layer AL-P and spaced apart from each other.

Although not shown, the second electrode layer may further include data lines connected to the second input electrode SE-P. The second electrode layer may be formed at the same time.

The first and second input electrodes SE-D and SE-P and the first and second output electrodes DE-D and DE-P may be formed at the same time. For example, the first and second input electrodes SE-D and SE-P and the first and second output electrodes DE-D and DE- (ES-D, ES-P), and patterning the conductive layer through a photolithography process. Alternatively, the first and second input electrodes SE-D and SE-P and the first and second output electrodes DE-D and DE-P may be formed by a deposition method using a patterned mask .

Then, as shown in FIG. 8L, a display electrode PE is formed in the display region DA. A third insulating film 30 is formed on the pixel transistor TR-P before the display electrodes PE are formed.

The third insulating layer 30 may include an organic material and / or an inorganic material. The third insulating layer 30 may be formed of a single layer or a plurality of organic layers or inorganic layers. At this time, the third insulating layer 30 may not be formed on the driving transistor TR-D.

The third insulating film 30 insulates the pixel transistor TR-P and provides a flat surface on which the display electrode PE is to be formed. However, the third insulating layer 30 is not limited thereto, and may be formed to cover the driving transistor TR-D.

A predetermined through hole (TH) may be formed in the third insulating film (30). The display electrode PE is electrically connected to the pixel transistor TR-P through the through hole TH.

The display electrode PE may be formed by a patterning, a deposition, or a photolithography process. The display electrode PE may be one electrode constituting the display device according to the present invention.

For example, the display electrode PE may be a pixel electrode constituting a liquid crystal capacitor (LC: see FIG. 2A). Although not shown, a common electrode, which is another electrode of the liquid crystal capacitor, is formed on the display electrode PE, and a liquid crystal layer controlled by a potential difference between the display electrode PE and the common electrode is formed. At this time, the common electrode may be provided on a separate substrate.

Alternatively, for example, the display electrode PE may be an anode electrode constituting an organic light emitting diode (OLED). Although not shown, a pixel defining layer defining an opening for exposing the display electrode PE is formed on the display electrode PE. The pixel defining layer can be formed by patterning an inorganic film.

Then, an organic light emitting layer for filling the openings is formed. The organic light emitting layer may be provided in a liquid phase, and then patterned through a drying process. A cathode electrode is formed on the organic light emitting layer. The cathode electrode may be formed to cover the pixel defining layer and the organic light emitting layer. At this time, a plurality of organic layers may be formed between the organic light emitting layer and the anode electrode, and between the organic light emitting layer and the cathode electrode. However, this is merely an example, and the display device according to one embodiment of the present invention can be formed by various processes, and is not limited to any one embodiment.

9A is a graph showing current-voltage characteristics of a pixel transistor according to an embodiment of the present invention, and FIG. 9B is a graph illustrating current-voltage characteristics of a driving transistor according to an embodiment of the present invention. 9C is a graph comparing electrical characteristics of a pixel transistor and a driving transistor according to an embodiment of the present invention. Hereinafter, electrical characteristics of the driving transistor according to an embodiment of the present invention will be described with reference to FIGS. 9A to 9C.

FIG. 9A shows the first group G1 and the second group G2, and FIG. 9B shows the third group G3 and the fourth group G4. The first group G1 includes the data voltages applied to the second group G2 and the third group G3 includes the data voltages higher than the fourth group G4 . ≪ / RTI > In this embodiment, a data voltage of about 5.1 V is applied to the first group G1 and the third group G3, respectively, and a data voltage of about 5.1 V is applied to the second group G2 and the fourth group G4. A data voltage of about 0.1 (V) was applied.

Meanwhile, the embodiments included in each of the first to fourth groups G1, G2, G3 and G4 have the same structure and are made of the same material. In the present embodiment, each of the first to fourth groups G1, G2, G3, and G4 is composed of thin film transistors having a width-length ratio (W / L) of 25/15.

As shown in FIGS. 9A and 9B, the first group G1 and the third group G3 have gate voltages V1 and V2 which are substantially equal in potential to the second group G2 and the fourth group G4, Has a high on-current value (I _D ) relative to the reference voltage (V _G ). And the output value is generally increased as the higher data voltage is applied to the gate voltage V _G of the same potential.

9A and 9B, the third group G3 has a slope of a graph as compared with the first group G1 and has a high on-current value I _D. Similarly, the fourth group G4 has a higher slope of the graph and a higher on-current value I _D than the second group G2. Therefore, it can be seen that the transfer characteristic of the driving transistor TR-D is improved as compared with the pixel transistor TR-P.

Further, when comparing Figs. 9A and 9B, the graph shown in Fig. 9A has more uniform plots than the graph shown in Fig. 9B. That is, the transfer characteristics of the embodiments shown in Fig. 9B are more uniform than the embodiments shown in Fig. 9A. Therefore, it can be seen that the driving transistor TR-D has improved device uniformity compared to the pixel transistor TR-P.

9C shows a comparison of the charge mobility PL-M and the threshold voltage slope PL-S of the pixel transistor TR-D and the driving transistor TR-D. Referring to FIG. 9C, the charge mobility of the driving transistor TR-D is higher than that of the pixel transistor TR-P. In this embodiment, the charge mobility of the driving transistor TR-D may be about 130% or more of the charge mobility of the pixel transistor TR-P.

Also, the driving transistor TR-D has a lower threshold voltage swing than the pixel transistor TR-P. The threshold voltage slope is related to the on-off characteristics of the thin film transistor. The lower the threshold voltage slope, the easier on-off control is. In this embodiment, the threshold voltage slope of the driving transistor TR-D may have a value reduced by about 12% from the threshold voltage slope of the pixel transistor TR-P.

In general, the charge mobility and the threshold voltage gradient may be in conflict with the carrier concentration in the active layer of the thin film transistor. For example, the charge mobility tends to increase as the carrier concentration increases. That is, as the carrier concentration increases, the charge mobility characteristics of the thin film transistor tend to be improved.

Alternatively, the threshold voltage gradient increases as the carrier concentration increases. That is, as the carrier concentration increases, on-off characteristics of the thin film transistor tend to decrease. If the carrier concentration is increased, a current can flow even when a low gate voltage is applied, so that the on-off characteristics of the thin film transistor are degraded, and a leakage current or the like may occur.

9A to 9C, the driving transistor TR-D according to the embodiment of the present invention not only improves the charge mobility as compared with the pixel transistor TR-P, The on-off characteristic is also improved. As the driving transistor TR-D according to an embodiment of the present invention becomes a metastable state through reduction of internal defects, the electrical characteristics can be improved without changing the carrier concentration.

The display device according to an embodiment of the present invention has different electrical characteristics required in each of the driving circuit portion and the pixel. In general, the driving transistor constituting the driving circuit portion is required to have higher charge mobility and higher on-off characteristic than the pixel transistor constituting the pixel.

In the display device according to an embodiment of the present invention, the driving transistor TR-D and the pixel transistor TR-P are formed of the same material and have the same design value, . ≪ / RTI > The method of manufacturing a display device according to an embodiment of the present invention further includes a plasma processing step so that thin film transistors having different electrical characteristics can be formed simultaneously without changing the material. In addition, the method of manufacturing a display device according to an embodiment of the present invention further includes the plasma treatment, thereby stably designing the device, thereby improving the reliability of the formed display device.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible. In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, and all technical ideas which fall within the scope of the following claims and equivalents thereof should be interpreted as being included in the scope of the present invention .

100: display panel 200: gate drive circuit
300: Data driving circuit TR-P: Pixel thin film transistor
TR-D: driving thin film transistor AL-D: first active layer
AL-P: Second active layer

Claims (16)

A pixel disposed in a display region of the base substrate, the pixel including a pixel transistor including a first active layer; And
And a driving circuit portion including a driving transistor arranged in a non-display region of the base substrate to apply an electrical signal to the pixel and including a second active layer,
Wherein the first active layer and the second active layer are made of the same material,
Wherein the second active layer has a charge mobility higher than a charge mobility of the first active layer. The method according to claim 1,
Wherein the plurality of pixels are provided,
The driving circuit unit includes:
And a gate driving circuit including a plurality of transistors and sequentially applying a gate signal to each of the pixels,
And the transistors include the driving transistor. The method according to claim 1,
Wherein the pixel transistor includes a first electrode layer disposed below the first active layer with an insulating film therebetween, and a second electrode layer disposed above the first active layer,
Wherein the driving transistor includes a third electrode layer disposed on the same layer as the first electrode layer and a fourth electrode layer disposed on the same layer as the second electrode layer,
Wherein the first active layer and the second active layer are disposed on the same layer. The method of claim 3,
And a display electrode connected to the pixel transistor,
And the display electrode is disposed on the second electrode layer. The method according to claim 1,
Wherein a charge mobility of the driving transistor is about 130% or more of a charge mobility of the pixel transistor. 6. The method of claim 5,
Wherein the first active layer and the second active layer are made of an amorphous oxide semiconductor material. The method according to claim 6,
Wherein the oxide semiconductor material comprises indium tin zinc oxide. And a driving circuit unit disposed in a non-display area adjacent to the display area, wherein the pixel includes a pixel transistor, and the driving circuit unit includes a driving transistor,
Forming a first oxide semiconductor pattern and a second oxide semiconductor pattern each made of the same oxide semiconductor material in the display region and the non-display region;
Selectively plasma-treating the second oxide semiconductor pattern of the first oxide semiconductor pattern and the second oxide semiconductor pattern; And
And heat treating the first oxide semiconductor pattern and the plasma-treated second oxide semiconductor pattern such that a first active layer of the pixel transistor and a second active layer of the driving transistor are formed. 9. The method of claim 8,
Forming the first oxide semiconductor pattern and the second oxide semiconductor pattern, respectively,
Forming a semiconductor layer including the oxide semiconductor material on the display region and the non-display region of the base substrate;
Forming a photoresist film on the semiconductor layer;
The first photoresist pattern corresponding to the first oxide semiconductor pattern and the second photoresist pattern corresponding to the second oxide semiconductor pattern and having a thickness lower than that of the first photoresist pattern are formed using the halftone mask, Etching the resist film; And
Etching the exposed areas of the semiconductor layer with the etched photoresist film,
Wherein the second photoresist pattern is removed in the step of etching the semiconductor layer, and a third photoresist pattern having a reduced thickness is formed from the first photoresist pattern. 10. The method of claim 9,
Wherein the step of selectively plasma-treating the first oxide semiconductor pattern comprises:
Exposing the second oxide semiconductor pattern exposed from the first oxide semiconductor pattern and the second photoresist pattern covered by the third photoresist pattern to a plasma; And
And removing the third photoresist pattern after the step of removing the third photoresist pattern. 11. The method of claim 10,
Wherein the plasma is generated from nitrogen or nitrogen oxide gas. 12. The method of claim 11,
Wherein the step of forming the first semiconductor pattern and the second semiconductor pattern and the step of selectively plasma processing the first semiconductor pattern proceed in the same chamber. 9. The method of claim 8,
Wherein the step of heat-treating the first oxide semiconductor pattern and the plasma-treated second oxide semiconductor pattern proceeds at a temperature lower than a crystallization temperature of the oxide semiconductor material. 9. The method of claim 8,
Forming a first electrode layer on the base substrate before forming the first oxide semiconductor pattern and the second oxide semiconductor pattern, respectively; And
And forming a second electrode layer on the first active layer and the second active layer after the heat treatment of the first oxide semiconductor pattern and the plasma-treated second oxide semiconductor pattern,
Wherein the first electrode layer is disposed on the same layer and includes a first electrode pattern superimposed on the first active layer and a second electrode pattern overlapping the second active layer,
Wherein the second electrode layer is disposed on the same layer and includes a third electrode pattern overlapping the first active layer and a fourth electrode pattern overlapping the second active layer. 15. The method of claim 14,
And forming a display electrode connected to the pixel transistor in the display region,
Wherein the display electrode is formed on the second electrode pattern. 16. The method of claim 15,
Forming gate signal lines connected to the pixel transistors in the display region; And
Forming data signal lines connected to the pixel transistors and insulated from the gate signal lines,
Wherein the gate signal lines are formed simultaneously with the first electrode layer.

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