KR20150107400A - Light emitting diode - Google Patents

Abstract

The present invention relates to a flip-chip type light emitting diode. The light emitting diode according to the present invention includes: a semiconductor stacked body comprising: a first conductive type semiconductor layer, a second conductive type semiconductor layer arranged on the first conductive type semiconductor layer, and an active layer arranged between the first conductive type semiconductor layer and second conductive type semiconductor layer; a first electrode arranged on the first conductive type semiconductor layer; a second electrode arranged on the second conductive type semiconductor layer; and bumps electrically connected to each of the first electrode and second electrode. The semiconductor stacked body includes: a first area where the first conductive type semiconductor layer is exposed; and a second area where the active layer and the second conductive type semiconductor layer are arranged. The first area includes: a first electrode area where the first electrode is arranged; and an extended area connected to the first electrode area. The first electrode area is surrounded by the second area except an area connected with the extended area.

Description

[0001] LIGHT EMITTING DIODE [0002]

The present invention relates to light emitting diodes. More particularly, the present invention relates to a flip chip type light emitting diode.

BACKGROUND ART GaN-based LEDs have been used in a variety of applications such as color LED display devices, LED traffic signals, backlight units, and lighting devices since gallium nitride (GaN) -based LEDs have been developed.

The gallium nitride series light emitting diode is generally formed by growing epitaxial layers on a substrate such as sapphire, and includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer interposed therebetween. On the other hand, an n-electrode is formed on the n-type semiconductor layer, and a p-electrode is formed on the p-type semiconductor layer. The light emitting diode is electrically connected to the external power source through the electrodes and driven. At this time, a current flows from the p-electrode to the n-electrode through the semiconductor layers.

On the other hand, a flip-chip type light emitting diode is used to prevent light loss due to the p-electrode and to increase heat dissipation efficiency. Since the light emitting diode having a horizontal structure has to transmit heat through a growth substrate such as a sapphire substrate, the heat dissipation efficiency is low. On the other hand, the flip chip type light emitting diodes transmit heat through the electrodes, and thus the heat dissipation efficiency is high. In addition, since the flip chip type light emitting diode emits light to the outside through the growth substrate, light loss due to the p-electrode can be reduced as compared with a light emitting diode having a horizontal structure that emits light to the outside through the epi layer. Particularly, a light emitting diode that emits light of a high energy such as a deep ultraviolet light emitting diode generates a light loss due to a p-type semiconductor layer, and thus adopts a flip chip type structure.

A light emitting diode having a current crowding effect in a light emitting diode and having a shape suitable for flip chip packaging is disclosed in U.S. Patent No. 7,928,451 entitled " SHAPED CONTACT LAYER FOR LIGHT EMITTING HETEROSTRUCTURE & have.

1 is a schematic plan view for explaining a conventional flip chip type light emitting diode.

1, the light emitting diode includes a substrate 11, an n-type semiconductor layer 13, a p-type semiconductor layer 17, an active layer, an n-electrode 19, a p- 30a and a p-bump 30b. The substrate 11 may be, for example, a sapphire substrate as a growth substrate for growing a gallium nitride-based semiconductor layer. The p-type semiconductor layer 17 is located on a part of the n-type semiconductor layer 13 as a contact layer and has an H-shape. The p-type semiconductor layer 17 has a shape recessed inward from both sides of the central region.

The n-electrode 19 is in ohmic contact with the n-type semiconductor layer 13 and the p-electrode 20 is in ohmic contact with the p-type semiconductor layer 17 along the shape of the p-type semiconductor layer 17. On the other hand, the n-bump 30a is located on the n-electrode 19 along one side edge of the substrate 11 in parallel with the p-type semiconductor layer 17. In addition, the p-bump 30b is located on the p-electrode 20. The p-bump 30b has a shape similar to that of the p-electrode 20.

In the conventional flip chip type light emitting diode, the n-electrode completely surrounds the p-electrode, and the p-type semiconductor layer is recessed inward to diffuse the current of the light emitting diode. Accordingly, it is difficult to maximize the area of the p-type semiconductor layer, which is a light emitting region, and thus there is a problem in manufacturing a high output light emitting diode and a large area light emitting diode. Therefore, in the prior art, a plurality of flip chip type light emitting diodes are used together to manufacture deep ultraviolet light emitting diodes requiring high output. However, light emitting diodes formed of thin film layers grown on one wafer and light emitting diodes formed of thin films grown on different wafers exhibit deviations in electrical and optical characteristics. Accordingly, when a plurality of light emitting diodes are used together, the overall reliability of the light emitting diode is deteriorated. In addition, since a plurality of light emitting diodes are fabricated and packaged together, the mass production of the light emitting diodes and the overall yield are inferior.

U.S. Patent No. 7,928,451

A problem to be solved by the present invention is to provide a light emitting diode which can easily disperse a current and is suitable for flip chip packaging.

Another object of the present invention is to provide a high output light emitting diode with improved reliability.

Another object of the present invention is to provide a large area light emitting diode.

Another object of the present invention is to provide a light emitting diode having improved overall yield and productivity.

A light emitting diode according to an embodiment of the present invention includes a first conductive semiconductor layer, a second conductive semiconductor layer disposed on the first conductive semiconductor layer, and a second conductive semiconductor layer formed on the first conductive semiconductor layer, A semiconductor laminate including an active layer disposed between semiconductor layers; A first electrode disposed on the first conductive semiconductor layer; A second electrode disposed on the second conductive semiconductor layer; Wherein the semiconductor layer includes a first region in which the first conductive type semiconductor layer is exposed and a second region in which the active layer and the second conductive type semiconductor layer are disposed Wherein the first region includes a first electrode region in which the first electrode is disposed and an extension region connected to the first electrode region, And may be surrounded by the second region except for the portion connected to the second region.

The second region may include at least one first light emitting region, at least one second light emitting region, and at least one connection region connecting the at least one first light emitting region and the at least one second light emitting region can do.

Further, the first light emitting region and the second light emitting region may be separated by the extension region.

The first light emitting region and the second light emitting region may be symmetrical with respect to the extension region.

In some embodiments, the bumps include a first bump and a second bump, the first bump is disposed on a first electrode, and the second bump is disposed on the first light emitting region and the second light emitting region And may be disposed on at least one area.

The total area of the second bumps may be at least half the total area of at least one of the first light emitting area and the second light emitting area in which the second bumps are disposed.

The apparatus of claim 1, further comprising an extension disposed in the extension region and connected to the first electrode, the extension comprising a first extension extending from the first electrode and a second extension extending from the first extension to at least two second And the extension may be disposed between the first light emitting area and the second light emitting area.

In some embodiments, the first luminescent region and the second luminescent region each include a first side that is a side facing each other, a second side that is a side opposite to the first side, and a second side that is a side connecting the first side and the second side The second aspect of the present invention.

Wherein the first extending portion is disposed near the first side faces of the first light emitting region and the second light emitting region and each of the second extending portions is disposed between the second side face and the third side face of each of the first light emitting region and the second light emitting region, Lt; / RTI >

At least one of the first extending portion and the second extending portion may include a concave portion on a side facing the second region.

The second region may include at least a part of the side surface facing the first extending portion and the second extending portion.

The second electrode may have irregularities formed along the irregularities.

Furthermore, an insulating layer covering the semiconductor stack may be further included, and the insulating layer may include a distributed Bragg reflector (DBR).

The second electrode may further include a reflective layer reflecting the light generated in the active layer.

The semiconductor laminate may be entirely rectangular in shape and the major axis length of the semiconductor laminate may be 1.5 to 2 times the minor axis length.

A light emitting diode according to another exemplary embodiment of the present invention includes a first conductive semiconductor layer, a second conductive semiconductor layer disposed on the first conductive semiconductor layer, and a second conductive semiconductor layer formed on the first conductive semiconductor layer, A semiconductor laminate including an active layer disposed between semiconductor layers; A first electrode disposed on the first conductive semiconductor layer; An extension disposed on the first conductive semiconductor layer and connected to the first electrode; And a second electrode disposed on the second conductive type semiconductor layer, wherein the semiconductor layered structure includes a first region in which the first conductive type semiconductor layer is exposed, and a second region in which the active layer and the second conductive type semiconductor layer are disposed Wherein the first region includes a first electrode region in which the first electrode is disposed and an extension region in which the extension connected to the first electrode region is disposed and extends to one side, The second region includes a first light emitting region, a second light emitting region, and a connection region connecting the first light emitting region and the second light emitting region, wherein the first electrode region includes a portion excluding the portion connected to the extension region And the connection region may be disposed near the side opposite to the side on which the extension region of the first electrode region extends.

According to the embodiments of the present invention, the current concentration effect can be reduced, and a light emitting diode suitable for flip chip packaging can be provided. In addition, since the LEDs exhibit uniform electrical and optical characteristics as compared with conventional LEDs, a high-output LED having improved reliability can be provided.

The light emitting diode according to the present invention does not require a process of packaging a plurality of light emitting diodes as compared with the conventional manufacturing process of a high output light emitting diode, so that the mass productivity and the overall yield are improved. In addition, it is possible to make the light emitting diodes large-sized more easily.

1 is a schematic plan view for explaining a conventional flip chip type light emitting diode.
2 is a schematic plan view illustrating a flip chip type light emitting diode according to an embodiment of the present invention.
3 is a schematic cross-sectional view taken along the perforated line AA of FIG. 2 to illustrate a flip chip type light emitting diode according to an embodiment of the present invention.
4 is a schematic plan view illustrating a flip chip type light emitting diode according to another embodiment of the present invention.
5 is a schematic plan view illustrating a flip chip type light emitting diode according to another embodiment of the present invention.
6 is a schematic plan view illustrating a flip chip type light emitting diode according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to designate the same or similar components throughout the drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, exemplary embodiments of the present invention will be described below, but the technical spirit of the present invention is not limited thereto, and various modifications may be made by those skilled in the art.

FIG. 2 is a schematic plan view for explaining a flip chip type light emitting diode according to an embodiment of the present invention, and FIG. 3 is a sectional view taken along the cut line A-A of FIG.

2 and 3, the light emitting diode includes a transparent substrate 51, a first conductive semiconductor layer 53, an active layer 55, a second conductive semiconductor layer 57, a first electrode 59, The second electrode 60, the insulating layer 63, the first bump 70a, the second bump 70b, the extension portion 71, the first light emitting region LA1, the second light emitting region LA2, And a region (CA). In addition, the extension portion 71 includes a first extension portion 71a and a second extension portion 71b. Each of the first and second light emitting regions LA1 and LA2 includes a first side surface 81, a second side surface 83, a third side surface 85, and a fourth side surface 87. The dotted line B represents a boundary between the first and second light emitting regions LA1 and LA2 and the connection region CA.

The transparent substrate 51 may be a substrate having a hexagonal crystal structure. The transparent substrate 51 may be a growth substrate for growing gallium nitride-based epitaxial layers, for example, sapphire, silicon carbide, or gallium nitride. In particular, in order to provide a deep ultraviolet light emitting diode, the transparent substrate 51 may be a sapphire substrate. The transparent substrate 51 includes top, bottom and side surfaces. The upper surface of the transparent substrate 51 is a surface on which semiconductor layers are grown and the lower surface is a surface on which light generated in the active layer 55 is emitted to the outside. The sides connect the top and bottom. The side surface of the transparent substrate 51 may be a surface perpendicular to the upper surface and the lower surface, but is not limited thereto and may include an inclined surface. In this embodiment, although the transparent substrate 51 is rectangular, the shape of the transparent substrate 51 is not limited to this, and may be various shapes such as a rectangular shape, a diamond shape, and a circular shape.

The first conductive type semiconductor layer 53 is located on the upper surface of the transparent substrate 51. The first conductive semiconductor layer 53 may cover the entire upper surface of the transparent substrate 51 but is not limited thereto and may include a first conductive semiconductor layer 53 ) May be limited within the upper surface of the transparent substrate 51.

The second conductivity type semiconductor layer 57 may be disposed on the first conductivity type semiconductor layer 53. The active layer 55 may be positioned between the first conductivity type semiconductor layer 53 and the second conductivity type semiconductor layer 57. A region where the active layer 55 and the second conductivity type semiconductor layer 57 are not disposed and a region where the first conductivity type semiconductor layer is exposed are the first region on the first conductivity type semiconductor layer 53. That is, the first region is a non-light emitting region. In contrast, the region where the active layer 55 and the second conductivity type semiconductor layer 57 are disposed on the first conductivity type semiconductor layer 53 is the second region. That is, the second region is a region where light is generated. The first region and the second region may be formed through a mesa etching process.

The first conductive semiconductor layer 53, the active layer 55 and the second conductive semiconductor layer 57 may be formed of a gallium nitride compound semiconductor material, that is, (Al, In, Ga) N. The composition ratio of the composition element is determined so that the active layer 55 emits light of a desired wavelength, for example, ultraviolet light or blue light.

The first conductive semiconductor layer 57 may be an n-type nitride semiconductor layer, the second conductive semiconductor layer 57 may be a p-type nitride semiconductor layer, or vice versa. The first conductivity type semiconductor layer 53 and / or the second conductivity type semiconductor layer 57 may be formed as a single layer or a multilayer structure. The active layer 55 may have a single quantum well structure or a multiple quantum well structure. The first conductive semiconductor layer 53, the active layer 55, and the second conductive semiconductor layer 57 may be formed using MOCVD or MBE techniques.

 The first conductivity type semiconductor layer 53, the second conductivity type semiconductor layer 57, the first conductivity type semiconductor layer 53, and the second conductivity type semiconductor layer 53, which are disposed on the first conductivity type semiconductor layer 53, The active layer 55 disposed between the layers 57 can be gathered to form a semiconductor laminate. The semiconductor laminate may include the first region and the second region described above.

When the semiconductor laminate is viewed from above, the semiconductor laminate may be entirely rectangular. When the semiconductor laminate is entirely rectangular, the major axis length of the semiconductor laminate may be 1.5 to 2 times the minor axis length. More specifically, when the length of the minor axis of the semiconductor laminate is 500 mu m, the length of the major axis may be 750 to 1000 mu m. If the length of the major axis of the semiconductor laminate is less than 1.5 times the minor axis length, the area of the second region which is the luminescent region is narrow, so that the light output of the light emitting diode is limited. Further, if the length of the minor axis of the semiconductor stacked body is more than two times, the current diffusion into the second region may be lowered.

As a result, the area of the second region, which is the light emitting region, can be widened as compared with the first region, which is the light emitting region, so that the light output of the light emitting diode can be improved. In this embodiment, the shape of the semiconductor laminate is shown as a rectangle, but the shape of the semiconductor laminate is not limited to this, and can be variously modified.

The second region may include a first emission region LA1, a second emission region LA2, and a connection region CA. The first light emitting region LA1, the second light emitting region LA2, and the connection region CA are regions capable of generating light. The first light emitting region LA1 and the second light emitting region LA2 are spaced apart from each other and may be connected through a connection region CA. In the drawing, the light emitting regions LA1 and LA2 and the connecting region CA are separated through a dotted line B. In this specification, the light emitting region and the connecting region are divided by the boundary of the first region. In particular, as shown by the dotted line (B), the edge of the first region, which is in common contact with the first light emitting region and the second light emitting region, It is distinguished by an extension of the edge. In this embodiment, the first light emitting region LA1 and the second light emitting region LA2 may be entirely rectangular, but the shapes of the first light emitting region LA1 and the second light emitting region LA2 are not limited thereto .

Specifically, each of the first light emitting region LA1 and the second light emitting region LA2 includes a first side surface 81, a second side surface 83, a third side surface 85 and a fourth side surface 87 . The first side surface 81 is a side where the first light emitting region LA1 and the second light emitting region LA2 face each other. The second side surface 83 is located farthest from the connection area CA among the side surfaces included in the first light emitting area LA1 and the second light emitting area LA2, (85). The third side 85 is the side opposite the first side 81. The fourth side surface 87 is a side surface that connects the first side surface 81 and the third side surface 85 and corresponds to a dotted line B which is a boundary line.

The first region may include a first electrode region to be formed with the first electrode 59 connected to the first conductivity type semiconductor layer 53 and an extension region that is an area where the extension portion 71 is to be formed . The first electrode region may be connected to the extension region. A portion of the extension region may be disposed between the first light emitting region LA1 and the second light emitting region LA2 and the other portion may be formed in a shape that surrounds the first light emitting region LA1 and the second light emitting region LA2 As shown in FIG. The first light emitting region LA1 and the second light emitting region LA2 may be separated by an extension region. The first light emitting region LA1 and the second light emitting region LA2 may be symmetrical with respect to the extension region.

2, the extension region is located near the first side 81, the second side 83, and the third side 85 of the first light emitting region LA1 and the second light emitting region LA2, respectively, Can be uniformly arranged. The second region may surround a portion of the first electrode region and the extension region of the first region, and the first region may surround the first light emitting region LA1 and the second light emitting region LA2 of the second region, . That is, since the first region and the second region are arranged so as to surround each other, they can easily diffuse the current between them, and the output of the light emitting diode can be improved.

The first electrode 59 may be disposed in the first electrode region included in the first region. The second electrode 60 may be disposed in the first emission region LA1, the second emission region LA2, and the connection region CA included in the second region. The second electrode 60 may cover the first emission region LA1, the second emission region LA2, and the connection region CA.

The first electrode 59 may be disposed on the first conductivity type semiconductor layer 53 and may be electrically connected to the first conductivity type semiconductor layer 53. The first electrode 59 may be uniformly spaced from the second conductive semiconductor layer 57. Thus, the current concentration phenomenon can be prevented. Further, concaves and convexes (not shown) may be formed on the surface of the first conductivity type semiconductor layer 53 between the first electrode 59 and the second conductivity type semiconductor layer 57. The current can be prevented from flowing along the surface of the second conductivity type semiconductor layer 53 by the unevenness, and the current can be further dispersed.

The second electrode 60 may be disposed on the second conductive semiconductor layer 57 and may be electrically connected to the second conductive semiconductor layer 57. The second electrode 60 may include a reflective layer (not shown) and a barrier layer (not shown). The reflective layer may include Ag, Ag alloy, Al or Al alloy, and may include, for example, Ni / Au / Al. The barrier layer may be formed of Ni, Cr, Ti, Pt, Rd, Ru, W, Mo, TiW or a composite layer thereof.

The extension portion 71 may include a first extension portion 71a and a second extension portion 71b. The first extension portion 71a and the second extension portion 71b may be disposed in the extension region. The first electrode 59 may be connected to the first extending portion 71a and the first extending portion 71a may be connected to the second extending portion 71b. The first electrode 59, the first extension 71a, and the second extension 71b may be electrically connected. The first extended portion 71a may be disposed between the first light emitting region LA1 and the second light emitting region LA2. The first light emitting region LA1 and the second light emitting region LA2 may be symmetrical with respect to the first extending portion 71a. The second extension 71b may be branched at the first extension 71a. Thus, one extension 71 may include one first extension 71a and two second extensions 71b. The branched second extensions 71b may cover two consecutive sides of the first light emitting region LA1 and the second light emitting region LA2. 2, the first extending portion 71a and the second extending portion 71b are formed by stacking an active layer 55 (see FIG. 2) included in each of the first light emitting region LA1 and the second light emitting region LA2, The first side 81 including the first light emitting region LA1 and the second light emitting region LA2 is formed in a state of being uniformly spaced from the first conductive semiconductor layer 57, the second conductive semiconductor layer 57, , The second side surface 83, and the third side surface 85.

The portion of the second extension 71b disposed adjacent to the third side face 85 is located at the side of the third side 85 included in each of the first light emitting region LA1 and the second light emitting region LA2, 2, and may be shorter than the third side 85 length. As shown in Fig. 2, an end of the second extending portion 71b may be terminated near the dotted line B. Accordingly, the connection region can have a constant width and surround the first electrode region, and current concentration phenomenon can be prevented more effectively through the above-described range of lengths. However, if necessary, the second extended portion 72b may extend to a part of the connecting region beyond the dotted line B.

The extended portion 71 can be electrically connected to the first electrode 59 and the first conductive type semiconductor layer 53 so that the current applied to the first electrode 59 can be efficiently supplied to the second electrode 59 through the above- Conductivity-type semiconductor layer 57 as shown in FIG. Therefore, the light emitting diode according to the present embodiment can prevent current concentration phenomenon.

The first bump 70a may be disposed on the first electrode 59. And the second bump 70b may be disposed on the second electrode 60. The second bump 70b may be disposed on the first light emitting area LA1 and the second light emitting area LA2. The second bump 70b may be disposed on the first light emitting area LA1 or the second light emitting area LA2. In this embodiment, although the second bump 70b is shown as being disposed on the first light emitting area LA1 and the second light emitting area LA2, it is not limited thereto.

 The total area of the second bump 70b formed on the first light emitting area LA1 is equal to or more than half the area of the first light emitting area LA1 and the second bump 70b formed on the second light emitting area LA2, May be more than half the area of the second light emitting area LA2. When the second bump 70b is disposed in either the first light emitting area LA1 or the second light emitting area LA2, the total area of the second bumps 70b is smaller than the area of the arranged light emitting area It can be more than half. When a plurality of second bumps 70b are disposed on the first light emitting area LA1 and / or the second light emitting area LA2, they all have the same polarity.

As the total area of the second bumps 70b occupied in the first light emitting area LA1 and the second light emitting area LA2 is wider, it is possible to manufacture light emitting diodes with higher output. Preferably occupies an area of 1/2 to 2/3 of the total area of each of the first light emitting area LA1 and the second light emitting area LA2. The first bump 70a and the second bump 70b may be formed of the same metal material. In addition, the first and second bumps 70a and 70b may be formed in a multi-layer structure, and may include, for example, an adhesive layer, a diffusion preventing layer, and a bonding layer. The bonding layer may include, for example, Ti, Cr or Ni, and the diffusion preventing layer may be formed of Cr, Ni, Ti, W, Ti, W, Mo, Pt or a composite layer thereof. Or AuSn. 2, a single second bump 70b is formed on each of the light emitting regions LA1 and LA2, but a plurality of bumps may be formed on each light emitting region. Also, a plurality of first bumps 70a may be formed on the first electrode 59 as well.

The insulating layer 63 may be disposed on the upper surface of the semiconductor stack body except for the regions where the first bumps 70a and the second bumps 70b are formed. The insulating layer 63 may be formed of an oxide film such as SiO ₂ , a nitride film such as SiNx, or an insulating film of SiON or MgF ₂ using a technique such as chemical vapor deposition (CVD). The insulating layer 63 may be formed of a single layer, but is not limited thereto and may be formed of multiple layers. Further, the insulating layer 63 may be formed of a distributed Bragg reflector (DBR) in which a low refractive material layer and a high refractive material layer are alternately laminated. For example, an insulating reflection layer having a high reflectance can be formed by laminating layers such as SiO ₂ / TiO ₂ and SiO ₂ / Nb ₂ O ₅ . The insulating layer 63 may be formed using a technique such as chemical vapor deposition (CVD).

4 is a schematic plan view illustrating a flip chip type light emitting diode according to another embodiment of the present invention. This embodiment is the same as the embodiment of Fig. 2 except for the arrangement area of the second bumps 70b. Hereinafter, a duplicate description will be omitted.

Referring to FIG. 4, the second bump 70b included in the light emitting diode is formed on the region including the first light emitting region LA1 and the second light emitting region LA2, As shown in FIG. By comparing this embodiment with the embodiment of FIG. 2, this embodiment can arrange the second bumps 70b which occupy less area.

5 is a schematic plan view illustrating a flip chip type light emitting diode according to another embodiment of the present invention. This embodiment is the same as the embodiment of Fig. 2 except for the concave / convex portion 73. Fig. Hereinafter, a duplicate description will be omitted.

Referring to FIG. 5, the second extended portion 71b of the extended portion 71 included in the light emitting diode includes a concave portion on a side facing the second region. Specifically, the second extended portion 71b may include a concave portion on a side facing the third side surface 85 included in each of the first light emitting region LA1 and the second light emitting region LA2.

Also, although not shown, the second region may include a concave portion on the side facing the first extending portion 71a and the second extending portion 71b. In this case, the second electrode 60 disposed in the second region may have irregularities formed along the irregularities. The current diffusion and the light extraction efficiency can be improved through the concave and convex portions 73. [ In this embodiment, the shape of the concave-convex portion 73 is a saw-tooth shape, but the shape of the concave-convex portion 73 is not limited to this.

6 is a schematic plan view illustrating a flip chip type light emitting diode according to another embodiment of the present invention. This embodiment is the same as the embodiment of FIG. 5 except that the number of elements or the area occupied by the elements of FIG. 5 are each doubled. Hereinafter, a duplicate description will be omitted.

Referring to FIG. 6, two light emitting diodes according to the embodiment of FIG. 5 are arranged side by side and integrally connected to each other to form a part of the connection area CA and a part of the second extension part 71b Respectively. That is, since the light emitting diode according to the present embodiment can be made large-sized, various purposes and needs can be met.

It will be apparent to those skilled in the art that various modifications, substitutions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. will be. Therefore, the embodiments disclosed in the present invention and the accompanying drawings are intended to illustrate and not to limit the technical spirit of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments and the accompanying drawings . The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

11: substrate
13: n-type semiconductor layer
17: p-type semiconductor layer
19: n- electrode
20: p-electrode
30a: n-bump
30b: p-bump
51: transparent substrate
53: first conductive type semiconductor layer
55:
57: second conductive type semiconductor layer
59: first electrode
60: Second electrode
63: insulating layer
70a: First bump
70b: second bump
71: Extension part
71a: first extension portion
71b:
73: concave and convex portion
81: First aspect
83: Second aspect
85: Third aspect
87: fourth aspect
LA1: first light emitting region
LA2: second light emitting region
CA: Connection area

Claims (16)

A first conductivity type semiconductor layer, a first conductivity type semiconductor layer, a second conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. A laminate;
A first electrode disposed on the first conductive semiconductor layer;
A second electrode disposed on the second conductive semiconductor layer;
And bumps electrically connected to the first electrode and the second electrode, respectively,
The semiconductor laminate includes a first region in which the first conductivity type semiconductor layer is exposed and a second region in which the active layer and the second conductivity type semiconductor layer are disposed,
Wherein the first region includes a first electrode region in which the first electrode is disposed, and an extension region connected to the first electrode region,
Wherein the first electrode region is surrounded by the second region except for a portion connected to the extension region. The method according to claim 1,
Wherein the second region includes at least one first light emitting region, at least one second light emitting region, and at least one connection region connecting the at least one first light emitting region and the at least one second light emitting region, diode. The method of claim 2,
Wherein the first light emitting region and the second light emitting region are separated by the extension region. The method of claim 2,
Wherein the first light emitting region and the second light emitting region are symmetrical with respect to the extension region. The method of claim 2,
The bumps comprising a first bump and a second bump,
The first bump being disposed on the first electrode,
And the second bump is disposed on at least one of the first light emitting region and the second light emitting region. The method of claim 5,
The total area of the second bumps is,
Wherein the second light emitting region is at least half the total area of at least one of the first light emitting region and the second light emitting region in which the second bump is disposed. The method according to claim 1,
Further comprising an extension disposed in the extension region and connected to the first electrode,
Wherein the extension comprises a first extension extending from the first electrode and at least two second extensions branched from the first extension,
And the first extending portion is disposed between the first light emitting region and the second light emitting region. The method of claim 7,
Wherein the first light emitting region and the second light emitting region each have a first side that is a side facing each other, a second side that is a side opposite to the first side, and a third side that connects the first side and the second side Emitting diode. The method of claim 8,
The first extension is disposed near the first sides of the first light emitting area and the second light emitting area,
And each of the second extensions is disposed near the second side and the third side of each of the first light emitting area and the second light emitting area. The method of claim 7,
And at least one of the first extending portion and the second extending portion includes a concave portion on a side facing the second region. The method of claim 10,
And the second region includes at least a part of the side surface facing the first extending portion and the second extending portion. The method of claim 11,
And the second electrode has irregularities formed along the concavo-convex portion. The method according to claim 1,
And an insulating layer covering the semiconductor stacked body,
Wherein the insulating layer comprises a distributed Bragg reflector (DBR). The method according to claim 1,
Wherein the second electrode further comprises a reflective layer for reflecting the light generated in the active layer. The method according to claim 1,
Wherein the semiconductor laminate is entirely rectangular,
Wherein the major axis length of the semiconductor laminate is 1.5 to 2 times the minor axis length. A first conductivity type semiconductor layer, a first conductivity type semiconductor layer, a second conductivity type semiconductor layer disposed on the first conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. A laminate;
A first electrode disposed on the first conductive semiconductor layer;
An extension disposed on the first conductive semiconductor layer and connected to the first electrode; And
And a second electrode disposed on the second conductive type semiconductor layer,
The semiconductor laminate includes a first region in which the first conductivity type semiconductor layer is exposed and a second region in which the active layer and the second conductivity type semiconductor layer are disposed,
Wherein the first region includes a first electrode region in which the first electrode is disposed and an extension region in which the extension connected to the first electrode region is disposed and extends to one side,
Wherein the second region includes a first light emitting region, a second light emitting region, and a connection region connecting the first light emitting region and the second light emitting region,
Wherein the first electrode region is surrounded by the second region except for a portion connected to the extension region,
Wherein the connection region is disposed near a side opposite to a side where the extension region of the first electrode region extends.

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