KR20150081869A - Organic light emitting device and manufacturing thereof - Google Patents

Abstract

The organic light emitting device and a manufacturing method thereof according to an embodiment of the present invention comprises: a first sub-semiconductor located on the substrate; a gate insulation layer located on the first sub-semiconductor; a gate electrode located on the gate insulation layer; a first inter-layer insulation layer located on the gate electrode; a second sub-semiconductor located on the first inter-layer insulation layer and connected to the first sub-semiconductor; a source electrode and a drain electrode which are located on the second sub-semiconductor and are connected to the first and the second sub-semiconductor;; a pixel electrode electrically connected to the drain electrode; an organic light emitting member located on the pixel electrode; and a common electrode located on the organic light emitting member.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting display and a method of manufacturing the same.

2. Description of the Related Art In recent years, a cathode ray tube (CRT) has been replaced by a flat panel display device in response to such demands.

Flat panel display devices include liquid crystal display devices, field emission display devices, organic light emitting display devices, and plasma display panels. Of the flat panel display devices, organic light emitting display devices are attracting attention due to their low power consumption, fast response speed, wide viewing angle, and high contrast ratio.

An organic light emitting diode (OLED) display is a self-luminous display having two electrodes and a light emitting layer interposed therebetween. Electrons injected from one electrode and holes injected from another electrode are combined in the light emitting layer The excitons emit energy and emit light.

An object of the present invention is to improve the performance of a display device and to provide a uniform image by securing a channel region of a predetermined length or more through semiconductors connected to each other on a different layer.

An organic light emitting display according to an embodiment of the present invention includes a substrate, a first sub-semiconductor disposed on the substrate, a gate insulating film disposed on the first sub-semiconductor, a gate electrode positioned on the gate insulating film, A second sub-semiconductor located on the first interlayer insulating film and connected to the first sub-semiconductor; a second sub-semiconductor disposed on the second sub-semiconductor and connected to the first sub-semiconductor and the second sub- A pixel electrode electrically connected to the drain electrode, an organic light emitting member disposed on the pixel electrode, and a common electrode disposed on the organic light emitting member.

The semiconductor includes the first sub-semiconductor and the second sub-semiconductor, and the semiconductor may include a source region, a drain region, and a channel region.

The source electrode is connected to the source region, the drain electrode is connected to the drain region, and the control electrode can overlap the channel region.

The width of the first sub-semiconductor may be greater than the width of the second sub-semiconductor.

And a second interlayer insulating film disposed on the second sub-semiconductor.

The material of the gate insulating film and the first interlayer insulating film may be any one of silicon oxide and silicon nitride.

The organic light emitting member may include a light emitting layer and a sub-layer.

A method of manufacturing an organic light emitting diode display according to an embodiment of the present invention includes forming a first sub-semiconductor on a prepared substrate, forming a gate electrode on the first sub-semiconductor and a gate insulating film, Forming a contact hole in which a first interlayer insulating film is laminated on the gate electrode and exposing a portion of the first sub-semiconductor, a second contact hole formed in the second interlayer insulating film, Forming a second interlayer insulating film including a contact hole for exposing a portion of the first sub-semiconductor and the second sub-semiconductor; forming a second interlayer insulating film on the second interlayer insulating film; A source electrode and a drain electrode connected to the second sub-semiconductor, And forming an organic light emitting member and a common electrode located on the pixel electrode.

The semiconductor includes the first sub-semiconductor and the second sub-semiconductor, and the semiconductor may be formed to include a source region, a drain region, and a channel region.

The source electrode may be connected to the source region, the drain electrode may be connected to the drain region, and the control electrode may overlap the channel region.

The width of the first sub-semiconductor may be greater than the width of the second sub-semiconductor.

The material of the gate insulating film and the first interlayer insulating film may be any one of silicon oxide and silicon nitride.

The organic light emitting member may be formed to include a light emitting layer and a sub-layer.

The semiconductor may be processed to include polycrystalline silicon using a laser.

According to the organic light emitting display as described above, the semiconductors located on different layers are mutually connected, and a channel region of a predetermined length or more can be provided regardless of the area where the semiconductor is formed. Accordingly, the organic light emitting display device having excellent performance regardless of the pixel size is provided, and the display device including the organic light emitting display device can provide a uniform image.

1 is a circuit diagram of a pixel of an organic light emitting display according to an embodiment of the present invention.
2 is a layout diagram of a pixel of an OLED display according to an exemplary embodiment of the present invention.
3 is a sectional view taken along the line III-III in Fig.
4 is a sectional view taken along the line IV-IV in Fig.
5 is a schematic view of an organic light emitting diode of an OLED display according to an embodiment of the present invention.
6 is an equivalent circuit diagram of one pixel of an OLED display according to another embodiment of the present invention.
7 is a schematic view illustrating a plurality of transistors and capacitors of an OLED display according to an embodiment of the present invention.
Fig. 8 is a specific arrangement diagram of Fig. 7. Fig.
9 is a cross-sectional view of the organic light emitting diode display of FIG. 8 taken along line IX-IX.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

1 is an equivalent circuit diagram of an OLED display according to an embodiment of the present invention.

1, the OLED display includes a plurality of signal lines 121, 171, and 172, a plurality of pixels PX connected to the pixels, and arranged in a matrix form, ).

The signal line includes a plurality of gate lines 121 for transmitting gate signals (or scanning signals), a plurality of data lines 171 for transmitting data signals, and a plurality of driving voltage lines and a driving voltage line 172. The gate lines 121 extend substantially in the row direction, are substantially parallel to each other, and the data lines 171 and the driving voltage lines 172 extend in a substantially column direction and are substantially parallel to each other.

Each pixel PX includes a switching transistor Qs, a driving transistor Qd, a storage capacitor Cst and an organic light emitting diode (OLED) LD. .

The switching transistor Qs has a control terminal, an input terminal and an output terminal. The control terminal is connected to the gate line 121 and the input terminal is connected to the data line 171 , And an output terminal thereof is connected to the driving transistor Qd. The switching transistor Qs transfers a data signal applied to the data line 171 to the driving transistor Qd in response to a gate signal applied to the gate line 121. [

The driving transistor Qd also has a control terminal, an input terminal and an output terminal. The control terminal is connected to the switching transistor Qs, the input terminal is connected to the driving voltage line 172, (LD). The driving transistor Qd passes an output current ILD whose magnitude varies according to the voltage applied between the control terminal and the output terminal.

Although not shown, the organic light emitting diode display according to the embodiment of the present invention includes a storage capacitor by a pixel electrode and a sustain electrode overlapping each other with an organic light emitting member interposed therebetween.

The storage capacitor charges the data signal applied to the control terminal of the driving transistor Qd and holds it even after the switching transistor Qs is turned off.

The organic light emitting diode LD has an anode connected to the output terminal of the driving transistor Qd and a cathode connected to the common voltage Vss. The organic light emitting diode LD emits light with different intensity according to the output current ILD of the driving transistor Qd to display an image.

The switching transistor Qs and the driving transistor Qd are n-channel field effect transistors (FETs). However, at least one of the switching transistor Qs and the driving transistor Qd may be a p-channel field-effect transistor. Also, the connection relationship between the transistors Qs and Qd, the capacitor Cst, and the organic light emitting diode LD may be changed.

Hereinafter, the detailed structure of the organic light emitting display device shown in FIG. 1 will be described in detail with reference to FIG. 2 to FIG.

FIG. 2 is a layout diagram of an organic light emitting display according to an embodiment of the present invention, and FIGS. 3 and 4 are cross-sectional views taken along lines III-III and IV-IV ' And FIG. 5 is a schematic view of an organic light emitting device of an organic light emitting diode display according to an embodiment of the present invention.

A blocking layer 111 made of silicon oxide or silicon nitride is formed on the substrate 110 made of transparent glass or the like. The present disclosure shows a single barrier layer 111, but is not limited thereto and may have a bilayer structure.

A plurality of pairs of first and second semiconductors 151a and 151b made of polycrystalline silicon or the like are formed on the blocking layer 111. [ Each of the island-like semiconductor layers 151a and 151b includes a plurality of extrinsic regions including n-type or p-type conductive impurities and at least one intrinsic region substantially containing no conductive impurities.

Semiconductors 151a and 151b made of polycrystalline silicon are formed by forming a hydrogenated amorphous silicon film at 350 ° C. to 450 ° C. by a chemical vapor deposition method and then removing the hydrogen contained in the silicon film by heat treatment at a temperature of 400 ° C. or more And crystallized by a laser to form a polycrystalline silicon film.

In the first semiconductor 151a, the impurity region includes a first source and drain region 153a, 155a and an intermediate region 1535, which are doped with an n-type impurity Are separated from each other. The intrinsic region includes a pair of first channel regions 154a1 and 154a2 located between the impurity regions 153a, 1535 and 155a.

In the second semiconductor 151b, the impurity region includes the second source and drain regions 153b and 155b, which are doped with the p-type impurity and are separated from each other. The intrinsic region includes a second channel region 154b located between the second source and drain regions 153b and 155b.

The impurity region may further include a lightly doped region (not shown) positioned between the channel regions 154a1, 154a2, 154b and the source and drain regions 153a, 155a, 153b, 155b. This lightly doped region can be replaced by an offset region that contains little impurities.

Alternatively, the impurity regions 153a and 155a of the first semiconductor 151a may be doped with a p-type impurity, or the impurity regions 153b and 155b of the second semiconductor 151b may be doped with an n-type impurity. Examples of the p-type conductive impurities include boron (B) and gallium (Ga). Examples of the n-type conductive impurities include phosphorus (P) and arsenic (As).

The second semiconductor 151b may include a first sub-semiconductor 151b1 and a second sub-semiconductor 151b2. The first part semiconductor 151b1 and the second part semiconductor 151b2 are located in different layers and can overlap with each other.

The first sub-semiconductor 151b1 may include one impurity region and some intrinsic regions, and the second sub-semiconductor 151b2 may include another impurity region and a portion of the intrinsic region. At this time, the intrinsic region of the second semiconductor 151b may overlap with the second control electrode 124b.

The intrinsic region of the first sub-semiconductor 151b1 can overlap the second control electrode 124b to be described later. The impurity region of the first sub-semiconductor 151b1 may be connected to the second input electrode 173b or the second output electrode 175b to be described later. The impurity region of the first sub- The impurity region of the second sub-semiconductor 151b2 may be connected to the second output electrode 175b. It goes without saying that they can be mutually exchanged.

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the semiconductor layers 151a and 151b and the blocking layer 111. [

A plurality of gate conductors including a plurality of gate lines 121 including a first control electrode 124a and a plurality of second control electrodes 124b are formed on the gate insulating film 140 gate conductors are formed.

The gate line 121 transmits the gate signal and extends mainly in the horizontal direction. The first control electrode 124a extends upward from the gate line 121 and intersects with the first semiconductor 151a to overlap with the first channel region 154a1 and 154a2. Each of the gate lines 121 may include a wide-area end portion for connection with another layer or an external driving circuit. When the gate driving circuit for generating the gate signal is integrated on the substrate 110, the gate line 121 may extend and be directly connected to the gate driving circuit.

The second control electrode 124b is separated from the gate line 121 and overlaps the second channel region 154b of the second semiconductor 151b. The second control electrode 124b may overlap both the channel region of the first sub-semiconductor 151b1 and the channel region of the second sub-semiconductor 151b2.

The gate conductors 121 and 124b may be formed of any one selected from the group consisting of aluminum-based metals such as aluminum (Al) and aluminum alloys, series metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, molybdenum Such as molybdenum metal, chromium (Cr), tantalum (Ta), and titanium (Ti). However, they may have a multi-film structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having a low resistivity, for example, an aluminum-based metal, a silver-based metal, or a copper-based metal to reduce signal delay and voltage drop. Alternatively, the other conductive film is made of a material having excellent physical, chemical, and electrical contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum metal, chromium, titanium, tantalum, A good example of such a combination is a chromium bottom film, an aluminum (alloy) top film, an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate conductors 121, 124b may be made of a variety of different metals and conductors as well.

The side surfaces of the gate conductors 121 and 124b are inclined with respect to the surface of the substrate 110, and the inclination angle thereof is preferably about 30-80 °.

A first interlayer insulating film 160a is formed on the gate conductors 121 and 124b. The first interlayer insulating film 160a is made of an inorganic insulating material such as silicon nitride or silicon oxide, an organic insulating material, or a low dielectric constant insulating material. The dielectric constant of the low dielectric constant insulating material is preferably 4.0 or less, and examples thereof include a-Si: C: O and a-Si: O: F formed by plasma enhanced chemical vapor deposition (PECVD). The interlayer insulating film 160a may be formed to have photosensitivity among the organic insulating materials, and the surface of the interlayer insulating film 160a may be flat. For example, the gate insulating film and the first interlayer insulating film may be made of the same material, for example, silicon oxide or silicon nitride.

On the next first interlayer insulating film 160a, the second sub-semiconductor 151b2 is located.

The second-section semiconductor 151b2 includes one impurity region and a portion of the intrinsic region as described above. The intrinsic region may overlap with the second control electrode 124b and the intrinsic region may overlap the first control electrode 124b through the first contact hole 156b where the gate insulating film 140 and the first interlayer insulating film 160a are removed, And may be connected to the semiconductor 151b1. At this time, the first sub-semiconductor 151b1, which is partially exposed, may also reveal the intrinsic region.

The impurity region of the second sub-semiconductor 151b2 may be connected to the second input electrode 173b or the second output electrode 175b. For example, when the impurity region of the first sub-semiconductor 151b1 is connected to the second output electrode 175b, the impurity region of the second sub-semiconductor 151b2 may be connected to the second input electrode 173b.

As an example of the present invention, the length of the second sub-semiconductor 151b2 may be longer than the length of the first sub-semiconductor 151b1, but the present invention is not limited thereto. The first sub-semiconductor 151b1 and the second sub- Any shape for connection to the input and output electrodes is possible.

Next, the second interlayer insulating film 160b is located on the second sub-semiconductor 151b2. The second interlayer insulating film 160b is made of an inorganic insulating material such as silicon nitride or silicon oxide, an organic insulating material, or a low dielectric constant insulating material. The dielectric constant of the low dielectric constant insulating material is preferably 4.0 or less, and examples thereof include a-Si: C: O and a-Si: O: F formed by plasma enhanced chemical vapor deposition (PECVD). The interlayer insulating film 160b may be formed to have photosensitivity among the organic insulating materials, and the surface of the second interlayer insulating film 160b may be flat.

A plurality of second contact holes exposing the first sub-semiconductor 151b1 or the second sub-semiconductor 151b2 are formed in the gate insulating film 140, the first interlayer insulating film 160a and the second interlayer insulating film 160b. (163b, 165b) are formed.

Specifically, the contact hole 156b connecting the first sub-semiconductor 151b1 and the second sub-semiconductor 151b2 is located in the gate insulating film 140 and the first interlayer insulating film 160a, and the first sub-semiconductor 151b1 A contact hole 165b is formed in the second interlayer insulating film 160a, the first interlayer insulating film 160b and the gate insulating film 140 so as to expose the contact hole 165b to be connected to the input electrode 173b or the output electrode 175b. A contact hole 163b exposed to connect the impurity region of the second sub-semiconductor 151b2 to the input electrode 173b or the output electrode 175b is located in the second interlayer insulating film 160b.

That is, a plurality of contact holes 163a, 163b, 165a, and 165b that expose the source and drain regions 153a, 153b, 155a, and 155b are formed in the interlayer insulating films 160a and 160b and the gate insulating film 140, respectively.

A plurality of data lines 171, a driving voltage line 172 and first and second output electrodes 175a and 175b are formed on the second interlayer insulating film 160b. A data conductor is formed.

The data line 171 transmits a data signal and extends mainly in the vertical direction and crosses the gate line 121. Each of the data lines 171 includes a plurality of first input electrodes 173a connected to the first source and drain regions 153a through contact holes 163a, And may have a wide end area for connection with the antenna. When the data driving circuit for generating the data signal is integrated on the substrate 110, the data line 171 can be extended and directly connected to the data driving circuit.

The driving voltage line 172 transmits the driving voltage and extends mainly in the vertical direction and crosses the gate line 121. Each of the driving voltage lines 172 includes a plurality of second input electrodes 173b connected to the second source and drain regions 153b through contact holes 163b.

The first output electrode 175a is separated from the data line 171 and the driving voltage line 172. [ The first output electrode 175a is connected to the first source and drain region 155a through the contact hole 165a and is connected to the second control electrode 124b through the contact hole 164.

The second output electrode 175b is separated from the data line 171, the driving voltage line 172 and the first output electrode 175a and connected to the second source and drain regions 155b through the contact hole 165b. .

The data conductors 171, 172, 175a, and 175b are preferably made of refractory metals such as molybdenum, chromium, tantalum, and titanium or their alloys, and may be formed of a conductive film (not shown) Film structure composed of a film (not shown). Examples of the multilayer structure include a double film of a chromium or molybdenum (alloy) lower film and an aluminum (alloy) upper film, a molybdenum (alloy) lower film, an aluminum (alloy) intermediate film and a molybdenum (alloy) upper film. However, the data conductors 171, 172, 175a, 175b may be made of a variety of different metals and conductors as well.

It is preferable that the data conductors 171, 172, 175a, and 175b are inclined at an angle of about 30-80 degrees with respect to the substrate 110 in the same manner as the gate conductors 121 and 124b.

A passivation layer 180 is formed on the data conductors 171, 172, 175a, and 175b. The protection film 180 is made of an inorganic material, an organic material, or a low dielectric constant insulating material.

The protective film 180 is formed with a plurality of contact holes 185 for exposing the second output electrode 175b. A plurality of contact holes (not shown) may be formed in the passivation layer 180 to expose the ends of the data lines 171. The passivation layer 180 and the interlayer insulating layer 160 may be formed with a plurality of contact holes A plurality of contact holes (not shown) may be formed.

A plurality of pixel electrodes 191 are formed on the passivation layer 180. The pixel electrode 191 is physically and electrically connected to the second output electrode 175b through the contact hole 185 and is made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, Can be.

 A plurality of contact assistants (not shown) or a connecting member (not shown) may be formed on the passivation layer 180. The gate lines 121 and the data lines 171, Lt; / RTI >

A partition 360 is formed on the passivation layer 180. The barrier rib 360 surrounds the periphery of the pixel electrode 191 and defines an opening and is made of an organic insulating material or an inorganic insulating material. The barrier ribs 360 may also be made of a photosensitizer containing a black pigment. In this case, the barrier ribs 360 serve as light shielding members, and the forming process is simple.

An organic light emitting member 370 is formed on the pixel electrode 191 surrounded by the barrier ribs 360. The organic light emitting member 370 is mostly located in a region surrounded by the barrier ribs 360, but is also located on the barrier ribs 360 and other pixel regions. The organic light emitting member 370 is made of an organic material that emits light of any one of primary colors such as red, green, and blue.

The organic light emitting member 370 has a multilayer structure including an auxiliary layer for improving the light emission efficiency of the light emitting layer (EML) in addition to the light emitting layer (EML) as shown in FIG. An electron transport layer (ETL) and a hole transport layer (HTL) for balancing electrons and holes and an electron injecting layer for enhancing the injection of electrons and holes are provided in the sub- (EIL) and a hole injecting layer (HIL). The sub-layer can be omitted.

A plurality of common electrodes 270 are disposed on the organic light emitting member 370.

The common electrode 270 is made of a transparent conductive material, such as ITO or IZO, or a reflective metal including Ca, Ba, Mg, Al, and silver.

In this organic light emitting display device, the first semiconductor 151a, the first control electrode 124a connected to the gate line 121, the first input electrode 173a connected to the data line 171, The output electrode 175a constitutes a switching thin film transistor Qs and the channel of the switching thin film transistor Qs is formed in the channel regions 154a1 154a2 of the first semiconductor 151a. A second control electrode 124b connected to the first output electrode 175a, a second input electrode 173b connected to the driving voltage line 172, and a pixel electrode 191 connected to the second semiconductor 151b, the first output electrode 175a, The second output electrode 175b is a driving TFT Qd and the channel of the driving thin film transistor Qd is formed in a channel region 154b of the second semiconductor 151b. The pixel electrode 191, the organic light emitting member 370 and the common electrode 270 form an organic light emitting diode. The pixel electrode 191 is an anode, the common electrode 270 is a cathode, The electrode 191 serves as the cathode, and the common electrode 270 serves as the anode.

The switching thin film transistor Qs transfers the data signal of the data line 171 in response to the gate signal of the gate line 121. [ When receiving the data signal, the driving thin film transistor Qd passes a current of a magnitude depending on the voltage difference between the second control electrode 124b and the second input electrode 173b. The voltage difference between the second control electrode 124b and the second input electrode 173b is also maintained after the storage capacitor Cst is charged and the switching thin film transistor Qs is turned off. The organic light emitting diode emits light by varying the intensity according to the magnitude of the current flowing through the driving thin film transistor Qd, thereby displaying an image.

As described above, the organic light emitting member 370 has a multi-layer structure including a light emitting layer as well as various sub-layers. Therefore, in addition to the region surrounded by the barrier ribs 360, at least one layer of the light emitting layer or various sublayers may be present on the barrier ribs 360 (not shown).

According to the organic light emitting display device described above, even if the area in which the semiconductor can be positioned is limited, the predetermined channel region length required by the display device can be satisfied by the semiconductor which is located in a plurality of layers and interconnected. Therefore, it is possible to provide a display device with excellent performance even when the pixel size is small.

The switching thin film transistor and the driving thin film transistor have been described above. Hereinafter, the organic light emitting display according to another embodiment of the present invention including the switching thin film transistor and the driving thin film transistor will be described in detail with reference to FIG. 6 to FIG.

6 is an equivalent circuit diagram of one pixel of an OLED display according to an exemplary embodiment of the present invention.

6, one pixel 1 of an OLED display according to another embodiment of the present invention includes a plurality of signal lines 121, 122, 123, 124, 128, 171, 172, A plurality of transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and an organic light emitting diode (OLED)

The transistor includes a driving thin film transistor T1, a switching thin film transistor T2, a compensation transistor T3, an initialization transistor T4, an operation control transistor T5, a light emission control transistor T6 And a bypass transistor T7.

The signal line includes a scan line 121 for transmitting a scan signal Sn, a previous scan line 122 for transferring a previous scan signal Sn-1 to the initialization transistor T4, an operation control transistor T5, An initializing voltage line 124 for transferring an initializing voltage Vint for initializing the driving transistor Tl and an initializing voltage line 124 for transferring the light emitting control signal En to the bypass thin film transistor T7, A bypass control line 128 for transmitting a bypass signal BP, a data line 171 for crossing the scan line 121 and transmitting the data signal Dm, a drive voltage ELVDD, And a driving voltage line 172 formed substantially in parallel with the pixel electrodes 171 and 171.

The gate electrode G1 of the driving transistor T1 is connected to one end Cst1 of the storage capacitor Cst and the source electrode S1 of the driving transistor Tl is connected to the driving voltage line Vcc via the operation control transistor T5. And the drain electrode D1 of the driving transistor T1 is electrically connected to the anode of the organic light emitting diode OLED via the emission control transistor T6. The driving transistor Tl receives the data signal Dm according to the switching operation of the switching transistor T2 and supplies the driving current Id to the organic light emitting diode OLED.

The gate electrode G2 of the switching transistor T2 is connected to the scan line 121. The source electrode S2 of the switching transistor T2 is connected to the data line 171, The drain electrode D2 of the driving transistor T1 is connected to the source electrode S1 of the driving transistor T1 and is connected to the driving voltage line 172 via the operation control transistor T5. The switching transistor T2 is turned on in accordance with the scan signal Sn transmitted through the scan line 121 to transfer the data signal Dm transferred to the data line 171 to the source electrode of the driving transistor T1 .

The gate electrode G3 of the compensating transistor T3 is directly connected to the scan line 121 and the source electrode S3 of the compensating transistor T3 is connected to the drain electrode D1 of the driving transistor T1 The drain electrode D3 of the compensating transistor T3 is connected to the one end Cst1 of the storage capacitor Cst1 and the drain electrode D2 of the initializing transistor T3 through the emission control transistor T6 and to the anode of the organic light emitting diode OLED, The drain electrode D4 of the transistor T4 and the gate electrode G1 of the driving transistor Tl. The compensating transistor T3 is turned on in response to the scan signal Sn transmitted through the scan line 121 to connect the gate electrode G1 and the drain electrode D1 of the driving transistor T1 to each other, T1).

The source electrode S4 of the initializing transistor T4 is connected to the initializing voltage line 124 and the initializing transistor T4 is connected to the initializing transistor T4. The gate electrode G4 of the initializing transistor T4 is connected to the previous scan line 122, The drain electrode D4 of the storage capacitor Cst is connected together to one end Cst1 of the storage capacitor Cst and the drain electrode D3 of the compensating transistor T3 and the gate electrode G1 of the driving transistor Tl. The initialization transistor T4 is turned on according to the previous scan signal Sn-1 transferred through the previous scan line 122 to transfer the initialization voltage Vint to the gate electrode G1 of the drive transistor Tl An initializing operation for initializing the voltage of the gate electrode G1 of the driving transistor T1 is performed.

The gate electrode G5 of the operation control transistor T5 is connected to the emission control line 123 and the source electrode S5 of the operation control transistor T5 is connected to the drive voltage line 172, The drain electrode D5 of the switching transistor T5 is connected to the source electrode S1 of the driving transistor T1 and the drain electrode S2 of the switching transistor T2.

The gate electrode G6 of the emission control transistor T6 is connected to the emission control line 123 and the source electrode S6 of the emission control transistor T6 is connected to the drain electrode D1 of the driving transistor T1, And the drain electrode D6 of the emission control transistor T6 is electrically connected to the anode of the organic light emitting diode OLED. The operation control transistor T5 and the emission control transistor T6 are simultaneously turned on in accordance with the emission control signal En received through the emission control line 123 so that the driving voltage ELVDD is applied to the organic light emitting diode OLED And the light emission current Ioled flows through the organic light emitting diode OLED.

The gate electrode G7 of the bypass thin film transistor T7 is connected to the bypass control line 128 and the source electrode S7 of the bypass thin film transistor T7 is connected to the drain electrode of the emission control thin film transistor T6. The drain electrode D7 of the bypass thin film transistor T7 is connected to the initialization voltage line 124 and the source electrode S4 of the initialization thin film transistor T4. Respectively.

The other end Cst2 of the storage capacitor Cst is connected to the driving voltage line 172 and the cathode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Accordingly, the organic light emitting diode OLED receives the light emission current Ioled from the driving transistor T1 and emits light to display an image.

Hereinafter, a detailed operation of one pixel of the OLED display according to an embodiment of the present invention will be described in detail.

First, the previous scan signal Sn-1 of a low level is supplied through the previous scan line 122 during the initialization period. Then, the initializing transistor T4 is turned on in response to the previous low level scan signal Sn-1, and the initializing voltage Vint is driven from the initializing voltage line 124 through the initializing transistor T4. Is connected to the gate electrode of the transistor T1 and the driving transistor T1 is initialized by the initializing voltage Vint.

Thereafter, a low level scan signal Sn is supplied through the scan line 121 during a data programming period. Then, the switching transistor T2 and the compensation transistor T3 are turned on in response to the low level scan signal Sn.

At this time, the driving transistor Tl is diode-connected by the turned-on compensation transistor T3, and is biased in the forward direction.

Then, the compensation voltage Dm + Vth, which is decreased by the threshold voltage (Vth) of the driving transistor Tl in the data signal Dm supplied from the data line 171, Is applied to the gate electrode of the transistor T1.

The drive voltage ELVDD and the compensation voltage Dm + Vth are applied to both ends of the storage capacitor Cst and the charge corresponding to the voltage difference between both ends is stored in the storage capacitor Cst. Thereafter, the emission control signal En supplied from the emission control line 123 during the emission period is changed from the high level to the low level. Then, the operation control transistor T5 and the emission control transistor T6 are turned on by the low level emission control signal En during the emission period.

A driving current Id corresponding to the voltage difference between the voltage of the gate electrode of the driving transistor Tl and the driving voltage ELVDD is generated and the driving current Id is supplied to the organic light emitting diode OLED. The gate-source voltage Vgs of the driving transistor Tl is maintained at '(Dm + Vth) -ELVDD' by the storage capacitor Cst during the light emitting period, and according to the current-voltage relationship of the driving transistor Tl, The driving current Id is proportional to the square of the value obtained by subtracting the threshold voltage from the source-gate voltage '(Dm-ELVDD) ² '. Therefore, the driving current Id is determined regardless of the threshold voltage Vth of the driving transistor Tl.

At this time, the bypass transistor T7 receives the bypass signal BP from the bypass control line 128. The bypass signal BP is a voltage of a predetermined level that can always turn off the bypass transistor T7 and the bypass transistor T7 receives the voltage of the transistor off level to the gate electrode G7, The transistor T7 is always turned off and a part of the driving current Id is allowed to pass through the bypass transistor T7 with the bypass current Ibp in the off state.

Accordingly, the light emission current Ioled of the organic light emitting diode, which is reduced by the amount of the bypass current Ibp exiting through the bypass transistor T7 from the drive current Id when the drive current for displaying the black image flows, The minimum amount of current is obtained at a level that can reliably express the black image. Accordingly, it is possible to realize an accurate black luminance image using the bypass transistor T7, thereby improving the contrast ratio.

The detailed structure of the pixel of the organic light emitting display device shown in FIG. 6 will now be described in detail with reference to FIGS. 7 to 9 with reference to FIG. 6. FIG.

FIG. 7 is a schematic view illustrating a plurality of transistors and capacitors of an OLED display according to another embodiment of the present invention, FIG. 8 is a specific layout diagram of FIG. 7, and FIG. 9 is a cross- IX-IX. ≪ / RTI >

2, the organic light emitting display according to an exemplary embodiment of the present invention includes a scan signal Sn, a previous scan signal Sn-1, a light emission control signal En, and a bypass signal BP. A light emitting control line 123 and a bypass control line 128 which are formed along the row direction and are connected to the scan line 121, the previous scan line 122, A data line 171 and a driving voltage line 172 which intersect the emission control line 123 and the bypass control line 128 and apply a data signal Dm and a driving voltage ELVDD to the pixel, . The initializing voltage Vint is transferred from the organic light emitting diode OLED through the initializing voltage line 124 to the driving transistor Tl through the initializing transistor T4.

The pixel includes a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, an operation control transistor T5, a light emission control transistor T6, a bypass transistor T7, A capacitor Cst, and an organic light emitting diode (OLED).

The driving transistor T1, the switching transistor T2, the compensating transistor T3, the initializing transistor T4, the operation control transistor T5, the emission control transistor T6 and the bypass transistor T7 are connected to the semiconductor layer 131, And the semiconductor layer 131 is formed by bending in various shapes. The semiconductor layer 131 may be formed of polysilicon or an oxide semiconductor. The oxide semiconductor may be at least one selected from the group consisting of Ti, Hf, Zr, Al, Ta, Ge, Zn, Ga, (Zn-In-O), zinc-tin oxide (Zn-Sn-Zn), indium- Zr-O) indium-gallium oxide (In-Ga-O), indium-tin oxide (In-Sn-O), indium-zirconium oxide Zr-Ga-O), indium-aluminum oxide (In-Al-O), indium-zirconium-tin oxide (In- In-Zn-Al-O, indium-tin-aluminum oxide, indium-aluminum-gallium oxide, indium-tantalum oxide (In-Ta-O), indium-tantalum-gallium oxide (In-Ta-Zn-O), indium-tantalum- -Ga-O), indium Germanium-gallium oxide (In-Ge-Zn-O), indium-germanium-tin oxide (In-Ge-Sn-O) In-Ge-Ga-O), titanium-indium-zinc oxide (Ti-In-Zn-O), and hafnium-indium-zinc oxide (Hf-In-Zn-O). In the case where the semiconductor layer 131 is made of an oxide semiconductor, a separate protective layer may be added to protect the oxide semiconductor, which is vulnerable to an external environment such as a high temperature.

The semiconductor layer 131 may include a channel region doped with an N-type impurity or a P-type impurity, a source region formed on both sides of the channel region, doped with a doping impurity doped in the channel region, Region and a drain region.

Hereinafter, a specific planar structure of the OLED display according to an embodiment of the present invention will be described in detail with reference to FIGS. 7 and 8, and a detailed sectional structure will be described in detail with reference to FIG.

7 and 8, a pixel 1 of an organic light emitting diode display according to an embodiment of the present invention includes a driving transistor T1, a switching transistor T2, a compensating transistor T3, A transistor T4, an operation control transistor T5, a light emission control transistor T6, a bypass transistor T7, a storage capacitor Cst, and an organic light emitting diode OLED. T3, T4, T5, T6 and T7 are formed along the semiconductor layer 131. The semiconductor layer 131 includes a driving semiconductor layer 131a formed on the driving transistor T1, The reset semiconductor layer 131d formed in the initialization transistor T4 and the operation control transistor T5 formed in the operation control transistor T5 are formed in the switching semiconductor layer 131b, the compensating semiconductor layer 131c formed in the compensating transistor T3, The semiconductor layer 131e, the emission control transistor T6 It includes a bypass semiconductor layer (131g) that is formed in the light emitting control semiconductor layer (131f), and by-pass thin film transistor (T7). In particular, according to one embodiment of the present invention, the driving semiconductor layer 131a is formed in a double structure located in a different layer. This has been described in detail with reference to FIG. 4, and description of the same configuration is omitted.

The driving transistor Tl includes a driving semiconductor layer 131a, a driving gate electrode 125a, a driving source electrode 176a, and a driving drain electrode 177a.

The driving semiconductor layer 131a is curved and may have a meander shape or a zigzag shape. By forming the drive semiconductor layer 131a having a curved shape in this way, the drive semiconductor layer 131a can be formed in a narrow space. Therefore, since the driving channel region 131a1 of the driving semiconductor layer 131a can be formed long, the driving range of the gate voltage applied to the driving gate electrode 125a is widened. Therefore, since the driving range of the gate voltage is wide, the gradation of the light emitted from the organic light emitting diode OLED can be finely controlled by changing the size of the gate voltage. As a result, the resolution of the organic light emitting display device can be increased, Can be improved.

The driving source electrode 176a corresponds to a driving source region 176a doped with an impurity in the driving semiconductor layer 131a and the driving drain electrode 177a corresponds to a driving drain region 177a. At this time, the driving source region 176a and the driving drain region 177a may be located in different layers. The driving gate electrode 125a overlaps the driving semiconductor layer 131a and the driving gate electrode 125a overlaps the scanning line 121, the previous scanning line 122, the emission control line 123, the switching gate electrode 125b The compensation gate electrode 125c, the initialization gate electrode 125d, the operation control gate electrode 125e and the light emission control gate electrode 125f.

The switching transistor T2 includes a switching semiconductor layer 131b, a switching gate electrode 125b, a switching source electrode 176b, and a switching drain electrode 177b. The switching gate electrode 125b is a part of the scan line 121.

The switching source electrode 176b which is a part of the data line 171 is connected to the switching source region 132b doped with the impurity in the switching semiconductor layer 131b and the switching drain electrode 177b is connected to the switching semiconductor layer 131b And corresponds to the switching-drain region 177b doped with the impurity.

The compensating transistor T3 includes a compensating semiconductor layer 131c, a compensating gate electrode 125c, a compensating source electrode 176c and a compensating drain electrode 177c and the compensating source electrode 176c comprises a compensating semiconductor layer 131c. The compensating drain electrode 177c corresponds to the compensating drain region 177c doped with the impurity, and the compensating drain electrode 177c corresponds to the compensating drain region 177c doped with the impurity.

The initializing transistor T4 includes an initializing semiconductor layer 131d, an initializing gate electrode 125d, an initializing source electrode 176d, and an initializing drain electrode 177d. The initializing source electrode 176d corresponds to the initialization source region 176d doped with the impurity and the initializing drain electrode 177d corresponds to the initializing drain region 177d doped with the impurity.

The operation control transistor T5 includes an operation control semiconductor layer 131e, an operation control gate electrode 125e, an operation control source electrode 176e, and an operation control drain electrode 177e. The operation control source electrode 176e which is a part of the driving voltage line 172 is connected to the operation control semiconductor layer 131e and the operation control drain electrode 177e is connected to the operation control drain Area 177e.

The emission control transistor T6 includes the emission control semiconductor layer 131f, the emission control gate electrode 125f, the emission control source electrode 176f and the emission control drain electrode 177f. The emission control source electrode 176f corresponds to the emission control source region 176f doped with the impurity in the emission control semiconductor layer 131f and the emission control drain electrode 177f is connected to the emission control semiconductor layer 131f .

The bypass thin film transistor T7 includes a bypass semiconductor layer 131g, a bypass gate electrode 125g, a bypass source electrode 176g, and a bypass drain electrode 177g. The bypass source electrode 176g corresponds to the bypass source region 176g doped with the impurity in the bypass semiconductor layer 131g and the bypass drain electrode 177g corresponds to the impurity doped in the bypass semiconductor layer 131g. The bypass drain region 177g. The bypass source electrode 176g is directly connected to the emission control drain region 133f.

One end of the driving semiconductor layer 131a of the driving transistor T1 is connected to the switching semiconductor layer 131b and the operation control semiconductor layer 131e and the other end of the driving semiconductor layer 131a is connected to the compensating semiconductor layer 131c, Emitting control semiconductor layer 131f. The driving source electrode 176a is connected to the switching drain electrode 177b and the operation control drain electrode 177e and the driving drain electrode 177a is connected to the compensation source electrode 176c and the emission control source electrode 176f do.

The storage capacitor Cst includes a first storage capacitor plate 125a and a second storage capacitor plate 126 disposed with a second gate insulating film 142 interposed therebetween. The first storage capacitor plate 125a is the driving gate electrode 125a and the second gate insulating film 143 is the dielectric and the voltage between the charge stored in the storage capacitor Cst and the capacitor plates 125a and 126 The storage capacitance is determined.

The connecting member 174 is formed on the same layer in parallel with the data line 171 and connects the driving gate electrode 125a and the compensating drain electrode 177c of the compensating thin film transistor T3 to each other. The first storage capacitor plate 125a as the driving gate electrode 125a is connected to the connecting member 174 and the compensating drain electrode 177c is connected to the connecting member 174 in the compensating semiconductor layer 131c.

The storage capacitor Cst stores the storage capacitance corresponding to the difference between the driving voltage ELVDD transferred to the second storage capacitor plate 126 through the driving voltage line 172 and the gate voltage of the driving gate electrode 125a do.

On the other hand, the switching transistor T2 is used as a switching element for selecting a pixel to emit light. The switching gate electrode 125b is connected to the scan line 121. The switching source electrode 176b is connected to the data line 171. The switching drain electrode 177b is connected to the driving transistor T1, (T5). The emission control drain electrode 177f of the emission control transistor T6 is directly connected to the pixel electrode 191 of the organic light emitting diode 70. [

Hereinafter, the structure of the OLED display according to another embodiment of the present invention will be described in detail with reference to FIG. Hereinafter, the driving transistor Tl will be mainly described, and the description of the other transistors described above may be omitted. In particular, since the operation control transistor T5 is substantially the same as the lamination structure of the emission control transistor T6, a detailed description thereof will be omitted.

A buffer layer 120 is formed on the substrate 110. The substrate 110 is formed of an insulating substrate made of glass, quartz, ceramics, plastic, or the like.

On the buffer layer 120, a driving semiconductor layer 131a, a switching semiconductor layer 131b, a compensating semiconductor layer 131c, an initializing semiconductor layer 131d, an operation controlling semiconductor layer 131e, a light emitting controlling semiconductor layer 131f, Pass semiconductor layer 131g is formed.

The driving semiconductor layer 131a includes a driving source region 176a and a driving drain region 177a located at both ends with a driving channel region 131a1 and a driving channel region 131a1 interposed therebetween, 131b includes a switching source region 132b and a switching drain region 177b facing each other with a switching channel region 131b1 and a switching channel region 131b1 interposed therebetween. The compensation semiconductor layer 131c includes a compensation channel region 131c, a compensation source region 176c and a compensation drain region 177c. The initialization semiconductor layer 131d includes an initialization channel region 131d, The emission control semiconductor layer 131f includes an emission control channel region 131f1, an emission control source region 176f and an emission control drain region 133f, Pass semiconductor layer 131g includes a bypass channel region 131g, a bypass source region 176g, and a bypass drain region 177g.

A portion of the driving semiconductor layer 131a, the switching semiconductor layer 131b, the compensating semiconductor layer 131c, the initialization semiconductor layer 131d, the operation control semiconductor layer 131e, the emission control semiconductor layer 131f, And a gate insulating layer 140 is formed on the gate insulating layer 131g. A scan line 121 including a switching gate electrode 125b and a compensation gate electrode 125c, a previous scan line 122 including an initialization gate electrode 125d, and an operation control gate electrode 125e And the bypass line 128 including the light emission control line 123, the driving gate electrode (first storage capacitor plate) 125a and the bypass gate electrode 125g including the light emission control gate electrode 125f and the light emission control gate electrode 125f, The gate wirings 121, 122, 123, 125a, 125b, 125c, 125d, 125e, 125f, 125g and 128 are formed.

A first interlayer insulating film 160a is formed on the gate wirings 121, 122, 123, 125a, 125b, 125c, 125d, 125e, 125f, 125g, 128 and the gate insulating film 140. [ A gate insulating film 14 and first interlayer insulating film (160a) is formed of silicon nitride (SiNx) or silicon oxide (SiO ₂₎ or the like.

On the first interlayer insulating film 160, a channel region and an impurity region extending from the driving semiconductor layer 131a are located. The channel region may overlap with the driving gate electrode 125a and a part of the semiconductor layer 131a located in the first interlayer insulating film 160 and a portion of the semiconductor layer 131a located under the gate insulating film 140 The semiconductor layer 131a may be connected.

The second interlayer insulating film 160b is disposed on the extended channel region and the impurity region of the driving semiconductor layer 131a and then the data line 171 including the switching source electrode 176b, the driving voltage line 172, The data lines 171, 172, 174, 176b, 177f, and 124 including the data line 174, the emission control drain electrode 177f, and the initialization voltage line 124 are formed.

The switching source electrode 176b is connected to the switching contact member 22 through the switching upper contact hole 62 formed in the interlayer insulating film 160. One end of the connecting member 174 is connected to the driving electrode And the other end of the connecting member 174 is connected to the compensating contact member 23 through the compensating upper contact hole 63 formed in the interlayer insulating film 160 The initialization voltage line 24 is connected to the initialization contact member 24 through the initialized upper contact hole 64 formed in the interlayer insulation film 160 and the drive voltage line 172 is connected to the initialization contact member 24 via the initialization contact line 24 formed in the interlayer insulation film 160 And the emission control drain electrode 177f is connected through the upper contact hole 65 to the emission control contact member 25 via the emission control upper contact hole 66 formed in the interlayer insulating film 160 26).

A protective film 180 covering the data lines 171, 172, 174, 176b, 177f and 124 is formed on the interlayer insulating film 160. A pixel electrode 191 is formed on the protective film 180. [ The pixel electrode 191 is connected to the pixel electrode 191 through a contact hole 81 formed in the passivation layer 180. The initialization voltage line 124 is connected to the pixel electrode 191 through a contact hole 82 formed in the passivation layer 180. [ (191).

A barrier rib 350 is formed on the edge of the pixel electrode 191 and the passivation layer 180. The barrier rib 350 has a barrier opening 351 for exposing the pixel electrode 191. The barrier rib 350 may be made of a resin such as polyacrylates resin and polyimide, or a silica-based inorganic material.

An organic light emitting layer 370 is formed on the pixel electrode 191 exposed through the barrier rib opening 351 and a common electrode 270 is formed on the organic light emitting layer 370. Thus, the organic light emitting diode 70 including the pixel electrode 191, the organic light emitting layer 370, and the common electrode 270 is formed.

Here, the pixel electrode 191 is an anode which is a hole injection electrode, and the common electrode 270 is a cathode which is an electron injection electrode. However, the embodiment of the present invention is not necessarily limited thereto, and the pixel electrode 191 may be a cathode and the common electrode 270 may be an anode according to a driving method of an OLED display. Holes and electrons are injected from the pixel electrode 191 and the common electrode 270 into the organic light emitting layer 370 and light is emitted when an exciton formed by the injected holes and electrons falls from the excited state to the ground state .

The organic light emitting layer 370 is made of a low molecular organic material or a polymer organic material such as PEDOT (Poly 3,4-ethylenedioxythiophene). The organic light emitting layer 370 includes a light emitting layer, a hole injection layer (HIL), a hole transporting layer (HTL), an electron transporting layer (ETL), and an electron injection layer , EIL). ≪ / RTI > When both are included, a hole injection layer is disposed on the pixel electrode 191 as an anode, and a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are sequentially stacked thereon.

The organic emission layer 370 may include a red organic emission layer that emits red light, a green organic emission layer that emits green light, and a blue organic emission layer that emits blue light. The red organic emission layer, the green organic emission layer, , A green pixel and a blue pixel to realize a color image.

The organic light emitting layer 370 is formed by laminating a red organic light emitting layer, a green organic light emitting layer and a blue organic light emitting layer all together in a red pixel, a green pixel, and a blue pixel, and forms a red color filter, a green color filter, So that a color image can be realized. As another example, a color image may be realized by forming a white organic light emitting layer emitting white light in both red pixels, green pixels, and blue pixels, and forming red, green, and blue color filters, respectively, for each pixel. When a color image is realized using a white organic light emitting layer and a color filter, a deposition mask for depositing a red organic light emitting layer, a green organic light emitting layer, and a blue organic light emitting layer on respective individual pixels, that is, red pixel, green pixel and blue pixel You do not have to do.

The white organic light emitting layer described in other examples may be formed of one organic light emitting layer, and may include a structure in which a plurality of organic light emitting layers are stacked to emit white light. For example, a configuration in which at least one yellow organic light emitting layer and at least one blue organic light emitting layer are combined to enable white light emission, a configuration in which at least one cyan organic light emitting layer and at least one red organic light emitting layer are combined to enable white light emission, And a structure in which at least one magenta organic light emitting layer and at least one green organic light emitting layer are combined to enable white light emission.

A sealing member (not shown) for protecting the organic light emitting diode 70 may be formed on the common electrode 270. The sealing member may be sealed to the substrate 110 by a sealant and may be formed of glass, quartz, ceramics, Plastic, metal, and the like. On the other hand, an inorganic film and an organic film may be deposited on the common electrode 270 without using a sealant to form a thin film sealing layer.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

110: substrate 111: blocking layer
121, 124b: gate conductor 124a, 124b: control electrode
140: gate insulating films 151a and 151b: semiconductor
160a and 160b: an interlayer insulating film 171: a data line
172: driving voltage line 180: protective film
191: pixel electrode 270: common electrode
360: barrier rib 370: organic light emitting member

Claims (14)

Board,
A first sub-semiconductor disposed on the substrate,
A gate insulating film disposed on the first sub-semiconductor,
A gate electrode disposed on the gate insulating film,
A first interlayer insulating film located on the gate electrode,
A second sub-semiconductor layer disposed on the first interlayer insulating layer and connected to the first sub-
A source electrode and a drain electrode which are located on the second sub-semiconductor and are connected to the first sub-semiconductor and the second sub-semiconductor,
A pixel electrode electrically connected to the drain electrode,
An organic light emitting member disposed on the pixel electrode, and
And a common electrode disposed on the organic light emitting member. The method of claim 1,
Wherein the semiconductor includes the first sub-semiconductor and the second sub-semiconductor,
Wherein the semiconductor includes a source region, a drain region, and a channel region. 3. The method of claim 2,
Wherein the source electrode is connected to the source region and the drain electrode is connected to the drain region,
And the gate electrode overlaps with the channel region. The method of claim 1,
Wherein a width of the first sub-semiconductor is greater than a width of the second sub-semiconductor. The method of claim 1,
And a second interlayer insulating film disposed on the second sub-semiconductor. The method of claim 5,
Wherein the gate insulating film and the first interlayer insulating film are made of silicon oxide or silicon nitride. The method of claim 1,
Wherein the organic light emitting member includes a light emitting layer and a sub-layer. Forming a first sub-semiconductor on the prepared substrate,
Depositing a gate insulating film on the first sub-semiconductor and forming a gate electrode on the gate insulating film,
Laminating a first interlayer insulating film on the gate electrode and forming a first contact hole exposing a part of the first sub-semiconductor,
Forming a second sub-semiconductor, which is connected to the first sub-semiconductor through the first contact hole, and which is located on the first inter-layer insulating film;
Forming a second interlayer insulating film including a second contact hole exposing a part of the first sub-semiconductor and the second sub-semiconductor,
Forming a source electrode and a drain electrode on the second interlayer insulating film and connected to the first sub-semiconductor and the second sub-semiconductor through the second contact hole,
Forming a pixel electrode electrically connected to the drain electrode, and
And forming an organic light emitting member and a common electrode on the pixel electrode. 9. The method of claim 8,
Wherein the semiconductor includes the first sub-semiconductor and the second sub-semiconductor,
Wherein the semiconductor is formed to include a source region, a drain region, and a channel region. The method of claim 9,
Wherein the source electrode is connected to the source region and the drain electrode is connected to the drain region,
Wherein the gate electrode is formed to overlap with the channel region. The method of claim 9,
Wherein the width of the first sub-semiconductor is greater than the width of the second sub-semiconductor. The method of claim 9,
Wherein the gate insulating film and the first interlayer insulating film are made of silicon oxide or silicon nitride. The method of claim 9,
Wherein the organic light emitting member is formed to include a light emitting layer and a sub-layer. The method of claim 9,
Wherein the semiconductor is processed to include polycrystalline silicon using a laser.

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