KR20150048361A - Thin film transistor, method of manufacturing a thin film transistor, and organic light emitting display device having the same - Google Patents

Abstract

A thin film transistor may include a semiconductor layer which is formed on a substrate and includes a poly silicon layer, a metallic etch stopper which is located to cover at least part of the upper side of the source/drain region of the semiconductor layer and at least part of the lateral side of the source/drain region, a gate electrode which is located to correspond to the channel region of the semiconductor layer, an gate insulating layer which is located between the gate electrode and the semiconductor layer to insulate the gate electrode and the semiconductor layer, and a source/drain electrode which is electrically connected to the source/drain region of the semiconductor layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor (TFT), a thin film transistor, and an organic light emitting diode (OLED)

The present invention relates to a display device, and more particularly, to a method of manufacturing a thin film transistor, a thin film transistor, and an organic light emitting display including the same.

2. Description of the Related Art As organic light emitting display devices (OLEDs) have become larger in recent years, semiconductor layers including a channel region have been actively studied to be formed into a poly-silicon layer favorable for large-area substrate processing It is progressing. However, when a large area display device is implemented, the uniformity of the polycrystalline silicon layer is lowered, the contact resistance with the source / drain electrodes increases, and the leakage current increases.

As one method for solving the above problem, the thickness of the semiconductor layer including the channel region may be reduced. However, in this case, there is a problem that contact failure occurs in the channel region due to loss (etching) of the semiconductor layer when forming the contact hole for forming the source / drain electrode.

It is an object of the present invention to provide a thin film transistor including an etch stopper of a metal material covering the top and sides of the source / drain region.

Another object of the present invention is to provide a method of manufacturing a thin film transistor including an etch stopper of a metal material covering upper and side surfaces of a source / drain region.

It is still another object of the present invention to provide an organic light emitting diode display including the thin film transistor and simultaneously forming the etch stopper and the storage capacitor lower electrode.

It is to be understood, however, that the present invention is not limited to the above-described embodiments and various modifications may be made without departing from the spirit and scope of the invention.

According to an aspect of the present invention, there is provided a thin film transistor comprising: a semiconductor layer formed on a substrate and including a polycrystalline silicon layer; at least a portion of a top surface of a source / And an etch stopper of a metal material positioned to cover at least a part of a side surface of the source / drain region, a gate electrode corresponding to a channel region of the semiconductor layer, And a source / drain electrode electrically connected to the gate insulating layer and the source / drain region of the semiconductor layer, respectively.

According to an embodiment, a buffer layer may be further formed on the substrate.

According to one embodiment, the etch stopper may be formed by patterning by a photolithography process.

According to an embodiment, the semiconductor layer and the etch stopper may be heat-treated after the patterning.

According to an embodiment, each of the source / drain electrodes may be in contact with the upper surface of the etch stopper.

According to an embodiment, an oxide layer formed between the source / drain region and the etch stopper may be further included.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: forming a semiconductor layer including a polycrystalline silicon layer on a substrate; forming a source / Forming a gate insulating film on the semiconductor layer and the etch stopper after forming an etch stopper covering at least a part of an upper surface of the semiconductor substrate and at least a part of a side surface of the source / A gate electrode corresponding to the channel region can be formed. Forming an interlayer insulating film over the entire surface of the substrate, and forming source / drain electrodes to be electrically connected to the source / drain regions.

According to an embodiment, a buffer layer may be formed on the substrate.

According to an embodiment, after forming the etch stopper, the semiconductor layer and the etch stopper may be subjected to a heat treatment.

According to one embodiment, the etch stopper may be formed by patterning by a photolithography process.

According to an embodiment, each of the source / drain electrodes may be in contact with the upper surface of the etch stopper.

According to one embodiment, the step of forming the gate insulating film may include removing the oxide film layer formed on the channel region of the semiconductor layer, and then coating the gate insulating film over the entire surface of the substrate.

According to an aspect of the present invention, there is provided an organic light emitting diode display comprising: a semiconductor layer formed on a substrate and including polycrystalline silicon; at least a portion of the upper surface of the source / An etch stopper of a metal material positioned to cover at least a portion of a side surface of the source / drain region; a storage capacitor lower electrode located apart from the semiconductor layer and formed simultaneously with the etch stopper on the substrate; A storage capacitor upper electrode spaced apart from the gate electrode and corresponding to the storage capacitor lower electrode; a gate electrode electrically connected to the semiconductor layer and the gate electrode to insulate the semiconductor layer from the gate electrode; A gate insulating film disposed between the semiconductor layers, A source / drain electrode electrically connected to the source / drain region, a protective film located on the source / drain electrode, a first electrode located on the protective film and electrically connected to the source / drain electrode, And a second electrode.

According to one embodiment, the storage capacitor lower electrode may be formed of the same material and the same process as the etch stopper.

According to an embodiment, the etch stopper and the capacitor lower electrode may be patterned by a photolithography process.

According to an embodiment, the semiconductor layer and the etch stopper may be heat-treated after the patterning.

According to an embodiment, each of the source / drain electrodes may be in contact with the upper surface of the etch stopper.

According to an embodiment, an oxide layer formed between the source / drain region and the etch stopper may be further included.

The thin film transistor according to embodiments of the present invention includes an etch stopper of a metal material positioned to cover at least a part of the upper surface of the source / drain region and at least a part of the side surface of the source / drain region, It is possible to prevent the source / drain region from being etched (or lost) during the etching process. Therefore, since the semiconductor layer having a very thin thickness can be uniformly formed, the leakage current problem of the thin film transistor can be greatly improved.

The method of manufacturing a thin film transistor according to embodiments of the present invention can prevent a source / drain region from being etched (or lost) during an etching process for forming a source / drain contact hole.

The OLED display according to embodiments of the present invention can uniformly form a semiconductor layer having a very thin thickness in realizing a large area display device by including the thin film transistor, It can be greatly improved. In addition, since the etch stopper and the lower electrode of the storage capacitor are formed of the metal material through the same patterning process, the manufacturing process is simplified and the doping process for the lower electrode of the storage capacitor is not required.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be variously expanded without departing from the spirit and scope of the present invention.

1 is a cross-sectional view illustrating a thin film transistor according to embodiments of the present invention.
2 is a cross-sectional view showing an example of the thin film transistor of FIG.
3 is a flowchart showing a method of manufacturing a thin film transistor according to embodiments of the present invention.
4A to 4D are cross-sectional views illustrating an example of a process of manufacturing the thin film transistor of FIG.
5A to 5E are cross-sectional views illustrating a manufacturing process of the organic light emitting display device and the organic light emitting display device according to the embodiments of the present invention.
6 is a cross-sectional view showing an example of the organic light emitting diode display of FIG.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention can be variously modified and may take various forms and should not be interpreted as being limited to specific embodiments.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Also, the terms "to" and the like in the present description mean a unit for processing at least one function or operation, and may be implemented by hardware, software, or a combination of hardware and software.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a cross-sectional view illustrating a thin film transistor according to embodiments of the present invention.

1, a thin film transistor 100 includes a substrate 110, a buffer layer 120, a semiconductor layer 130, etch stoppers 140a and 140b, a gate insulating layer 150, a gate electrode 160, A source electrode 170, and source / drain electrodes 180a and 180b.

When the thin film transistor 100 is applied to a display device, the thin film transistor 100 may include a switching transistor and a driving transistor. The switching transistor can perform a function of providing a data signal from the data line and the driving transistor can perform the function of receiving the data signal from the switching transistor and controlling the amount of current.

The substrate 110 may include a transparent substrate such as a glass substrate, a quartz substrate, a transparent plastic substrate, or the like. For example, the transparent plastic substrate that can be used as the substrate 110 may be a polyimide, an acryl, a polyethylene terephthalate, a polycarbonate, a polyacrylate, Polyether, and the like. In addition, the substrate 110 may be formed of a flexible substrate.

In one embodiment, a buffer layer 120 may be further included on the substrate 110. The buffer layer 120 may prevent diffusion of impurities generated from the substrate 110 and may control the heat transfer rate during the crystallization process for forming a semiconductor pattern. According to exemplary embodiments, the buffer layer 120 may comprise silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or the like. The buffer layer 120 may have a single-layer structure or a multi-layer structure including a silicon compound.

A semiconductor layer 130 including a polycrystalline silicon layer may be disposed on the substrate 110 or the buffer layer 120. The polycrystalline silicon layer can be formed by crystallizing amorphous silicon into polycrystalline silicon. A method of crystallizing amorphous silicon into a polycrystalline silicon layer may include a crystallization method using a metal catalyst such as a metal induced crystallization (MIC) method, a metal induced lateral crystallization (MILC) method, or a super grain silicon (SGS) method. However, the method of crystallizing the polycrystalline silicon layer is not limited thereto. For example, the polycrystalline silicon layer can be crystallized by excimer laser annealing (ELA) which crystallizes by using a low-temperature laser. In addition, the semiconductor layer 130 may be formed of an oxide semiconductor according to an embodiment.

The semiconductor layer 130 may include source / drain regions 130a and 130b and channel regions 132 formed by implanting n + or p + impurities through the source contact hole and the drain contact hole, respectively. At this time, the semiconductor layer 130 further includes a light doped drain (LDD) region doped with n-impurities on the channel region 132 and the source / drain regions 130a and 130b to reduce the off current You may.

The etch stoppers 140a and 140b may be positioned to cover at least a portion of the upper surface of the source / drain regions 130a and 130b of the semiconductor layer 130 and at least a portion of the sides of the source / drain regions 130a and 130b . The etch stoppers 140a and 140b may be formed of a conductive metal material. For example, the etch stoppers 140a and 140b may include any one of metals such as titanium (Ti), molybdenum (Mo), and chromium (Cr), or an alloy thereof. However, this is an exemplary one, and the etch stoppers 140a and 140b may include various metal materials depending on the embodiment. A metal material is deposited on the buffer layer 120 and the semiconductor layer 150 and then patterned by a photolithography process to form at least a portion of the upper surface of the source / drain regions 130a and 130b of the semiconductor layer 130 And etch stoppers 140a and 140b may be formed to cover at least a part of the side surfaces of the source / drain regions 130a and 130b. At this time, the etch stoppers 140a and 140b may be formed by a wet etching process. However, this is merely an example, and the process of forming the etch stoppers 140a and 140b is not limited thereto. The etch stoppers 140a and 140b are formed such that the source / drain regions 130a and 130b located under the etch stoppers 140a and 140b are etched (or removed) when the source contact holes and the drain contact holes are formed It can play a role to prevent.

In one embodiment, the semiconductor layer 130 and the etch stoppers 140a and 140b may be heat treated after the patterning process of the etch stoppers 140a and 140b. The amount of the metal catalyst in the semiconductor layer 130 is reduced by the heat treatment process and the gettering effect may be generated toward both sides of the semiconductor layer 130. The gettering effect can reduce the leakage current and prolong the lifetime of the carrier, which can contribute to improvement of the performance of the thin film transistor. The heat treatment process may be a furnace process, a rapid thermal annealing (RTA) process, a UV process, or a laser process.

The gate electrode 160 may be positioned corresponding to the channel region 132 of the semiconductor layer 130. The gate insulating layer 150 may be disposed between the semiconductor layer 130 and the gate electrode 160 to isolate the semiconductor layer 130 from the gate electrode 160. The gate electrode 160 may be composed of a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd) or a multilayer of aluminum alloy on a chromium (Cr) or molybdenum have. The gate insulating film 150 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof.

The source / drain electrodes 180a and 180b may be electrically connected to the source / drain regions 130a and 130b of the semiconductor layer 130, respectively. The source / drain electrodes 180a and 180b may be formed to be insulated from the gate electrode 160 by an interlayer insulating layer 170. [ In one embodiment, the source / drain electrodes 180a and 180b may be formed to contact the upper surfaces of the etch stoppers 140a and 140b, respectively. That is, the source / drain electrodes 180a and 180b are formed in the source contact hole and the drain contact hole through the gate insulating film 150 and the interlayer insulating film 170, respectively. At this time, since the etch stoppers 140a and 140b are formed of a metal material, they are not etched (or removed) by the etching process. Therefore, the source / drain electrodes 180a and 180b do not directly contact the source / drain regions 130a and 130b by the etch stoppers 140a and 140b. The source / drain electrodes 180a and 180b may be formed of a material selected from the group consisting of Mo, Cr, W, MoW, Al, Al-Nd, And may be formed of any one of titanium nitride (TiN), copper (Cu), molybdenum alloy (Mo alloy), aluminum alloy (Al alloy), and copper alloy (Cu alloy).

The interlayer insulating layer 170 may be formed of an organic material. For example, the interlayer insulating layer 170 may be formed of a photoresist, an acryl-based polymer, a polyimide-based polymer, a polyamide-based polymer, a siloxane-based polymer, A novolak resin, an alkali-soluble resin, and the like. These may be used alone or in combination with each other. In other exemplary embodiments, the interlayer insulating film 170 may be formed using an inorganic material such as a silicon compound, a metal, or a metal oxide. For example, the interlayer insulating film 170 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), silicon carbonitride (SiCxNy), aluminum (Al) Mg, Mg, Zn, Hf, Zr, Ti, Ta, AlOx, TiOx, TaOx, MgOx, ), Zinc oxide (ZnOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), and the like. These may be used alone or in combination with each other.

In one embodiment, an oxide layer and / or a nitride layer may be further formed between the source / drain regions 130a and 130b and the etch stoppers 140a and 140b. The oxide film layer and the nitride film layer may be formed thinly on the polycrystalline silicon layer as a by-product in the crystallization process of the polycrystalline silicon of the semiconductor layer 130. Therefore, the etch stoppers 140a and 140b can be patterned on the upper portion. At this time, since the side surfaces of the source / drain regions 130a and 130b are in contact with the etch stoppers 140a and 140b, the source / drain electrodes 180a and 180b can be electrically connected to the source / drain regions 130a and 130b have. In addition, the oxide film layer and / or the nitride film layer above the channel region 132 can be removed by a cleaning process performed immediately before the formation of the gate insulating film 150. The cleaning process may be performed by a hydrofluoric acid (HF) -based material.

As described above, the thin film transistor 100 according to the embodiments of the present invention includes the source / drain regions 130a and 130b by disposing the metal stoppers 140a and 140b so as to cover the upper and side surfaces of the source / drain regions 130a and 130b, It is possible to prevent the source / drain regions 130a and 130b from being etched (or lost) during the etching process for forming the contact holes. Therefore, since the semiconductor layer 130 having a very thin thickness can be uniformly formed, the leakage current problem of the thin film transistor can be greatly improved.

2 is a cross-sectional view showing an example of the thin film transistor of FIG.

2, the thin film transistor 200 includes a substrate 110, a buffer layer 120 formed on the substrate 110, a semiconductor layer 130 including a polycrystalline silicon layer, a source / The etch stoppers 140a and 140b of metal material positioned to cover at least a part of the upper surface of the source and drain regions 130a and 130b and at least a part of the side surfaces of the source / drain regions 130a and 130b, A gate insulating film 150 positioned between the semiconductor layer 130 and the gate electrode 160 to insulate the electrode 160, a gate electrode 160 positioned corresponding to the channel region 132 of the semiconductor layer 130, An interlayer insulating film 170 for insulating the source / drain electrodes 180a and 180b and the gate electrode 160 from each other and source / drain regions 130a and 130b electrically connected to the source / drain regions 130a and 130b of the semiconductor layer 130, Electrodes 180a and 180b. However, since this has been described above, a detailed description of the overlapping contents will be omitted.

The polycrystalline silicon layer of the semiconductor layer is formed by crystallizing amorphous silicon into a polycrystalline silicon layer by using a crystallization method using a metal catalyst such as a metal induced crystallization (MIC) method, a metal induced lateral crystallization (MILC) method, or a super grain silicon .

In one embodiment, an oxide layer 136 may further be formed between the sidewall / drain regions 130a and 130b and the etch stoppers 140a and 140b. The oxide layer 136 may be formed thinly on the polycrystalline silicon layer as a by-product in the crystallization process of the polycrystalline silicon of the semiconductor layer 130. Therefore, the etch stoppers 140a and 140b can be patterned on the oxide film layer 136 without removing the oxide film layer 136. [ At this time, since the side surfaces of the source / drain regions 130a and 130b are in contact with the etch stoppers 140a and 140b, the source / drain electrodes 180a and 180b can be electrically connected to the source / drain regions 130a and 130b have. In addition, the oxide film layer formed on the channel region 132 may be removed by a cleaning process performed immediately before the formation of the gate insulating film 150. The cleaning process may be performed by a hydrofluoric acid (HF) -based material.

The thin film transistor 200 is formed by arranging etch stoppers 140a and 140b of a metal material so as to cover upper and side surfaces of the source / drain regions 130a and 130b, thereby forming source / drain contact holes in the source / It is possible to prevent the occurrence of etching (or loss) of the electrodes 130a and 130b.

FIG. 3 is a flow chart showing a method of manufacturing a thin film transistor according to embodiments of the present invention, and FIGS. 4A to 4D are cross-sectional views illustrating an example of a process of manufacturing the thin film transistor of FIG.

Referring to FIG. 3, a method of manufacturing a thin film transistor includes forming a semiconductor layer including a polycrystalline silicon layer on a substrate (Step S110), forming a source / drain region (Step S120). A gate insulating film is formed on the semiconductor layer and the etch stopper (Step S130). A gate insulating film is formed on the gate insulating film to correspond to the channel region of the semiconductor layer. An electrode may be formed (step S140). Then, an interlayer insulating film is formed over the entire surface of the substrate (Step S150), source / drain electrodes are formed to be electrically connected to the source / drain regions after forming contact holes passing through the gate insulating film and the interlayer insulating film . When the thin film transistor thus formed is applied to a display device, the thin film transistor may include a switching transistor and a driving transistor. The switching transistor can perform a function of providing a data signal from the data line and the driving transistor can perform the function of receiving the data signal from the switching transistor and controlling the amount of current.

4A, a buffer layer 120 is formed on a substrate 110, and a semiconductor layer 130 including a polycrystalline silicon layer is formed (Step S110). The polycrystalline silicon layer can be formed by crystallizing amorphous silicon into polycrystalline silicon. A method of crystallizing amorphous silicon into a polycrystalline silicon layer may include a crystallization method using a metal catalyst such as MIC method, MILC method or SGS method. However, the method of crystallizing the polycrystalline silicon layer is not limited thereto. The oxide layer and / or the nitride layer may be formed thin on the upper surface of the semiconductor layer 130 by the crystallization. The oxide film layer and the nitride film layer formed on the channel region of the semiconductor layer 130 are deteriorated in performance of the thin film transistor and can be removed by a subsequent process.

4B, an etch stopper (not shown) is formed of a metal material covering at least a part of the upper surface of the source / drain regions 130a and 130b of the semiconductor layer 130 and at least a part of the sides of the source / drain regions 130a and 130b 140a, and 140b may be formed (Step S120).

The semiconductor layer 130 may include source / drain regions 130a and 130b and a channel region 132 formed by implanting n + or p + impurities through a source contact hole and a drain contact hole in a subsequent process, respectively.

The etch stoppers 140a and 140b may be formed of a conductive metal material. For example, the etch stoppers 140a and 140b may include metals such as titanium (Ti), molybdenum (Mo), and chromium (Cr). However, this is an exemplary one, and the etch stoppers 140a and 140b may include various metal materials depending on the embodiment. A metal material is deposited on the buffer layer 120 and the semiconductor layer 150 and then patterned by a photolithography process to form at least a portion of the upper surface of the source / drain regions 130a and 130b of the semiconductor layer 130 And etch stoppers 140a and 140b may be formed to cover at least a part of the side surfaces of the source / drain regions 130a and 130b. At this time, the etch stoppers 140a and 140b may be formed by a wet etching process. However, this is merely an example, and the process of forming the etch stoppers 140a and 140b is not limited thereto.

In one embodiment, the semiconductor layer 130 and the etch stoppers 140a and 140b may be heat treated after the patterning process of the etch stoppers 140a and 140b. The amount of the metal catalyst in the semiconductor layer 130 is reduced by the heat treatment process and the gettering effect may be generated toward both sides of the semiconductor layer 130. The gettering effect can reduce the leakage current and prolong the lifetime of the carrier, which can contribute to improvement of the performance of the thin film transistor. The heat treatment process may be a furnace process, a rapid thermal annealing (RTA) process, a UV process, or a laser process.

4C, a gate insulating layer 150 is formed on the semiconductor layer 130 and the etch stoppers 140a and 140b (Step S130), and a channel region (not shown) of the semiconductor layer 130 is formed on the gate insulating layer 150 The gate electrode 160 may be formed to correspond to the gate electrode 132 (step S140).

The gate insulating layer 150 may be formed over the entire surface of the substrate 110 after removing the oxide layer formed on the channel region 132 of the semiconductor layer 130. In this case, The oxide film layer can be removed by a cleaning process. The cleaning process may be performed by a hydrofluoric acid (HF) -based material. In another embodiment, the etch stoppers 140a and 140b may be formed after removing the entire oxide layer formed on the semiconductor layer 130. [ 4B to 4B show an example in which the entire process of the oxide layer formed on the semiconductor layer 130 is removed and the subsequent process is performed. The gate electrode 160 may be composed of a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd) or a multilayer of aluminum alloy on a chromium (Cr) or molybdenum have. The gate insulating film 150 may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof.

4D, an interlayer insulating layer 170 is formed over the entire surface of the substrate 110 (step S150), a contact hole is formed through the gate insulating layer 150 and the interlayer insulating layer 170, The source / drain electrodes 180a and 180b may be formed to be electrically connected to the first electrodes 130a and 130b (Step S160). The source / drain contact holes may be formed by exposing only a part of the etch stoppers 140a and 140b through an etching process. At this time, the source / drain regions 130a and 130b and the channel region 132 may be formed in the semiconductor layer 130 by implanting n + or p + impurities through the source contact hole and the drain contact hole, respectively.

The etch stoppers 140a and 140b made of a metal material are not etched by the etching process. Therefore, the source / drain regions 130a and 130b located under the etch stoppers 140a and 140b can be kept constant in thickness without being affected by the etching process for forming the contact holes. Source / drain electrodes 180a and 180b may be formed through the contact holes (Step S160). In this case, the source / drain electrodes 180a and 180b and the source / drain regions 130a and 130b may be electrically connected through etch stoppers 140a and 140b formed of a metal material.

As described above, the method of manufacturing the thin film transistor 100 according to the embodiments of the present invention includes forming the etch stoppers 140a and 140b of the metal material covering the source / drain regions 130a and 130b after forming the semiconductor layer 130 (Or loss) of the source / drain regions 130a and 130b during the etching process for forming the source / drain contact holes can be prevented. Therefore, since the semiconductor layer 130 having a very thin thickness can be uniformly formed, the leakage current problem of the thin film transistor can be greatly improved.

5A to 5E are cross-sectional views illustrating a manufacturing process of the organic light emitting display device and the organic light emitting display device according to the embodiments of the present invention.

5A, the OLED display 500 includes a substrate 110, a buffer layer 120, a semiconductor layer 130, etch stoppers 140a and 140b, a gate insulating layer 150, a gate electrode 160, A storage capacitor including a thin film transistor including an interlayer insulating layer 170 and source / drain electrodes 180a and 180b, a storage capacitor lower electrode 520 and a storage capacitor upper electrode 540, source / drain electrodes 180a and 180b A first electrode 560, an organic light emitting structure 580, and a second electrode 590, which are electrically connected to each other.

The etch stoppers 140a and 140b are formed of a metal material and cover at least a part of the upper surface of the source / drain regions 130a and 130b of the semiconductor layer 130 and at least a part of the sides of the source / drain regions 130a and 130b. . The etch stoppers 140a and 140b are formed such that the source / drain regions 130a and 130b located under the etch stoppers 140a and 140b are etched (or removed) when the source contact holes and the drain contact holes are formed It can play a role to prevent.

However, since the thin film transistor has been described above, a detailed description of the overlapping contents will be omitted.

The organic light emitting diode display 100 may further include a storage capacitor provided on the substrate 110. The storage capacitor may serve to supply a predetermined current to the thin film transistor even if the switching transistor is turned off.

The storage capacitor lower electrode 520 is spaced apart from the semiconductor layer 130 and may be formed simultaneously with the etch stoppers 140a and 140b. In one embodiment, the storage capacitor lower electrode 520 may be formed of the same material and the same process as the etch stoppers 140a and 140b. For example, in one embodiment, the storage capacitor lower electrode 520 and the etch stoppers 140a and 140b may be patterned by a photolithography process and may be formed of the same metal material. Thus, the storage capacitor may have a capacitor structure of a metal-insulator-metal structure.

The storage capacitor upper electrode 540 may be formed on the gate insulating film 150. The storage capacitor upper electrode 540 may be formed at a position vertically corresponding to the storage capacitor lower electrode 520 and may be formed in the same layer as the gate electrode 160. The storage capacitor upper electrode 540 may include a gate electrode And may be insulated with respect to the storage capacitor lower electrode 520 by the insulating film 150.

The storage capacitor upper electrode 540 may be formed of the same material and the same structure as the gate electrode 160. Thus, the storage capacitor upper electrode 160 may comprise a transparent conductive material.

The storage capacitor lower electrode 520 is formed in the same layer as the semiconductor layer 130 through the same process as the etch stoppers 140a and 140 and the storage capacitor upper electrode 540 is formed in the same layer as the gate electrode 160 The manufacturing process of the OLED display 500 can be simplified.

The organic light emitting diode display 500 includes a thin film transistor and a passivation layer 550 covering the storage capacitor. The passivation layer 550 has a pixel contact hole exposing the drain electrode 180a of the transistor. The first electrode 560 can be connected to the source electrode 180b of the thin film transistor according to the circuit configuration.

The protective film 550 may include an inorganic film such as a silicon oxide film and a silicon nitride film and may include an organic film such as polyimide, benzocyclobutene series resin or acrylate, have. Or may have a laminated structure of the inorganic film and the organic film.

The first electrode 560 may be electrically connected to the drain electrode 180a through the contact hole. The first electrode 560 may be formed of an anode or a cathode. When the first electrode 180 is an anode, the anode may be formed of a transparent conductive film (for example, ITO, IZO, ITZO, or the like). When the first electrode 180 is a cathode, ), Calcium (Ca), aluminum (Al), silver (Ag), barium (Ba), or an alloy thereof.

A pixel defining layer 570 having an opening exposing a part of the surface of the first electrode 560 is formed on the first electrode 560 and an organic light emitting layer 560 including an organic light emitting layer is formed on the exposed first electrode 560 The structure 580 may be formed. The organic light emitting structure 580 may include a layer including at least one of a hole injecting layer, a hole transporting layer, a hole blocking layer, an electron blocking layer, an electron injecting layer, and an electron transporting layer. The second electrode 590 may be formed on the organic light emitting structure 580 and the pixel defining layer 570.

Referring to FIG. 5B, a buffer layer 120 may be formed on a substrate 110, and a semiconductor layer 130 including a polycrystalline silicon layer may be formed. The polycrystalline silicon layer can be formed by crystallizing amorphous silicon into polycrystalline silicon. The oxide layer and / or the nitride layer may be formed thin on the upper surface of the semiconductor layer 130 by the crystallization. The oxide film layer and the nitride film layer formed on the channel region of the semiconductor layer 130 are deteriorated in performance of the thin film transistor and can be removed by a subsequent process.

Referring to FIG. 5C, an etch stopper (not shown) is formed of a metal material covering at least a part of the upper surface of the source / drain regions 130a and 130b of the semiconductor layer 130 and at least a part of the sides of the source / drain regions 130a and 130b 140a and 140b and the storage capacitor lower electrode 520 may be formed simultaneously.

The etch stoppers 140a and 140b and the storage capacitor lower electrode 520 may be made of the same metal material having conductivity. For example, the etch stoppers 140a and 140b and the storage capacitor lower electrode 520 may include any one of metals such as titanium (Ti), molybdenum (Mo), and chromium (Cr), or an alloy thereof. However, it is to be understood that various metal materials may be included according to the embodiment. Accordingly, the storage capacitor may have a metal-insulator-metal structure. Therefore, the process of doping the storage capacitor lower electrode 520 separately can be omitted.

In one embodiment, the etch stoppers 140a and 140b and the capacitor lower electrode 520 may be formed by patterning a metal material deposited on the semiconductor layer 130 and the buffer layer 120 by a photolithography process. At this time, the etch stoppers 140a and 140b and the storage capacitor lower electrode 520 may be formed by a wet etching process. However, the etching stoppers 140a and 140b and the process of forming the storage capacitor lower electrode 520 are not limited thereto.

In one embodiment, the semiconductor layer 130 and the etch stoppers 140a and 140b may be heat treated after the patterning process of the etch stoppers 140a and 140b. The amount of the metal catalyst in the semiconductor layer 130 is reduced by the heat treatment process and the gettering effect may be generated toward both sides of the semiconductor layer 130. However, since this has been described above, a duplicate description thereof will be omitted.

5D, a gate insulating layer 150 is formed on the semiconductor layer 130 and the etch stoppers 140a and 140b, and then the gate insulating layer 150 is formed on the channel region 132 of the semiconductor layer 130 The storage capacitor upper electrode 540 may be formed at a position corresponding to the storage capacitor lower electrode 520 in the vertical direction while forming the gate electrode 160 correspondingly positioned. The storage capacitor upper electrode 540 may be composed of the same material as the gate electrode 160. [ Thus, the storage capacitor may have a metal-insulator-metal structure.

5E, an interlayer insulating layer 170 is formed over the entire surface of the substrate 110, a contact hole is formed through the gate insulating layer 150 and the interlayer insulating layer 170, and then the source / drain regions 130a and 130b The source / drain electrodes 180a and 180b may be formed to be electrically connected to the source / drain electrodes 180a and 180b.

The etch stoppers 140a and 140b made of a metal material are not etched by the etching process that forms the source / drain contact holes to form the source / drain electrodes 180a and 180b. Therefore, the source / drain regions 130a and 130b located under the etch stoppers 140a and 140b can be kept constant in thickness without being affected by the etching process for forming the contact holes. In this case, the source / drain electrodes 180a and 180b and the source / drain regions 130a and 130b may be electrically connected through etch stoppers 140a and 140b formed of a metal material.

5A can be manufactured by forming the passivation layer 550, the first electrode 560, the pixel defining layer 570, the organic light emitting structure 580 and the second electrode in a subsequent process .

As described above, the OLED display 500 includes source / drain contact holes by disposing the metal stoppers 140a and 140b so as to cover the top and side surfaces of the source / drain regions 130a and 130b It is possible to prevent the source / drain regions 130a and 130b from being etched (or lost) during the etching process. Therefore, in realizing a large-area display device, the semiconductor layer 130 having a very thin thickness can be uniformly formed, so that the leakage current problem of the thin film transistor can be greatly improved. In addition, since the etch stoppers 140a and 140b and the storage capacitor lower electrode 520 are formed of a metal material through the same patterning process, the manufacturing process is simplified and a doping process for the storage capacitor lower electrode 520 is further required There is an advantage that it is not.

6 is a cross-sectional view showing an example of the organic light emitting diode display of FIG.

6, the OLED display 600 includes a substrate 110, a buffer layer 120 formed on the substrate 110, a semiconductor layer 130 including a polycrystalline silicon layer, a semiconductor layer 130, The etch stoppers 140a and 140b and the semiconductor layer 130 are formed to cover at least a portion of the upper surface of the source / drain regions 130a and 130b and at least a portion of the side surfaces of the source / drain regions 130a and 130b, A storage capacitor lower electrode 520 spaced apart from the gate electrode 160 and formed simultaneously with the etch stoppers 140a and 140b, a semiconductor layer 130 and a gate electrode 160 for insulating the semiconductor layer 130 from the gate electrode 160, A gate electrode 160 positioned to correspond to the channel region 132 of the semiconductor layer 130 and a gate electrode 160 spaced apart from the gate electrode 160 and being connected to the storage capacitor lower electrode 520, A correspondingly positioned storage capacitor top electrode 540, source / drain pre- Drain electrodes 180a and 180b electrically connected to the source / drain regions 130a and 130b of the semiconductor layer 130. The source / drain electrodes 180a and 180b are electrically connected to the source / drain regions 130a and 130b of the semiconductor layer 130, A protective layer 570, a first electrode 560, an organic light emitting structure 580, and a second electrode 590 disposed on the source / drain electrodes 180a and 180b. However, since this has been described above, a detailed description of the overlapping contents will be omitted.

In one embodiment, an oxide layer 136 may further be formed between the source / drain regions 130a and 130b and the etch stoppers 140a and 140b. The oxide layer 136 may be formed thinly on the polycrystalline silicon layer as a by-product in the crystallization process of the polycrystalline silicon of the semiconductor layer 130. Therefore, the etch stoppers 140a and 140b can be patterned on the oxide film layer 136 without removing the oxide film layer 136. [ At this time, since the side surfaces of the source / drain regions 130a and 130b are in contact with the etch stoppers 140a and 140b, the source / drain electrodes 180a and 180b can be electrically connected to the source / drain regions 130a and 130b have. In addition, the oxide film layer formed on the channel region 132 may be removed by a cleaning process performed immediately before the formation of the gate insulating film 150. The cleaning process may be performed by a hydrofluoric acid (HF) -based material.

The present invention can be applied to a thin film transistor and an organic light emitting display having the same. For example, the present invention may be applied to various electrical and electronic devices such as televisions, monitors, mobile communication devices, MP3, portable display devices, lighting devices, and the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims. It can be understood that it is possible.

100, 200: thin film transistor 110: substrate
130: semiconductor layer 130a, 130b: source / drain region
132: channel region 136: oxide layer
140a, 140b: etch stopper 150: gate insulating film
160: gate electrode 170: interlayer insulating film
180a, 180b: source / drain electrodes 500, 600: organic light emitting display
520: storage capacitor lower electrode
540: storage capacitor upper electrode

Claims (18)

A semiconductor layer formed on the substrate, the semiconductor layer including a polycrystalline silicon layer;
An etch stopper of a metal material positioned to cover at least a portion of an upper surface of a source / drain region of the semiconductor layer and at least a portion of a side surface of the source / drain region;
A gate electrode corresponding to the channel region of the semiconductor layer;
A gate insulating film positioned between the semiconductor layer and the gate electrode to insulate the semiconductor layer from the gate electrode; And
And source / drain electrodes electrically connected to the source / drain regions of the semiconductor layer, respectively. The method according to claim 1,
And a buffer layer on the substrate. The thin film transistor according to claim 1, wherein the etch stopper is patterned by a photolithography process. The thin film transistor of claim 3, wherein the semiconductor layer and the etch stopper are subjected to a heat treatment after the patterning. The thin film transistor of claim 1, wherein each of the source / drain electrodes is in contact with an upper surface of the etch stopper. The method according to claim 1,
And an oxide layer formed between the source / drain region and the etch stopper. Forming a semiconductor layer including a polycrystalline silicon layer on a substrate;
Forming an etch stopper covering at least a portion of an upper surface of the source / drain region of the semiconductor layer and at least a portion of a side surface of the source / drain region with a metal material;
Forming a gate insulating film on the semiconductor layer and the etch stopper;
Forming a gate electrode on the gate insulating film so as to correspond to a channel region of the semiconductor layer;
Forming an interlayer insulating film over the entire surface of the substrate; And
And forming a source / drain electrode to be electrically connected to the source / drain region. 8. The method of claim 7,
Forming a buffer layer on the substrate; and forming a buffer layer on the substrate. 8. The method of claim 7, wherein the etch stopper is patterned by a photolithography process. 10. The method of claim 9, wherein forming the etch stopper comprises:
Further comprising the step of heat treating the semiconductor layer and the etch stopper. 8. The method of claim 7, wherein the source / drain electrodes are respectively in contact with the upper surface of the etch stopper. 8. The method of claim 7, wherein forming the gate insulating layer comprises:
Removing an oxide layer formed on the channel region of the semiconductor layer;
And applying the gate insulating film over the entire surface of the substrate. A semiconductor layer formed on the substrate and including polycrystalline silicon;
An etch stopper of a metal material positioned to cover at least a portion of an upper surface of a source / drain region of the semiconductor layer and at least a portion of a side surface of the source / drain region;
A storage capacitor lower electrode spaced from the semiconductor layer and formed on the substrate at the same time as the etch stopper;
A gate electrode corresponding to the channel region of the semiconductor layer;
A storage capacitor upper electrode spaced apart from the gate electrode and corresponding to the storage capacitor lower electrode;
A gate insulating film positioned between the semiconductor layer and the gate electrode to insulate the semiconductor layer from the gate electrode;
Source / drain electrodes electrically connected to the source / drain regions of the semiconductor layer;
A protective film on the source / drain electrode; And
An organic light emitting diode (OLED), and a second electrode disposed on the passivation layer and electrically connected to the source / drain electrode. 14. The OLED display of claim 13, wherein the storage capacitor lower electrode is formed of the same material and the same process as the etch stopper. 15. The OLED display of claim 14, wherein the etch stopper and the capacitor lower electrode are patterned by a photolithography process. The organic light emitting diode display according to claim 15, wherein the semiconductor layer and the etch stopper are subjected to heat treatment after the patterning. 14. The OLED display of claim 13, wherein the source / drain electrodes are respectively in contact with the upper surface of the etch stopper. 14. The method of claim 13,
And an oxide layer formed between the source / drain region and the etch stopper.

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