KR20140119577A - Cell array of single poly EEPROM and method of operating the same - Google Patents

Abstract

A cell array of a single poly EEPROM, according to an embodiment, comprises a single well region shared by a plurality of unit cells. Each of the unit cells include: an array control gate (ACG) region including a single poly gate disposed to overlap in the well region; a read transistor including a single poly gate overlapped by being extended from the single poly gate of the ACG region, and a reading region in which the read transistor is disposed; and a tunneling transistor including a single poly gate overlapped by being extended from the single poly gate from the reading region, and a tunneling region in which a program selecting transistor is disposed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell array of a single poly-

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly, to a cell array of a single poly-type polyimide and an operation method thereof.

Various structures for an EEPROM memory cell capable of electrically programming and erasing data among nonvolatile memory elements in which data stored in the memory cells are not erased even when power supply is interrupted are proposed. As a unit memory cell structure of an EEPROM (EEPROM), a stack gate structure in which a floating gate for storing data and a control gate formed over a floating gate are sequentially stacked is adopted . However, recently, as the size of electronic devices has become smaller and the manufacturing technology of semiconductor devices has improved, a variety of semiconductor devices, such as logic devices and memory devices, which perform various functions in one semiconductor chip, System On Chip (EEPROM) is emerging as a key component of advanced digital products, and therefore embedded EEPROM manufacturing technology embedded in a system on chip (SOC) is required.

In order to manufacture such an embedded EEPROM, logic devices and EEPROM are manufactured in the same process step. Logic devices typically employ transistors of a single gate structure, and the fabrication process of embedding an EEPROM, which employs a stacked gate structure, on the same substrate together with logic elements becomes very complicated. To solve this problem, a single poly EEPROM, which is a single gate structure rather than a laminated gate structure, has been widely used as an embedded EEPROM. When a single poly EEPROM is employed, a system-on-chip (SOC) can be easily implemented by applying a general complementary metal oxide semiconductor (CMOS) manufacturing process applied to manufacture logic devices.

In general, the embedded EEPROM requires a fast access time and thus has a NOR-type array structure rather than a NAND type. In this case, there is a restriction on the application of a designing circuit that can prevent a read error phenomenon caused by an over erased unit cell in the reading process. Therefore, in the operation process in the unit cell or the cell array, It is necessary to prevent a reading error phenomenon due to over-erasing. In addition to this, it is also required to suppress the generation of a distrub that is undesirably affected by a unit cell not selected in the program or the reading process.

A problem to be solved by the present application is to provide a cell array of a single poly-type microprocessor and a method of operating the cell array so as to suppress the occurrence of disturbance during a reading process or a program process.

An example cell array of single poly i pyrimes comprises a single well region shared by a plurality of unit cells, each unit cell comprising an array comprising a single poly gate arranged to overlap the well region A read region in which a read transistor and a read select transistor are disposed, the read region including a control gate (ACG) region and a single poly gate extending from the single poly gate of the array control gate region; And a tunneling region in which a program selection transistor is disposed.

In one example, the single poly gate is placed in a floating state.

In one example, the unit cells include first, second, third, and fourth unit cells, the single poly gate of the first unit cell overlaps with the upper left portion of the well region, The polygate is overlapped with the right upper portion of the well region, the single poly gate of the third unit cell overlaps with the lower left portion of the well region, and the single poly gate of the fourth unit cell is overlapped with the lower right portion of the well region .

In this case, the read transistor may comprise a single poly gate and a first impurity region and a third impurity region at both ends of the single poly gate.

In this case, the read select transistor may include a read select gate, a second impurity region and a third impurity region at both ends of the read select gate.

In this case, the tunneling transistor may comprise a single poly gate and an impurity region overlapping the single poly gate.

In this case, the program selection transistor may include a program selection gate and a source region and a drain region at both ends of the program selection gate.

In this case, it may further comprise a wiring connecting the drain region of the program select transistor and the impurity region of the tunneling transistor.

In this case, a first program select gate line for connecting the program select gate of the first unit cell and a program select gate of the second unit cell, and a program select gate of the third unit cell are connected to a program select gate of the fourth unit cell And a second program select gate line.

In this case, a first program bit line connecting the source region of the program select transistor in the first unit cell and the source region of the program select transistor in the third unit cell, and the source region of the program select transistor in the second unit cell, And a second program bit line connecting the source region of the program select transistor in the fourth unit cell.

A first read select gate line connecting the read select gate of the first unit cell and the read select gate of the second unit cell and a read select gate of the third unit cell and a read select gate of the fourth unit cell, And a second read select gate line.

A first bit line connecting the second impurity region of the read select transistor in the first unit cell and the second impurity region of the read select transistor in the third unit cell and a second bit line connecting the second impurity region of the read select transistor in the second unit cell And a second bit line connecting the second impurity region of the read select transistor in the fourth unit cell.

A method of operating a cell array of a single poly-i-fluoride according to an example includes a single well region shared by a plurality of unit cells, each unit cell including a single poly gate arranged to overlap the well region A reading region in which a read transistor including a single poly gate extending from a single poly gate of the array control gate region and overlapping the read select transistor is arranged and a single poly gate of the read region, A method of operating a single poly Ipium cell array including a tunneling region in which a tunneling transistor including a single extended poly gate and a program selecting transistor are disposed, the method comprising: applying an erase voltage equal to or greater than a predetermined value to the array control gate region, Erase operation for unit cells A step of causing a program operation to be performed in a tunneling transistor of a unit cell selected by turning on a program select transistor of a selected unit cell among a plurality of unit cells, And causing a read operation to be performed in the read transistor of the unit cell selected by the turn-on of the transistor.

According to the embodiment disclosed in the present application, there is no restriction on the size of the cell array, and an advantage that the reliability of the device can be increased by preventing the occurrence of disturbance without a separate inhibit bias circuit is provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a layout diagram showing a cell array of single poly-type iipilm according to one embodiment of the present application. FIG.
2 is a layout diagram showing a first unit cell of the cell array of FIG.
FIGS. 3 to 5 are cross-sectional views taken along lines III-III ', IV-IV' and V-V ', respectively, of FIG.
6 is a diagram showing an erase operation of the cell array of the single poly-type Iipulm of FIG. 1. FIG.
7 is a diagram for explaining the programming operation of the cell array of the single poly-type Iipyrium of FIG.
FIG. 8 is a diagram for explaining a read operation of the cell array of single poly-type polyimide of FIG. 1; FIG.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a layout diagram showing a cell array of single poly-type iipilm according to one embodiment of the present application. FIG. 1, a cell array 100 of single poly-type i-pill according to this embodiment includes a first unit cell 100-1 disposed on the upper left side with respect to a first n-type well region 111, A second unit cell 100-2 disposed on the upper right side, a third unit cell 100-3 disposed on the lower left side, and a fourth unit cell 100-4 disposed on the lower right side . In this example, the array is a 2 ㅧ 2 structure, but in some cases, it may be an array of 2 ㅧ n (n is a natural number of 3 or more) structure.

The first unit cell 100-1, the second unit cell 100-2, the third unit cell 100-3 and the fourth unit cell 100-4 are connected to the first n-type well region 111, . Specifically, a portion of the single poly gate 140-1 of the first unit cell 100-1 overlaps with the upper left portion of the first n-type well region 111. [ A part of the single poly gate 140-2 of the second unit cell 100-2 overlaps with the upper right portion of the first n-type well region 111. [ A part of the single poly gate 140-3 of the third unit cell 100-3 overlaps with the lower left portion of the first n-type well region 111. [ A part of the single poly gate 140-4 of the fourth unit cell 100-4 overlaps with the lower right portion of the first n-type well region 111. [ In the first n-type well region 111, a first active region 131 is disposed. An array control gate (ACG) contact region 121 is disposed in the first active region 131. A portion of the single poly gate 140-1 of the first unit cell 100-1 overlaps with the upper left portion of the array control gate (ACG) contact region 121. [ A portion of the single poly gate 140-2 of the second unit cell 100-2 overlaps the upper right portion of the array control gate (ACG) contact region 121. [ A portion of the single poly gate 140-3 of the third unit cell 100-3 overlaps with the lower left portion of the array control gate (ACG) contact region 121. [ A portion of the single poly gate 140-4 of the fourth unit cell 100-4 overlaps with the lower right portion of the array control gate (ACG) contact region 121. [

2 is a layout diagram showing a first unit cell of the cell array of FIG. And FIGS. 3 to 5 are sectional views cut along the lines III-III ', IV-IV', and V-V 'of FIG. 2, respectively. Referring to FIG. 2 together with FIGS. 3 to 5, the first unit cell 100-1 of the single poly-type polyimide includes an array control gate (ACG) region 100C A single poly gate 140-1 is disposed on a substrate 200 having a tunneling region 100T and a read region 100R interposed therebetween. The substrate 200 may be doped with p-type and may have a p-type well region (not shown) if it does not have a p-type conductivity type. The single poly gate 140-1 is arranged to overlap with the array control gate region 100C. The single poly gate 140-1 extends from the control gate region 100C and overlaps the read region 100R and the tunneling region 100T. The single poly gate 140-1 is disposed on the substrate 200 in a floating state from the substrate 200 via the first gate insulating layer 145. [

The first n-type well region 111 is arranged in the array control gate (ACG) region 100C of the substrate 200. [ In the first n-type well region 111, a first active region 131 is disposed. The first active region 131 is defined by a device isolation layer 202. An array control gate (ACG) contact region 121 is disposed in the first active region 131. The conductivity type of the array control gate (ACG) contact region 121 is n + type, but it may be p + type in some cases. The array control gate (ACG) contact region 121 is provided with a contact 122 for applying a bias to the first n-type well region 111 through the array control gate (ACG) contact region 121. Although a single contact 122 is shown in the figure, it is possible that a plurality of contacts 122 may be arranged according to the size of the bias applied as an example only. Most of the area of the single poly gate 140-1 in the array control gate (ACG) region 100C overlaps the array control gate (ACG) contact region 121. [ 1, the first n-type well region 111 and the array control gate (ACG) contact region 121 are formed in the same manner as the single polygate of the other unit cells 100-2, 100-3, And are shared with the gates 140-2, 140-3, and 140-4.

A second active region 132 is disposed in the read region 100R of the substrate 200. [ The second active region 132 is also defined by the device isolation layer 202 and is spaced apart from the first n-type well region 111 by a certain distance. A first impurity region 161 and a second impurity region 162 are disposed at both ends of the second active region 132, and a third impurity region 163 is disposed between the first impurity region 161 and the second impurity region 162. The first impurity region 161, the second impurity region 162, and the third impurity region 163 all have an n + type conductivity type. The first impurity region 161 is a source region and the second impurity region 162 is a drain region. A source contact 171 is disposed in the first impurity region 161 and a drain contact 172 is disposed in the second impurity region 162. The single poly gate 140-1 passes over the substrate 200 between the first impurity region 161 and the third impurity region 163. The single poly gate 140-1 together with the first impurity region 161 and the third impurity region 163 constitute a read transistor RT. A read select gate 150 is disposed on the substrate 200 between the second impurity region 162 and the third impurity region 163 with a second gate insulating layer 155 interposed therebetween. The read select gate 150 together with the second impurity region 162 and the third impurity region 163 constitute a read select transistor RST. The read select gate 150 is provided with a contact 152 for bias application to the read select gate 150.

 A second n-type well region 112 is disposed in the tunneling region 100T of the substrate 200. [ A third active region 133 is disposed in the second n-type well region 112. The third active region 133 is also defined by the device isolation layer 202. An n + -type impurity region 180 for tunneling is disposed in the third active region 133. A contact 182 for bias application is disposed in the n + -type impurity region 180 for tunneling. A single poly gate 140-1 extending to the tunneling region 100T is disposed across the third active region 133. [ This single poly gate 140-1 together with the n + type impurity region 180 constitute a tunneling transistor TT. A fourth active region 134 is disposed at a position spaced apart from the second n-type well region 112 by a predetermined distance. The fourth active region 134 is also defined by the device isolation layer 202. An n + type source region 191 and an n + type drain region 192 are disposed at both ends of the fourth active region 134, respectively. The n + type source region 191 is provided with a contact 195 for bias application. Similarly, a contact 194 for bias application is disposed in the n + -type drain region 192 as well. A program selection gate 190 is disposed on the substrate 200 between the n + type source region 191 and the n + type drain region 192 via the third gate insulating layer 197. A contact 193 for application of a gate bias is disposed in the program selection gate 190. The program select gate 190 constitutes the program select transistor TST together with the n + type source region 191 and the n + type drain region 192. [ The contact 195 in the n + type source region 191 is electrically interconnected via the wire 198 with the contact 182 in the n + type impurity region 180 for tunneling. Therefore, whether or not bias is applied to the n < + > -type impurity region 180 can be determined by the turn-on or turn-off state of the program select transistor.

The structure of the first unit cell 100-1 described with reference to FIGS. 2 to 5 is the same as the structure of the second unit cell 100-1, which shares the first n-type well region 111 and the first active region 121 together. 2, the third unit cell 100-3, and the fourth unit cell 100-4, and therefore the second unit 100-2, the third unit cell 100-3, The description of the structure of the fourth unit cell 100-4 will be omitted.

FIGS. 6 to 8 are diagrams for explaining the operation of the cell array of the single poly-type Iipulm of FIG. In the single poly-type polyimide cell array according to this example, the program operation is performed for the selected unit cell, while the erase operation is performed for all the unit cells collectively. Hereinafter, the case where the selected unit cell is the first unit cell 100-1 will be described as an example. 6 to 8, a structure in which the first unit cell 100-1, the second unit cell 100-2, the third unit cell 100-3, and the fourth unit cell 100-4 are disposed Are the same as those shown in Fig.

In order to perform the erase operation with respect to the cell array of the single poly-type polyimide, as shown in FIG. 6, an erase voltage is applied to the first n-type well region 111 through the array control gate (ACG) 16V is applied. And do not apply any bias to other contacts. When the erase voltage is applied to the array control gate (ACG) contact region 121 as described above, the single poly gate 140-1 of the first unit cell 100-1 and the single cell of the second unit cell 100-2 The single poly gate 140-3 of the third unit cell 100-3 and the single poly gate 140-4 of the fourth unit cell 100-4 are coupled to the poly gate 140-2, Voltage is applied. The magnitude of the coupling voltage is determined by the coupling ratio of the single polygates 140-1, 140-2, 140-3, 140-4 and the array control gate (ACG) do. The coupling voltage is applied to the single polygates 140-1, 140-2, 140-3 and 140-4 so that the tunneling region of the first unit cell 100-1 and the tunneling region of the second unit cell 100- The electrons are injected into the single polygates 140-1, 140-2, and 140-4 in the tunneling region of the first unit cell 100-2, the tunneling region of the third unit cell 100-3, and the tunneling region of the fourth unit cell 100-4, The first unit cell 100-1, the second unit cell 100-2, the third unit cell 100-3, and the fourth unit cell 100- 4) are all large.

7, in order to perform the program operation for the first unit cell 100-1 of the single-poly type dipole type cell array without generating disturbance, For example, 16 V is applied to the program select gate 190 and the n + type source region 191, respectively. And 0 V is applied to the array control gate (ACG) contact region 121. Concretely, a program select gate line PSG1 for connecting the program select gate 190 of the first unit cell 100-1 and the program select gate 190-2 of the second unit cell 100-2 For example, a voltage of 16V is applied. On the other hand, the program select gate line PSG2 for connecting the program select gate 190-3 of the third unit cell 100-3 and the program select gate 190-4 of the fourth unit cell 100-4 0V is applied. And a program bit line PB1 connecting the n + type source region 191 of the first unit cell 100-1 and the n + type source region 191-3 of the third unit cell 100-3 to a predetermined size , For example, a voltage of 16V is applied. On the other hand, the program bit line PB2 connecting the n + type source region 191-2 of the second unit cell 100-2 and the n + type source region 191-4 of the fourth unit cell 100-4, 0V is applied.

The program select transistor 700-1 of the first unit cell 100-1 is turned on by the application of the bias, and therefore, the bias applied to the n + type source region 191 becomes the n + type drain region 192. [ And the n + -type impurity region 180 for tunneling through the wiring 198. As the 16V is applied to the n + type impurity region 180 for tunneling and the 0V is applied to the array control gate (ACG) contact region 121, the single polygate 140 of the first unit cell 100-1 -1) escape to the n + -type impurity region 180, and accordingly, the threshold voltage value becomes small. In the case of the second unit cell 100-2, the program select transistor 700-2 is turned on. However, as 0V is applied to the n + type source region 191-2, a bias is applied to the n + type impurity region 180 And as a result no program operation is performed. In the case of the third unit cell 191-3, 0V is applied to the single poly gate 190-3 so that the program select transistor is turned off. Therefore, even if 16V is applied to the n + type source region 191-3, A bias is not applied to the n + -type impurity region 180-3 for the n + -type impurity region 180-3. As a result, no program operation is performed for the third unit cell 191-3. In the case of the fourth unit cell 191-4, 0V is applied to the single-poly gate 190-4 so that the program select transistor is turned off and 0V is applied to the n + type source region 191-4 The program operation is not performed.

8, in order to perform the read operation for the first unit cell 100-1 of the single-poly type dipole type cell array without disturb, it is necessary to perform the read operation of the selected first unit cell 100-1 5 V and 1 V are applied to the read select gate 150 and the second impurity region 162, respectively. 0 V is applied to the array control gate (ACG) contact region 121, but a small read voltage may be applied in some cases. Specifically, a read select gate line RSG1 connecting the read select gate 150 of the first unit cell 100-1 and the read select gate 150-2 of the second unit cell 100-2 is applied with a voltage of 5V Is applied. On the other hand, in the read select gate line RSG2 for connecting the read select gate 150-3 of the third unit cell 100-3 and the read select gate 150-4 of the fourth unit cell 100-4, 0V is applied. A voltage of 1V is applied to the bit line BL1 connecting the second impurity region 162 of the first unit cell 100-1 and the second impurity region 162-3 of the third unit cell 100-3. . On the other hand, in the bit line BL2 connecting the second impurity region 162-2 of the second unit cell 100-2 and the second impurity region 162-4 of the fourth unit cell 100-4, 0V is applied.

As the voltage of 5V is applied to the read select gate line RSG1, the read select transistor of the first unit cell 100-1 is turned on. The bias of 1 V applied to the second impurity region 162 through the bit line BL1 is applied to the third impurity region 163 due to the turn-on of the read select transistor. Accordingly, the read transistor 800-1 is turned on or off according to the state of the threshold voltage. That is, when the read transistor 800-1 is turned on, a state having a low threshold voltage value, that is, a program state is determined. Conversely, even when the read select transistor is turned on and the bias of 1V is delivered to the third impurity region 163, it is determined that the read transistor 800-1 has a high threshold voltage value, that is, an erase state. In the case of the second unit cell 100-2, the read select transistor is turned on as 5V is applied to the read select gate line RSG1, but the third impurity region 163- 2, the bias is not applied to the second unit cell 100-2, so that the read operation for the second unit cell 100-2 is not performed. In the case of the third unit cell 100-3 and the fourth unit cell 100-4, as the 0V is applied to the read select gate line RSG2, the read select transistor is turned off, , And BL2, regardless of whether a bias is applied or not.

100C, 100R, 100T ... array control gate (ACG) area, read area, tunneling area
100-1, 100-2, 100-3, 100-4 ... First, second, third, and fourth unit cells
111, 112 ... first and second n-type well regions
121 ... Array Control Gate (ACG) Contact Area
131, 132, 133, 134 ... first, second, third, and fourth active regions
150 ... Read select gate
161, 162, 163 ... First, second, and third impurity regions
180 ... n + type impurity region for tunneling
190 ... program selection gate
191, 192 ... n + type source regions, n + type drain regions
198 ... wiring

Claims (13)

A single well region shared by a plurality of unit cells,
Each of the unit cells,
An array control gate (ACG) region including a single poly gate arranged to overlap the well region;
A read region in which a read transistor and a read select transistor are disposed, the read transistor including a single poly gate extending from and overlapping a single poly gate of the array control gate region; And
A tunneling transistor including a single poly gate extending from and overlapping a single poly gate of the read region; and a tunneling region in which a program select transistor is disposed. The method according to claim 1,
Wherein the single poly gate is disposed in a floating state. The method according to claim 1,
Wherein the unit cells include first, second, third, and fourth unit cells, a single poly gate of the first unit cell overlaps with a left upper portion of the well region, The single poly gate of the third unit cell overlaps the lower left portion of the well region and the single poly gate of the fourth unit cell overlaps the lower right portion of the well region, The cell array of single poly-i-pyrimes. The semiconductor memory device according to claim 3,
A single poly gate and a first impurity region and a third impurity region at both ends of the single poly gate. 5. The semiconductor memory device according to claim 4,
A read select gate, a second impurity region at both ends of the read select gate, and the third impurity region. The method of claim 5, wherein the tunneling transistor comprises:
Wherein the single poly gate and the single poly gate are overlapped with each other. 7. The semiconductor memory device according to claim 6,
A program select gate, and a source region and a drain region at both ends of the program select gate. 8. The method of claim 7,
And a wiring connecting the drain region of the program select transistor and the impurity region of the tunneling transistor. 9. The method of claim 8,
A first program select gate line connecting a program select gate of the first unit cell and a program select gate of the second unit cell; And
And a second program select gate line connecting a program select gate of the third unit cell and a program select gate of a fourth unit cell. 9. The method of claim 8,
A first program bit line connecting a source region of the program select transistor in the first unit cell and a source region of the program select transistor in the third unit cell; And
And a second program bit line connecting a source region of the program select transistor in the second unit cell and a source region of the program select transistor in the fourth unit cell. 9. The method of claim 8,
A first read select gate line connecting a read select gate of the first unit cell and a read select gate of the second unit cell; And
And a second read select gate line connecting a read select gate of the third unit cell and a read select gate of the fourth unit cell. 9. The method of claim 8,
A first bit line connecting a second impurity region of the read select transistor in the first unit cell and a second impurity region of the read select transistor in the third unit cell; And
And a second bit line connecting a second impurity region of the read select transistor in the second unit cell and a second impurity region of the read select transistor in the fourth unit cell. An array control gate (ACG) region including a single well region shared by a plurality of unit cells, each unit cell including a single poly gate arranged to overlap the well region; A tunneling transistor including a read polygate extending from and overlapping a single poly gate of the region and a read region in which a read select transistor is disposed and a single poly gate extending from the single poly gate of the read region, And a tunneling region in which a program select transistor is disposed, the method comprising:
Performing an erase operation on the plurality of unit cells by applying an erase voltage of a predetermined magnitude or more to the array control gate region;
Causing a program operation to be performed in a tunneling transistor of the selected unit cell by turning on a program selection transistor of a selected unit cell among the plurality of unit cells; And
And performing a read operation in a read transistor of the selected unit cell by turning on a read select transistor of a selected unit cell among the plurality of unit cells.

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