KR20140118187A - Phase change memory and method for fabrication of the same - Google Patents

Abstract

A phase change memory includes at least one wiring layer which includes a first conduction layer and a phase change layer horizontally deposited on the first conduction layer, a heater layer vertically touching the at least one wiring layer, and a second conduction layer which horizontally touches the heater layer and transmits a current which flows from at least one electrode to the least one wiring layer. The phase change layer is made of a phase change material. The thickness of the phase change layer is thinner than that of the first conduction layer.

Description

[0001] PHASE CHANGE MEMORY AND METHOD FOR FABRICATION OF THE SAME [0002]

Embodiments of the present invention are directed to a phase change memory using a phase change material and a method of manufacturing the phase change memory.

Recently, various three-dimensional memory device structures have been proposed to improve the two-dimensional phase scaling limitation of NAND flash memory. A typical example of the 3D NAND flash memory structure is a built-in current sensor (BICS) structure and a bit cost scalable (NAND flash cell) structure of a pipe type (Piped Type).

The BIC 3-D NAND flash memory structure uses ONO (Oxide-Nitride-Oxide) layer as storage, and the structure using nitride of Nitride layer is less reliable, Research is underway.

In addition, the NAND flash three-dimensional structure structurally scales on an ONO structure as a storage site in a vertical polysilicon channel, so that a contact size for a vertical channel becomes larger than that of an ONO layer And when the ONO thickness is taken as 10 nm to 20 nm, a contact area of 50 nm or more should be secured.

In recent years, studies have been continuing to secure characteristics of a NAND flash structure by combining a resistive memory element (e.g., a PRAM (Phase-change memory) or a ReRAM (Resistive RAM)) with the three-dimensional structure. A resistive memory device is easy to implement a cross-point relative to an ONO layer, and scaling is easier than an ONO layer in realizing a vertical channel or a gate. However, the three-dimensional structure using the resistance change material (PRAM, ReRAM) needs to be improved in terms of securing reliability.

Since the conventional 3D structure is difficult to scale vertically and it is difficult to maintain the contact hole size of the vertical channel (or gate electrode) to 40 nm or less due to the limitation of the storage thickness, Multiple layers of more than 100 layers are required to achieve the same degree of integration.

In a three-dimensional flash memory structure using a general phase-change material, a phase-change material is vertically formed on the sidewalls of the contact holes to make contact with the horizontal conductive layer. It is difficult to reduce the contact area to 20 nm or less in consideration of the resistance of the conductive layer, A phase change material for a memory in a hole, a heater layer, and the like are formed, so that it is difficult to scale the structure as compared with the structure using the ONO layer.

One embodiment of the present invention provides a three-dimensional NAND flash memory device structure in which a phase change material is formed.

One embodiment of the present invention aims at providing a thin wiring layer by depositing a phase change material horizontally on a conductive layer through an atomic layer deposition method.

One embodiment of the present invention aims at reducing the driving current density of a three-dimensional flash memory.

The phase change memory according to an embodiment of the present invention includes at least one wiring layer including a first conductive layer and a phase change layer horizontally deposited on the first conductive layer, a heater layer vertically contacting the at least one wiring layer, And a second conductive layer in parallel contact with the heater layer and through which current flows from at least one of the electrodes to the at least one interconnection layer, wherein the phase change layer is formed of a phase change material, Which is smaller than the thickness.

According to one aspect of the present invention, the phase change layer may be horizontally deposited on the first conductive layer by an atomic layer deposition (ALD) technique.

According to an aspect of the present invention, the phase-change layer may be formed to a thickness of 1 nm or less.

According to one aspect of the present invention, the one or more wiring layers can be separated from each other by one or more insulating layers interposed therebetween.

According to an aspect of the present invention, the phase-change layer may be phase-changed at a portion vertically contacting the heater layer.

The phase change memory according to an aspect of the present invention may further include an insulator formed in a space provided by etching a part of the first conductive layer.

According to an aspect of the present invention, the insulator may be formed at a portion where the at least one wiring layer and the heater layer are in contact with each other.

According to one aspect of the present invention, the one or more wiring layers may have a larger area than the wiring layer in which the wiring layer disposed at the lower portion is disposed at the upper portion.

The phase change memory according to an aspect of the present invention may further include one or more lower electrodes connected to the one or more wiring layers, and an upper electrode connected to the second conductive layer.

According to an embodiment of the present invention, there is provided a method of fabricating a phase change memory, comprising: providing a phase change layer horizontally on a first conductive layer to form at least one wiring layer; forming a heater layer vertically contacting the at least one wiring layer; And forming a second conductive layer in parallel contact with the heater layer and through which current flows from at least one electrode to the at least one interconnection layer, wherein the phase change layer is formed of a phase change material And is thinner than the thickness of the first conductive layer.

According to an embodiment of the present invention, a three-dimensional NAND flash memory device structure in which a phase change material is formed can be provided.

According to an embodiment of the present invention, a phase change material may be horizontally deposited on the conductive layer through an atomic layer deposition method to provide a thin wiring layer.

According to an embodiment of the present invention, the driving current density of the three-dimensional flash memory can be reduced.

1 is a diagram illustrating a structure of a phase-change memory according to an embodiment of the present invention.
2 is a vertical cross-sectional view illustrating current flow in a phase change memory according to one aspect of the present invention.
3 is a horizontal sectional view of a three-dimensional structure phase change memory.
4 is a vertical cross-sectional view of a three-dimensional structure phase change memory.
FIGS. 5 to 9 are views illustrating a manufacturing process of a phase-change memory having a cross-point structure according to an embodiment of the present invention.
10 is a flowchart illustrating a method of manufacturing a phase change memory according to an aspect of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and accompanying drawings, but the present invention is not limited to or limited by the embodiments.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The terminology used herein is a term used for appropriately expressing an embodiment of the present invention, which may vary depending on the user, the intent of the operator, or the practice of the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.

1 is a diagram illustrating a structure of a phase-change memory according to an embodiment of the present invention.

1, a phase change memory according to an exemplary embodiment of the present invention includes a first conductive layer 111 and a phase change layer 112 horizontally deposited on the first conductive layer 111, The wiring layer 110, the heater layer 120, and the second conductive layer 130 are structured.

The heater layer 120 is vertically in contact with one or more wiring layers 110 and the second conductive layer 130 is in parallel contact with the heater layer 120 and is electrically connected to at least one electrode 110 . The one or more wiring layers 110 may have a larger area than the wiring layer in which the wiring layer disposed at the lower portion is disposed at the upper portion.

The phase change layer 112 is formed of a phase change material and has a thickness thinner than the thickness of the first conductive layer 111. For example, the phase change layer 112 may be formed to a thickness of 1 nm or less. In addition, the phase change layer 112 may be deposited horizontally in the first conductive layer 111 by an atomic layer deposition (ALD) technique.

The phase change memory according to an aspect of the present invention may further comprise at least one lower electrode 140 connected to one or more wiring layers 110 and an upper electrode 150 connected to the second conductive layer 130. [

The phase change memory utilizes a phase change material having a contact area of atomic layer thickness as a storage material to improve the contact area scaling problem due to the limitation of the sidewall thickness of the memory structure using the ONO layer, The number of stacked layers can be reduced.

The phase change memory includes a phase change layer 112 formed by laminating a phase change material on a top surface or a bottom surface of a first conductive layer 111 in a horizontal direction by a monolayer (for example, a monolayer having a thickness of 1 nm or less) And the phase change layer 112 can be used as a memory site. The phase change memory is capable of scale contact area by removing memory storage material within the vertical contact holes.

According to one aspect of the present invention, a phase change memory having a three-dimensional structure can be reduced to less than 1/100 of that of a two-dimensional resistive memory by forming a phase change contact area with an atomic layer of 1 nm or less.

The phase change memory can provide a memory structure capable of preventing a short circuit between the wiring in the horizontal direction and the heater layer and the wiring in the vertical direction in the phase change contact region which is a cross point. For example, the phase change memory adopts the structure of the wiring layer 110 in the horizontal direction, the heater layer 120 in the vertical direction, and the second conductive layer 130, and is formed between the lower electrode 140 and the upper electrode 150 Current can be conducted without interruption.

2 is a vertical cross-sectional view illustrating current flow in a phase change memory according to one aspect of the present invention.

Referring to FIG. 2, the wiring layer 210 of the phase-change memory has an atomic layer thickness of 1 nm or less as the contact area of the phase-change layer 212, and a part of the first conductive layer 211 is chemically or dry A cross-point structure can be formed by forming the insulator 240 in a space provided by etching through the through holes. For example, the insulator 240 may be formed at a portion where one or more wiring layers 210 and the heater layer 220 are in contact with each other. In addition, the wiring layers 210 can be separated from each other by one or more insulating layers 250 interposed therebetween.

The phase change memory may be phase-shifted in a region where the phase-change layer 212 formed horizontally perpendicularly to the heater layer 220 or near the heater layer 220, Similarly, according to the crystallization of the phase change layer 212, a current can be conducted between the wiring layer 210 and the second conductive layer 230. At this time, the phase change layer in the horizontal direction can be drastically reduced by securing an extremely thin thickness of 1 nm or less by atomic layer deposition or the like.

FIG. 3 is a horizontal sectional view of a three-dimensional phase change memory, and FIG. 4 is a vertical sectional view of a three-dimensional phase change memory.

The phase-change memory may be a three-dimensional NAND flash memory device structure. As shown in FIGS. 3 and 4, in the horizontal or vertical cross-sectional structure, by using the thickness of the phase change material as the contact area, The driving current density can be extremely reduced by lowering the thickness of the phase change layer. The phase change memory can improve the integration degree by utilizing the three-dimensional structure, and can secure reliability at the cross point point.

For example, the phase-change memory of the three-dimensional memory structure may include at least one wiring layer 310 including a phase change layer 312 horizontally deposited on the first conductive layer 311 and the first conductive layer 311, A heater layer 320 in vertical contact with one or more wiring layers 310 and a second conductive layer 320 in parallel contact with the heater layer 320 and through which current flows from at least one electrode to one or more wiring layers 310. [ (330). At this time, the phase change memory may be formed with an insulator 340 in a space provided by etching a part of the first conductive layer 311. The phase change memory may conduct current between the wiring layer 310 and the second conductive layer 330 according to crystallization of the phase change layer 312 like the current path 350.

FIGS. 5 to 9 are views illustrating a manufacturing process of a phase-change memory having a cross-point structure according to an embodiment of the present invention.

Referring to FIG. 5, the first conductive layer 510, the phase change layer 520, and the insulating layer 530 are sequentially formed and repeatedly formed. Accordingly, a plurality of wiring layers in which the first conductive layer 510 and the phase-change layer 520 are alternately formed can be formed.

Referring to FIG. 6, a cavity 540 may be formed to penetrate the first conductive layer 510, the phase change layer 520, and the insulating layer 530 which are repeatedly formed.

Referring to FIG. 7, a horizontal etching process may be performed on the first conductive layer 510 on the structure shown in FIG. Through this etching process, a space 550 in which the insulators 560 separated from each other can be secured can be secured.

Referring to FIG. 8, a process of depositing an insulator 560 on a horizontally etched space 550 on the structure shown in FIG. 7 is performed, and a heater layer 570 is formed along the outer wall of the cavity 540, Lt; / RTI >

Referring to FIG. 9, after the heater layer 570 is deposited on the structure shown in FIG. 8, the open space can be filled with the second conductor layer 580.

10 is a flowchart illustrating a method of manufacturing a phase change memory according to an aspect of the present invention.

10, a phase change layer is deposited horizontally on the first conductive layer to form at least one wiring layer 1010. For example, a phase change layer may be formed by atomic layer deposition (ALD) So that it can be deposited horizontally on the first conductive layer.

In addition, at least one insulating layer may be formed between at least one wiring layer (1020), and an insulator may be formed in a space provided by etching a portion of the first conductive layer (1030). For example, the insulator may be formed at a portion where one or more wiring layers and the heater layer are in contact with each other.

In addition, a heater layer is formed (140) in vertical contact with one or more wiring layers, and a second conductive layer is formed in parallel contact with the heater layer and through which current flows from at least one electrode to one or more wiring layers (1050 ).

In addition, one or more lower electrodes connected to one or more wiring layers may be formed, and an upper electrode connected to the second conductive layer may be formed.

The phase-change memory according to one aspect of the present invention can secure scalability in a horizontal dimension, dramatically reduce the burden on the number of stacks in the vertical direction, and reduce manufacturing costs in terms of process technology. Dimensional memory structure capable of realizing a three-dimensional memory structure capable of achieving stable cell characteristics and reliability in a three-dimensional memory structure by vertical scaling.

A phase change memory according to one aspect of the present invention is a three-dimensional NAND flash memory device structure in which a thickness of a phase change material is used as a contact area and a phase change material is deposited on a conductive layer by an atomic layer deposition method, The driving current density can be extremely reduced.

The phase change memory according to one aspect of the present invention can improve the degree of integration by utilizing a three-dimensional structure and can secure data reliability due to resistance change at a data storage cross point.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

111: phase change layer
112: first conductive layer
110: wiring layer
120: heater layer
130: second conductive layer
140: lower electrode
150: upper electrode

Claims (18)

At least one wiring layer including a first conductive layer and a phase change layer horizontally deposited on the first conductive layer;
A heater layer vertically contacting the at least one wiring layer; And
A second conductive layer in parallel contact with the heater layer and through which current flows from the at least one electrode to the at least one interconnection layer,
/ RTI >
Wherein the phase change layer is formed of a phase change material and has a thickness thinner than the thickness of the first conductive layer. The method according to claim 1,
The phase-
Wherein the first conductive layer is deposited horizontally by an atomic layer deposition (ALD) technique. The method according to claim 1,
The phase-
And a thickness of 1 nm or less. The method according to claim 1,
Wherein the at least one wiring layer comprises:
Phase-change memory separated by one or more intervening dielectric layers. The method according to claim 1,
The phase-
And a phase change is made at a portion vertically contacting the heater layer. The method according to claim 1,
A first conductive layer formed on the first conductive layer,
/ RTI > The method according to claim 6,
The insulator
Wherein the at least one wiring layer and the heater layer are in contact with each other. The method according to claim 1,
Wherein the at least one wiring layer comprises:
Wherein the wiring layer disposed at the lower portion has a larger area than the wiring layer disposed at the upper portion. The method according to claim 1,
At least one lower electrode connected to the at least one wiring layer; And
And an upper electrode connected to the second conductive layer
/ RTI > Depositing a phase change layer horizontally on the first conductive layer to provide at least one wiring layer;
Forming a heater layer in vertical contact with the at least one wiring layer; And
Forming a second conductive layer in parallel contact with the heater layer and through which current flows from the at least one electrode to the at least one interconnection layer,
Lt; / RTI >
Wherein the phase change layer is formed of a phase change material and has a thickness thinner than the thickness of the first conductive layer. 11. The method of claim 10,
The step of providing the one or more wiring layers includes:
The phase-change layer is deposited horizontally on the first conductive layer by atomic layer deposition (ALD)
Wherein the phase change memory comprises a phase change memory. 11. The method of claim 10,
The phase-
And a thickness of 1 nm or less. 11. The method of claim 10,
Forming at least one insulating layer between the at least one wiring layer;
Further comprising the steps of: 11. The method of claim 10,
The phase-
And a phase change is made at a portion vertically contacting the heater layer. 11. The method of claim 10,
Forming an insulator in a space provided by etching a part of the first conductive layer;
Further comprising the steps of: 16. The method of claim 15,
The insulator
Wherein the one or more wiring layers and the heater layer are in contact with each other. 11. The method of claim 10,
Wherein the at least one wiring layer comprises:
Wherein the wiring layer disposed at the lower portion has a larger area than the wiring layer disposed at the upper portion. 11. The method of claim 10,
Forming at least one lower electrode connected to the at least one wiring layer; And
Forming an upper electrode connected to the second conductive layer
Further comprising the steps of:

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