KR20140115600A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device and, more specifically, to a liquid crystal display device capable of inputting clocks to both ends to a gate in panel (GIP) and a driving method thereof. The liquid crystal display device, according to the present invention, comprises: a panel in which pixels are formed in every intersection area of data lines and gate lines; a data driver for supplying a data voltage to the data lines; a timing controller for driving the data driver; and a first panel integrated gate driver which is embedded in a first non-display region of the panel, is driven by the same clocks inputted by the timing controller, and sequentially supplies scan signals to the gate lines.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display (LCD)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a large area and a high resolution and a driving method thereof.

Flat panel displays (FPDs) are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. Examples of flat panel display devices include a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) (EPD: ELECTROPHORETIC DISPLAY) are also widely used.

Among flat panel display devices, liquid crystal display devices are most widely commercialized at present because of advantages of mass production technology, ease of driving means, and realization of high image quality.

1 is a diagram illustrating an example of a conventional high resolution liquid crystal display device.

2. Description of the Related Art As a manufacturing technique of a liquid crystal display device has been developed, a large-area and high-resolution liquid crystal display device has been manufactured.

In a large-area and high-resolution liquid crystal display device, the panel load increases due to its large area, and high-speed driving is required because of its high resolution.

However, when a panel-built gate driver (GIP: Gate In Panel) is formed in a liquid crystal display device formed in a large area and driven at a high speed as described above, a delay of signal transmission is seriously generated, Charging shortage and poor color mixing occur. Therefore, in a large-area and high-resolution liquid crystal display device, the panel built-in gate driver (GIP) can not be normally operated.

That is, in a large-area and high-resolution liquid crystal display device, since the number of gate lines increases twice as many as the number of gate lines in a liquid crystal display device having a normal resolution, a delay corresponding to the clock capacitance CLK Cap increases, The gate falling time of the clock CLK input to the gate driver is increased. Therefore, in a large-area and high-resolution liquid crystal display device, a panel built-in gate driver (GIP) in which elements for outputting a scan signal to a gate line are formed directly on a panel can not be normally operated.

Therefore, in a large-area and high-resolution liquid crystal display device, for example, a UD class liquid crystal display device, each integrated gate drive IC is mounted on a TCP (Tape Carrier Package) The gate driver 20 is formed in a form connected to the panel 10 in the Tape Automated Bonding method. The gate driver 20 applied to a large-area and high-resolution liquid crystal display device may be mounted on the non-display area 11 of the panel 10 by a COG (Chip On Glass) method.

1, the gate driver 20 is mounted on the left and right non-display areas 11 on both sides of the panel 10, and the panel (not shown) The data driver 30 is mounted on the upper and lower non-display areas 11 of the motherboard 10 and the two timing controllers 40 for controlling the two data drivers 30 are mounted on the independent main board 50, Respectively.

In addition, among the conventional liquid crystal display devices in which a signal is input only at the left and right ends of the panel, a liquid crystal display device using a-Si, having a size of 21.6 "to 60" , And a panel built-in gate driver (GIP). However, a liquid crystal display device having a large area of 72 inches or more and driven by FHD and ultra-high resolution (UD class) has a load (R / C) twice as large as that of a conventional liquid crystal display device, Since the charging time is doubled, it can not be driven by a general panel built-in gate driver (GIP).

That is, when a liquid crystal display device having a large area of 72 inches or more, and driven by FHD and ultra-high resolution (UD class) is constituted by a conventional general GIP, the Cap / resistance to the clock CLK is large, Since the clock CLK in the deepened state is input to the panel built-in gate driver (GIP), even if the design of the panel built-in gate driver (GIP) is optimized, normal operation of the liquid crystal display device is impossible.

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above-mentioned problems, and it is a technical object of the present invention to provide a liquid crystal display device and a driving method thereof that can input clocks to both ends of a panel built-in gate driver (GIP).

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a panel having pixels formed at intersections of data lines and gate lines; A data driver for supplying a data voltage to the data lines; A timing controller for driving the data driver; And a first panel built-in gate driver which is built in a first non-display area of the panel and is driven by the same clocks input from the timing controller to sequentially supply a scan signal to the gate lines.

According to another aspect of the present invention, there is provided a liquid crystal display device comprising: a panel having pixels formed at intersections of data lines and gate lines; A first data driver coupled to the panel in a third non-display area of the panel, the data driver supplying a data voltage to the data lines; A second data driver connected to the panel in a fourth non-display area facing the third non-display area of the panel, the data driver supplying a data voltage to the data lines; A first timing controller for driving the first data driver; A second timing controller for driving the second data driver; A first timing controller which is incorporated in a first non-display area of the panel and is driven by a first clock input from the first timing controller and a second clock input from the second timing controller, A first panel built-in gate driver for supplying a signal; And a third non-display area which is embedded in a second non-display area of the panel facing the first non-display area, wherein the third clock input from the first timing controller and the fourth clock input from the second timing controller And a second panel built-in gate driver driven to supply a scan signal to the gate lines sequentially, wherein the first clock to the fourth clock have the same amplitude and period.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display, including: generating a gate control signal, a data control signal, and image data using timing signals input from an external system; Transmitting a clock included in the gate control signal to each of two different stages in a panel built-in gate driver built in a panel; Sequentially outputting a scan signal generated by using the two clocks to gate lines formed on the panel; And outputting the data voltage generated by using the data control signal and the image data to the data lines while the scan signal is output to the gate line.

According to the present invention, since a liquid crystal display device which is applied to a large-area and ultra-high resolution (FHD / UD) television can be realized by a panel built-in gate driver (GIP), a large area and ultra high resolution (FHD / UD) The manufacturing process of the liquid crystal display device applied to the television can be simplified, and the manufacturing cost can be reduced.

According to the present invention, since the gate driver IC can be omitted in a liquid crystal display device which is applied to a large-area and ultra-high resolution (FHD / UD) television, manufacturing cost of the liquid crystal display device can be reduced, It is possible to improve the design of the display device.

1 is an exemplary view showing a conventional high resolution liquid crystal display device.
2 is a view schematically showing a liquid crystal display device according to the present invention.
3 is a view showing a first embodiment of a panel built-in gate driver applied to a liquid crystal display device according to the present invention.
4 is a view showing a second embodiment of a panel built-in gate driver applied to a liquid crystal display device according to the present invention.
5 is another view schematically showing a liquid crystal display device according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a view schematically showing a liquid crystal display device according to the present invention.

2, the liquid crystal display device according to the present invention includes a panel 100 in which pixels are formed at intersecting regions of data lines DL1 to DLd and gate lines GL1 to GLg, A data driver 300 for supplying a data voltage to the data lines DL1 to DLd; a timing controller 400 for driving the data driver 300; And a first panel built-in gate driver 200a which is driven by the same clocks input from the timing controller 400 and sequentially supplies a scan signal to the gate lines GL1 to GLg.

First, the panel 100 includes pixels formed in regions defined by the intersections of the gate lines GL1 to GLg formed in the display region 110 and the data lines DL1 to DLd, A thin film transistor (TFT) is formed.

The thin film transistor (TFT) supplies a data voltage supplied from the data line to the pixel electrode in response to a scan signal supplied from the gate line. The transmittance of light is adjusted by driving the liquid crystal in which the pixel electrode is located in contact with the common electrode in response to the data voltage.

The liquid crystal mode of the panel applicable to the present invention may be any mode of liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. Further, the liquid crystal display device according to the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device.

Next, the data driver 300 converts the digital image data transmitted from the timing controller 400 into a data voltage, and supplies the data voltage of one horizontal line for each horizontal period supplied with the scan signal to the gate line To the data lines.

2, the data driver 300 may include at least one source drive IC connected to the panel 100 in a chip-on-film (COF) mode or a TCP (tape carrier package) mode . That is, the data driver 300 collectively refers to a plurality of source drive ICs, and the function of each of the source drive ICs is the same. Hereinafter, the data driver 300 refers to each of the source drive ICs.

The data driver 300 converts the image data into the data voltage using gamma voltages supplied from a gamma voltage generator (not shown), and outputs the data voltage to the data line. To this end, the data driver 300 includes a shift register unit, a latch unit, a digital-analog converter (DAC), and an output buffer.

The shift register unit outputs a sampling signal using data control signals (SSC, SSP, etc.) received from the timing controller (400).

The latch unit latches the digital image data (Data) sequentially received from the timing controller (400), and simultaneously outputs the digital image data (Data) to the digital-analog converter (DAC).

The digital-to-analog converter converts the image data transmitted from the latch unit into a data voltage of positive or negative polarity and outputs the same. That is, the digital-analog converter uses the gamma voltage supplied from the gamma voltage generator (not shown) to generate the image data according to the polarity control signal POL transmitted from the timing controller 400 Polarity or negative polarity data voltage and outputs the data voltage to the data lines.

The output buffer outputs a positive or negative polarity data voltage transmitted from the digital-analog converter to the data line DL of the panel according to a source output enable signal SOE transmitted from the timing controller 400, .

Next, the timing controller 400 uses the timing signals input from the external system 600, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE, Generates a gate control signal (GCS) for controlling the operation timing of the first panel built-in gate driver (200a) and a data control signal (DCS) for controlling the operation timing of the data driver (300) 300 to generate the image data to be transmitted.

The timing controller 400 includes a receiver for receiving input image data and timing signals from the external system 600, a control signal generator for generating various control signals, And outputs the control signals and the image data. The output unit 440 outputs the control signals and the image data.

That is, the timing controller 400 rearranges the input image data input from the external system 600 according to the structure and characteristics of the panel 100, and outputs the rearranged image data to the data driver (300). Such a function can be executed in the data arrangement section.

The timing controller 400 uses the timing signals transmitted from the external system 600, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE, A data control signal DCS for controlling the driver and a gate control signal GCS for controlling the first panel built-in gate driver and transmitting the control signals to the data driver and the first panel built- . Such a function may be executed in the control signal generator 400b.

The gate control signals GCS generated by the control signal generator 400b include a gate output enable signal GOE, a gate start signal VST, and a clock CLK.

The data control signals generated by the control signal generator 400b include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE and a polarity control signal POL .

Finally, the first panel built-in gate driver 200a sequentially applies a gate-on signal to each of the gate lines GL1 to GLg using the gate control signals GCS generated in the timing controller 400, .

Here, the gate-on signal refers to a voltage capable of turning on the switching thin film transistor connected to the gate lines. The voltage capable of turning off the switching thin film transistor is referred to as a gate off signal, and the gate on signal and the gate off signal are generically referred to as a scan signal.

When the thin film transistor is of the N type, the gate on signal is a high level voltage and the gate off signal is a low level voltage. When the thin film transistor is of the P type, the gate on signal is a low level voltage and the gate off signal is a high level voltage.

Meanwhile, the liquid crystal display according to the present invention has a large area of 72 " or more and is driven by FHD and ultra high resolution (UD class). In such a large-area high resolution liquid crystal display, Panel built-in gate drivers 200a and 200b are built in each of the two non-display areas of the panel 100. [ 2, the non-display area formed on the left side of the panel 100 is referred to as a first non-display area and the non-display area opposite thereto is referred to as a second non-display area, The non-display area formed on the upper side is referred to as a third non-display area, and the non-display area facing the latter is referred to as a fourth non-display area.

The panel built-in gate driver built in the first non-display area is referred to as a first panel built-in gate driver 200a, and the panel built-in gate driver built in the second non- The data driver 300 connected to the third non-display area is referred to as a first data driver, and the data driver 300 connected to the fourth non-display area is referred to as a second data driver 200b. do.

The structure and functions of the first panel built-in gate driver 200a and the second panel built-in gate driver 200b are the same. Therefore, in the following, the present invention will be described by taking the first panel built-in gate 200a as an example.

The first panel built-in gate driver 200a receives the gate control signal generated by the timing controller, and sequentially outputs the scan signal to the gate lines using the gate control signal.

The first panel built-in gate driver 200a receives a first clock input from the timing controller through one side of the first panel built-in gate driver 200a and a second clock input from the other side of the first panel built- Wherein the first clock and the second clock are driven by a second clock input from the timing controller, and the first clock and the second clock have the same amplitude and period.

That is, the timing controller 400 outputs two clocks CLK1 and CLK2 having the same amplitude and period. The first one of the two identical clocks CLK1 is connected to one side of the first panel built-in gate driver 200a, i.e., the first data driver 300a adjacent to the first data driver 300 And the second clock CLK2 is input to the first panel built-in gate driver 200a through the other end of the first non-display area, that is, the fourth non- Is input to the gate driver 200a.

2, the first clock CLK1 is connected to a first clock transmission line (not shown) formed in a chip-on film (COF) or a tape carrier package (TCP) in which the first data driver 300 is mounted, May be input to the first panel built-in gate driver (200a) after being transferred to the panel (100) through the first panel built-in gate driver (210). However, the first clock CLK1 does not interrupt the chip-on-film (COF) or the tape carrier package (TCP) on which the first data driver 300 is mounted, May be transmitted from the timing controller 400 to the first panel built-in gate driver 200a through the first clock transmission line 210 directly connected to one side of the one-panel built-in gate driver 200a.

The second clock CLK2 is connected to the timing controller 300 and the second clock transmission line 220 directly connected to the other side of the first panel built-in gate driver 200a, as shown in FIG. 2 To the first panel built-in gate driver (200a) from the timing controller (400). However, the second clock transmission line 220 is connected to the first panel built-in gate driver 200a of the first non-display area in the same manner as the first clock transmission line 210 shown in FIG. The first panel built-in gate driver 200a may extend along the first non-display area to the other side of the first panel built-in gate driver 200a and may be connected to the first panel built-in gate driver 200a at the other side. That is, the second clock transmission line 220 may be formed of a general wire, a film, or a line-on-glass (LOG) form on the panel 100.

The specific internal configuration of the first panel built-in gate driver 200a will be described below with reference to FIGS. 3 and 4. FIG.

3 is a view showing a first embodiment of a panel built-in gate driver applied to a liquid crystal display device according to the present invention.

The first embodiment of the panel built-in gate driver applied to the liquid crystal display according to the present invention includes a plurality of stages 230 connected to each gate line, as shown in FIG.

As described above, the liquid crystal display device according to the present invention has a large area of 72 "or more and is driven by FHD and ultra-high resolution (UD class). Hereinafter, The present invention will be described as an example.

When the panel 100 is driven with ultra-high resolution (UD), 2160 gate lines are formed in the panel 100.

Accordingly, the first panel built-in gate driver 200a has 2160 stages (Stage 1 to Stage 2160), and from the stages, the first scan signals (VGOUTl) to the 2160th scan signals (VGOUT2160) .

The internal configuration and functions of the stage 230 can be configured in various forms according to current general technology, and a detailed description thereof will be omitted. The gate control signal input to the stage may be variously formed according to the internal structure and function of the stage 230 so that basic signals such as the clock CLK and the gate start signal VST) according to the present invention.

The first panel gate driver 200a may further include stages for dummy lines other than the stages directly connected to the gate lines.

First, the basic operation of the stage 230 will be described as follows.

That is, when the gate start signal VST is input to the first stage Stage 1 of the stages 230, the first stage Stage 1 starts driving. The first stage Vstage1 generates a first scan signal VGOUT1 using the clock CLK and the gate start signal VST and outputs the first scan signal VGOUT1 to the first gate line GL1 , And transmits the first scan signal to the second stage (Stgae). The second stage Stage 2 starts driving by the first scan signal VGOUT1 and then generates a second scan signal VGOUT2 by using the clock CLK and the gate start signal VST, 2 gate line GL2.

The above-described operation is repeated in the same manner from the third stage (Stage 3) to the 2160 stage (Stage 2160).

That is, the stages sequentially output the scan signal (VGOUT) to each gate line by using the clock (CLK) and the gate start signal (VST).

The first panel built-in gate driver 200a operates as described above. In order to generate the scan signal, the clock CLK used in each of the stages is transferred to the first stage Stage 1 (Stage 2160) as well as the 2160 stage (Stage 2160).

That is, in the panel built-in gate driver applied to the conventional liquid crystal display device, the clock CLK is input only to the first stage. However, in the present invention, the first stage Stage 1 and the 2160th stage ).

In addition, when the first panel built-in gate driver 200a includes the first stage (Stage 1) to the 2160 stage (Stage 2160), the first panel built-in gate driver 200a controls the timing controller 400) to the first stage (Stage 1) and the second clock (CLK 2) input from the timing controller to the n-th stage (Stage), and the first clock (CLK 1) CLK1 and the second clock CLK2 have the same amplitude and period.

In this case, the first clock line 241 through which the first clock is transmitted and the second clock line 242 through which the second clock is transmitted are connected to each other.

Accordingly, the clock substantially input to the 1078th stage (Stage 1088) to the 1082th stage (Stage 1082) arranged at an intermediate position among the first stage (Stage 1) through the 2160th stage (Stage 2160) (CLK1) and the second clock (CLK2). If the amplitudes of the first clock CLK1 and the second clock CLK2 are appropriately set in consideration of attenuation and delay in the first clock line 231 and the second clock line 242, The delay time between clocks actually input to the panel 100 can be reduced, so that a normal image can be output through the panel 100. [

That is, in the first embodiment of the panel built-in gate driver as described above, the first clock (CLK1) and the second clock (CLK2) output from the timing controller (400) The first clock line 241 to which the first clock CLK1 is inputted and the first clock line 241 to which the second clock CLK2 is input are input to the first stage Stage 1 and the last stage Stage 200a, 2 clock lines 242 are connected to each other.

4 is a view showing a second embodiment of a panel built-in gate driver applied to a liquid crystal display according to the present invention. In the following description, the same or similar contents as those described with reference to Figs. 2 and 3 are omitted or briefly described.

The second embodiment of the panel built-in gate driver applied to the liquid crystal display according to the present invention includes a plurality of stages 230 connected to each gate line, as shown in FIG.

The second panel built-in gate driver 200b is characterized in that, in order to generate the scan signal, a clock CLK used in each of the stages is supplied not only to the first stage Stage 1, Stage 2160) (where n is 2160).

In other words, when the first panel built-in gate driver 200a includes the first stage (Stage 1) to the nth stage (Stage 2160), the first panel built-in gate driver 200a controls the timing controller 400) to the first stage (Stage 1) and the second clock (CLK 2) input from the timing controller to the n-th stage (Stage), and the first clock (CLK 1) CLK1 and the second clock CLK2 have the same amplitude and period.

In the first panel built-in gate driver 200a, the first clock line 241 through which the first clock is transmitted is divided into the first stage (Stage 1) to the (n / 2) th stage And the second clock line 242 through which the second clock is transmitted is connected from the (n / 2) + 1 stage to the nth stage (Stage 1060).

In this case, in the conventional FHD-class liquid crystal display device in which the first clock CLK1 is input to the first stage (Stage 1) to the 1080th stage (Stage 1080) CLK) are the same as those in which the first to tenth stages are driven.

Also, in the conventional FHD-class liquid crystal display device in which the first clock CLK2 is input to the 1081st stage through the 2160th stage, CLK < / RTI > are sequentially driven by 1080 stages.

That is, in the second embodiment of the panel built-in gate driver as described above, the stages are driven in the same manner as the method in which the stages that have been applied to the conventional FHD-class liquid crystal display device are driven. Accordingly, the delay time between the clocks input to the 2160 stages can be reduced, so that a normal image can be output through the panel 100. [

In addition, in the second embodiment of the panel built-in gate driver as described above, the first clock (CLK1) and the second clock (CLK2) output from the timing controller (400) The first clock line 241 and the second clock CLK2 are inputted to the first stage Stage 1 and the last stage of the gate driver 200a and the first clock CLK1 is input, The input second clock lines 242 are separated from each other.

As described above with reference to FIG. 2, the liquid crystal display according to the present invention includes a first panel built-in gate driver 200a formed in the first non-display region and a second panel built- And a second panel built-in gate driver 200b.

That is, the liquid crystal display according to the present invention is built in the second non-display area of the panel 100 facing the first non-display area, And a second panel built-in gate driver (200b) driven by the same clocks and sequentially supplying a scan signal to the gate lines. The first panel built-in gate driver (200a) The two clocks CLK1 and CLK2 and the two clocks CLK3 and CLK4 input to the second panel built-in gate driver 200b have the same amplitude and period.

In this case, the second panel built-in gate driver 200b may have the same configuration as the first panel built-in gate driver 200a.

FIG. 5 is another diagram schematically showing a liquid crystal display device according to the present invention. In the following description, the same or similar contents as those described with reference to Figs. 2 to 4 are omitted or briefly described.

As described above, the liquid crystal display device according to the present invention has a large area of 72 inches or more and is driven by FHD and ultra-high resolution (UD class). In such a large-area high resolution liquid crystal display device, In each of the two opposing non-display areas of the panel 100, as well as the panel built-in gate driver is embedded in each of the two opposing non-display areas of the panel 100, 300a, 300b may be formed.

That is, as shown in FIG. 5, a large-area high-resolution liquid crystal display device according to the present invention includes a panel 100 in which pixels are formed at intersecting areas of data lines and gate lines, A first data driver 300a connected to the panel 100 in the third non-display area and supplying a data voltage to the data lines, a second data driver 300b for supplying a data voltage to the data lines 300a, A second data driver 300b connected to the panel 100 in the non-display area for supplying a data voltage to the data lines, a first timing controller 400a for driving the first data driver 300a, A second timing controller 400b for driving the second data driver 300b and a second timing controller 400b built in the first non-display area of the panel 100, A clock CLK1, A first panel built-in gate driver 200a which is driven by a second clock CLK2 inputted from the second timing controller 400b and sequentially supplies a scan signal to the gate lines, Display area of the first timing controller 400a and the third clock CLK3 input from the first timing controller 400a and the fourth clock CLK3 input from the second timing controller 400b, And a second panel built-in gate driver (200b) driven by a clock (CLK4) and sequentially supplying a scan signal to the gate lines, wherein the first to fourth clocks (CLK1 to CLK4) , The same amplitude and period.

The first timing controller 400a is mounted on the first main board 500a and receives a timing signal and input image data from the external system 600 to generate a gate control signal, do. The first timing controller 400a outputs the first clock CLK1 and the third clock CLK3 of the gate control signals to the first internal gate driver 210 and the second internal gate driver 210 And inputs them to the first stages Stage 1.

The second timing controller 400b is mounted on the second main board 500b and receives a timing signal and input image data from the external system 600 to generate a gate control signal, do. The second timing controller 400b outputs the second clock CLK2 and the fourth clock CLK4 of the gate control signals to the first internal gate driver 210 and the second internal gate driver 210 Th stage (Stage 2160).

The first gate driver 210 and the second gate driver 220 may be formed as shown in FIG. 3 or may be formed as shown in FIG.

That is, in the first panel built-in gate driver 200a, the first clock line through which the first clock CLK1 is transmitted and the second clock line through which the second clock is transmitted are connected to each other, In the panel built-in gate driver 200b, the third clock line through which the third clock CLK3 is transmitted and the fourth clock line through which the fourth clock CLK4 is transmitted may be connected to each other.

When each of the first panel built-in gate driver 200a and the second panel built-in gate driver 200b is comprised of the first stage to the nth stage, the first panel built-in gate driver 200a The first clock line through which the first clock CLK1 is transmitted is connected from the first stage Stage 1 to the nth stage Stage 2 and the second clock CLK2 is transmitted The second clock line is connected from the (n / 2) +1 stage to the n-th stage. In the second panel built-in gate driver 200b, The third clock line through which the third clock CLK3 is transmitted is connected from the first stage Stage 1 to the nth stage Stage 2 and the fourth clock CLK4 is transmitted. 4 clock line may be connected from the (n / 2) +1 stage (Stage (n / 2) +1) to the nth stage.

That is, the method of driving a liquid crystal display according to the present invention configured as described above includes the steps of generating a gate control signal, a data control signal, and image data using the timing signals input from the external system 600, Transmitting a clock included in the gate control signal to each of two different stages in a panel built-in gate driver built in the panel 100, transmitting a scan signal generated using the two clocks to the panel Sequentially outputting the data voltages generated by using the data control signal and the image data to the gate lines formed in the data lines 100 while the scan lines are being output to the gate lines, And a step of outputting the output signal.

Hereinafter, the contents described above will be briefly summarized.

One of the biggest problems when a panel built-in gate driver (GIP) is used in a UD-class panel is that since a cap / resistance to a clock (CLK) is large, . Therefore, even if the design of the panel built-in gate driver is optimized, there is a high possibility that defects such as color mixing may occur.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above-mentioned problems, and has an object of providing a liquid crystal display device which inputs a clock CLK at the top and bottom of a panel in a dual manner and reduces a load applied to the clock CLK in half, To improve the deterioration. As a result of the simulation, it was confirmed that the rising and falling time were improved by 10 to 12% compared to the conventional case. Also, since the high voltage of the Q node of each stage rises by 1.0 V or more compared to the conventional one, the rising time is improved by about 15%, and the defect due to the shortage of charging can be improved.

Particularly, in the present invention, as in the second embodiment, the clock CLK is inputted as the upper and lower duals, the intermediate 1 to 1080 and the 1081 to 2160 stages are separated and a load applied to the clock CLK The panel load can be reduced to half by separating the drive itself and improving the delay deterioration of the gate output.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: panel 200a, 200b: gate driver
300, 300a, 300b: Data driver 400, 400a, 400b: Timing controller
500, 500a, 500b: main board 600: external system

Claims (10)

A panel in which pixels are formed for each intersection of the data lines and the gate lines;
A data driver for supplying a data voltage to the data lines;
A timing controller for driving the data driver; And
And a first panel built-in gate driver which is embedded in a first non-display area of the panel and is driven by the same clocks input from the timing controller to sequentially supply a scan signal to the gate lines, Device. The method according to claim 1,
Wherein the first panel built-in gate driver comprises:
Wherein the first panel-integrated gate driver is driven by a first clock input from the timing controller through one side of the first panel built-in gate driver and a second clock input from the timing controller through the other side of the first panel-
Wherein the first clock and the second clock have the same amplitude and period. The method according to claim 1,
Wherein the first panel built-in gate driver comprises:
Wherein the first stage to the n < th >
A first clock input from the timing controller to the first stage, and a second clock input from the timing controller to the n-th stage,
Wherein the first clock and the second clock have the same amplitude and period. The method of claim 3,
In the first panel built-in gate driver,
Wherein the first clock line through which the first clock is transmitted and the second clock line through which the second clock is transmitted are connected to each other. The method of claim 3,
In the first panel built-in gate driver,
The first clock line through which the first clock is transmitted is connected from the first stage to the n / 2 stage,
And the second clock line through which the second clock is transmitted is connected from the (n / 2) +1 stage to the n-th stage. The method according to claim 1,
And a second non-display region which is included in a second non-display region facing the first non-display region of the panel and is driven by two other identical clocks input from the timing controller, And a second panel built-in gate driver for supplying the second panel-
Wherein the two clocks input to the first panel built-in gate driver and the two clocks input to the second panel built-in gate driver have the same amplitude and period. A panel in which pixels are formed for each intersection of the data lines and the gate lines;
A first data driver coupled to the panel in a third non-display area of the panel, the data driver supplying a data voltage to the data lines;
A second data driver connected to the panel in a fourth non-display area facing the third non-display area of the panel, the data driver supplying a data voltage to the data lines;
A first timing controller for driving the first data driver;
A second timing controller for driving the second data driver;
A first timing controller which is incorporated in a first non-display area of the panel and is driven by a first clock input from the first timing controller and a second clock input from the second timing controller, A first panel built-in gate driver for supplying a signal; And
And a second timing controller which is built in a second non-display area facing the first non-display area of the panel and is driven by a third clock input from the first timing controller and a fourth clock input from the second timing controller And a second panel built-in gate driver for sequentially supplying a scan signal to the gate lines,
Wherein the first clock to the fourth clocks have the same amplitude and period. 8. The method of claim 7,
In the first panel built-in gate driver, the first clock line through which the first clock is transmitted and the second clock line through which the second clock is transmitted are connected to each other,
Wherein the third clock line through which the third clock is transmitted and the fourth clock line through which the fourth clock is transmitted are connected to each other in the second panel built-in gate driver. 8. The method of claim 7,
Wherein each of the first panel built-in gate driver and the second panel built-in gate driver comprises a first stage to an n-th stage,
In the first panel built-in gate driver, the first clock line through which the first clock is transmitted is connected from the first stage to the n / 2 stage, and the second clock line through which the second clock is transmitted, (N / 2) +1 stage to the n-th stage,
In the second panel built-in gate driver, the third clock line through which the third clock is transmitted is connected from the first stage to the n / 2 stage, and the fourth clock line through which the fourth clock is transmitted, And the (n / 2) +1 stage is connected to the n-th stage. Generating a gate control signal, a data control signal, and image data using timing signals input from an external system;
Transmitting a clock included in the gate control signal to each of two different stages in a panel built-in gate driver built in a panel;
Sequentially outputting a scan signal generated by using the two clocks to gate lines formed on the panel; And
And outputting the data voltage generated by using the data control signal and the image data to the data lines while the scan signal is output to the gate line.

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