KR20140112649A - Solar cell - Google Patents

Abstract

A solar cell, according to the present invention, comprises a semiconductor substrate containing impurities of a first conductive type; a rear electric field unit which is arranged on the back surface of the substrate and contains impurities of the first conductive type; and a first electrode connected to the rear electric field unit. The rear electric field unit includes a first intrinsic rear electric field layer which comes into contact with the back surface of the substrate and does not contain impurities; a second intrinsic rear electric field layer which comes into contact with the back surface of the first rear electric field layer and does not contain impurities; and a third rear electric field layer of the first conductive type which comes into contact with the back surface of the second rear electric field layer and contains relatively high concentration of impurities of the first conductive type compared to the substrate. The first rear electric field layer can be formed with the amorphous silicon, and the second rear electric field layer and the third rear electric field layer can be formed with amorphous silicon carbide.

Description

Solar cell {SOLAR CELL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell, and more particularly, to a heterojunction solar cell.

With the recent depletion of existing energy resources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells produce electric energy from solar energy, and they are attracting attention because they have abundant energy resources and there is no problem about environmental pollution.

A typical solar cell includes a substrate and an emitter portion that forms a p-n junction with the substrate, and generates a current by using light incident through one side of the substrate.

In recent years, a solar cell having a heterojunction structure constituting an electric field portion using an amorphous silicon (a-Si) layer has been developed.

SUMMARY OF THE INVENTION The present invention provides a solar cell with improved efficiency.

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate containing an impurity of a first conductivity type; A back electrometer located on a back surface of the substrate and containing an impurity of the first conductivity type; And a first electrode connected to the backside electrical portion.

The rear electric field portion includes a first rear front layer in intrinsic contact with the rear surface of the substrate and containing no impurities, a second back front layer in intimate contact with the rear surface of the first rear front layer and containing no impurities, 2 third backside front layer of a first conductivity type that contacts the backside of the backside front layer and contains impurities of the first conductivity type at a higher concentration than the substrate.

The second rear front layer and the third rear front layer may each be formed of a material having an energy band gap higher than that of the first rear front layer.

As an example, the first back-front layer may have an energy band gap of 1.70 to 1.85, and the second back-front layer and the third back-front layer may have an energy band gap of 1.85 to 2.08.

The second rear front layer and the third rear front layer may be formed of the same material.

As an example, the first rear whole layer may be formed of amorphous silicon, and the second rear front layer and the third rear front layer may be formed of amorphous silicon carbide, respectively.

The entire front surface of the first electrode can be in direct contact with the third rear front layer.

The first rear whole layer is preferably formed to a thickness of 3 nm or less, the second rear whole layer is preferably formed to a thickness of 6 nm to 15 nm, and the third rear whole layer is formed to a thickness of 3 nm to 10 nm It is preferable that it is formed to have a thickness.

The solar cell may further include a second electrode connected to the emitter portion and an emitter portion containing an impurity of the second conductivity type opposite to the first conductive type, and a dielectric layer disposed on the front surface of the emitter portion.

Here, the emitter portion may be located on the front surface of the substrate, and the second electrode may be located on the front surface of the emitter portion.

The second electrode may further include a plurality of first finger electrodes extending in a first direction and a plurality of first bus bar electrodes extending in a second direction orthogonal to the first direction.

The first bus bar electrode may be physically connected to the first finger electrode and the back electric field portion may be located on the entire rear surface of the substrate.

Alternatively, the emitter and the second electrode may be located on the rear surface of the substrate, and the dielectric layer may be positioned on the front surface of the semiconductor substrate.

In the conventional heterojunction solar cell, both the intrinsic thin film and the doped thin film constituting the back electric field portion are formed of amorphous silicon. Since the amorphous silicon has an energy band gap of approximately 1.70 to 1.85, the open voltage (Voc) and the fill factor , Fill Factor) can not be effectively increased.

However, in the present invention, the intrinsic thin film constituting the passivation layer of the rear electric field portion is formed of a double thin film of an intrinsic amorphous silicon layer and an intrinsic amorphous silicon carbide layer, and the doped thin film is doped with impurities of the same conductivity type as the substrate And is formed of an amorphous silicon carbide layer.

Therefore, since the difference? Ec of the valence band and the difference? Ev of the conduction band are increased as compared with the conventional one, the passivation property of the rear field portion is improved and the flow of electrons and holes is smoothly performed. Also, since the first electrode is in direct contact with the microcrystalline silicon carbide layer of the first conductivity type, the contact resistance of the first electrode is reduced, thereby increasing the fill factor. Thus, the efficiency of the solar cell is improved.

1 is a partial perspective view of a solar cell according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the solar cell shown in FIG. 1 cut along the line II-II.
Fig. 3 is an enlarged view of the portion A in Fig. 2. Fig.
4 is a band diagram at the interface of the rear surface electric field portion formed on the n-type substrate.
5 is a band diagram at the interface of the rear surface electric field portion formed on the p-type substrate.
6 to 9 are views for explaining an example of a method of manufacturing a solar cell according to the present invention.
10 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It is to be understood that the present invention is not intended to be limited to the specific embodiments but includes all changes, equivalents, and alternatives falling within the spirit and scope of the present invention.

In describing the present invention, the terms first, second, etc. may be used to describe various components, but the components may not be limited by the terms. The terms may only be used for the purpose of distinguishing one element from another.

For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The term "and / or" may include any combination of a plurality of related listed items or any of a plurality of related listed items.

Where an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, but other elements may be present in between Can be understood.

On the other hand, when it is mentioned that an element is "directly connected" or "directly coupled" to another element, it can be understood that no other element exists in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions may include plural expressions unless the context clearly dictates otherwise.

In the present application, the terms "comprises", "having", and the like are used interchangeably to designate one or more of the features, numbers, steps, operations, elements, components, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, or combinations thereof.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Terms such as those defined in commonly used dictionaries can be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are, unless expressly defined in the present application, interpreted in an ideal or overly formal sense .

In addition, the following embodiments are provided to explain more fully to the average person skilled in the art. The shapes and sizes of the elements in the drawings and the like can be exaggerated for clarity.

Embodiments of the present invention will now be described with reference to the accompanying drawings.

2 is a cross-sectional view taken along a line II-II of the solar cell shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line II-II in FIG. This is an enlarged view.

FIG. 5 is a band diagram at the interface of the rear surface electric field portion formed on the p-type substrate, and FIGS. 6 to 9 are band diagrams at the interface of the rear surface electric field portion formed on the n- Fig. 3 is a view for explaining an example of a method for manufacturing a semiconductor device.

As shown in the drawing, a solar cell according to an embodiment of the present invention includes a substrate 110, an emitter 120, a first dielectric layer 130 located on a front surface of the substrate 110, The second dielectric layer 180 located on the back surface of the rear electric field portion 170 and the rear electric field portion 170 located on the back surface of the rear electric field portion 110, And a second electrode 140 connected to the first electrode 150 and the emitter section 120.

Hereinafter, "front surface" refers to a surface facing upward in the accompanying drawings, and "rear surface " refers to a surface facing downward in the accompanying drawings.

The substrate 110 is a semiconductor substrate 110 made of a crystalline silicon containing an impurity of a first conductivity type, for example, an n-type conductivity type. At this time, the silicon may be single crystal silicon or polycrystalline silicon.

Since the substrate 110 has an n-type conductivity type, the substrate 110 contains impurities of pentavalent elements such as phosphorus (P), arsenic (As), antimony (Sb), and the like.

Alternatively, however, the substrate 110 may be of the p-type conductivity type and may be made of a semiconductor material other than silicon. When the substrate 110 has a p-type conductivity type, the substrate 110 may contain an impurity of a trivalent element such as boron (B), gallium, indium, or the like.

Hereinafter, a case where the substrate 110 has an n-type conductivity type will be described as an example.

Such a substrate 110 has a texturing surface whose surface is textured. More specifically, the substrate 110 is formed with a textured surface having a front surface on which the emitter section 120 is located and a back surface located on the opposite side of the front surface.

The emitter portion 120 located on the front surface of the substrate 110 is an impurity portion having a second conductivity type opposite to the conductivity type of the substrate 110, for example, a p-type conductivity type, Lt; RTI ID = 0.0 > 110 < / RTI >

Due to the built-in potential difference due to the pn junction, the electron-hole pairs, which are charges generated by the light incident on the substrate 110, are separated into electrons and holes, electrons move toward the n- Moves toward the p-type.

Therefore, the separated electrons move toward the substrate 110 and the separated holes move toward the emitter part 120 because the substrate 110 is n-type and the emitter part 120 is p-type.

Since the emitter section 120 has a p-type conductivity type, the emitter section 120 is formed by doping an impurity of a trivalent element such as boron (B), gallium (Ga), indium (In) .

Unlike the present embodiment, when the substrate 110 has a p-type conductivity type, the emitter portion 120 has an n-type conductivity type. In this case, the separated holes move toward the substrate 110, and the separated electrons move toward the emitter section 120.

When the emitter section 120 has an n-type conductivity type, the emitter section 120 dopes impurities of pentavalent elements such as phosphorus (P), arsenic (As), antimony (Sb) .

A first region of the emitter section 120 in contact with the second electrode 140 in the emitter section 120 and a second region of the emitter section 120 that is not in contact with or overlapped with the second electrode 140 The impurity doping concentrations may be different.

For example, the first region of the emitter portion 120, which overlaps and contacts the second electrode 140 among the emitter portions 120 formed on the front surface of the substrate 110, has a relatively high doping concentration of the impurity, And the second region of the emitter section 120 which is not in contact with or overlapped with the second electrode 140 may be formed as a low concentration emitter section having a lower doping concentration than that of the high concentration emitter section.

The first dielectric layer 130 formed on the emitter portion 120 may be formed of a material having a negative fixed charge such as aluminum oxide (AlO _x ) or yttrium oxide (Y ₂ O ₃ ) Lt; RTI ID = 0.0 > 130a < / RTI >

The aluminum oxide (AlO _x ) or the trisium oxide (Y ₂ O ₃ ) forming the first front dielectric layer 130a has a chemical passivation property due to the low interface trap density and a negative charge The field-effect passivation characteristics are excellent. It also has excellent stability, moisture permeability and abrasion resistance.

Therefore, the recombination speed of the charges on the surface of the emitter section 120 can be reduced to improve the efficiency of the solar cell and improve the long-term reliability.

The first dielectric layer 130 further includes a second front dielectric layer 130b and a third front dielectric layer 130c located on the first front dielectric layer 130a and a third front dielectric layer 130c further comprises a second front dielectric layer 130c, 130b.

The second front dielectric layer 130b is made of silicon nitride (SiN _x ) having a positive charge and the third front dielectric layer 130c is made of silicon oxide (SiOx) having a positive charge .

The second front dielectric layer 130b and the third front dielectric layer 130c reduce the reflectivity of light incident through the front surface of the substrate 110 and increase the selectivity of a specific wavelength region to increase the efficiency of the solar cell.

The first dielectric layer 130 includes a plurality of openings OP1 that are formed in a line type or a spot type and expose a part of the emitter layer 120. [

The second electrode 140 is formed on the emitter 120 exposed through the opening OP1.

The second electrode 140 is located on the emitter section 120 of the front surface of the substrate and is electrically and physically connected to the emitter section 120.

The second electrode 140 includes a plurality of second finger electrodes 141 and a plurality of second bus bar electrodes 143.

At this time, the plurality of second finger electrodes 141 extend in the first direction shown in FIG. 1, that is, in the X-X 'direction, and extend in parallel to the adjacent second finger electrodes 141 at regular intervals.

The plurality of second finger electrodes 141 collect charge, for example, holes, which have migrated toward the emitter section 120.

The plurality of second finger electrodes 141 are made of Ni, Cu, Sn, Zn, In, Ti, Au, and combinations thereof. And at least one conductive material selected from the group consisting of

The plurality of second finger electrodes 141 may be formed by a screen printing method for printing and firing a conductive paste containing a conductive material, or may be formed using a plating process using a seed layer. The second finger electrode 141 formed by the plating process includes a plating layer 141a.

The plurality of second bus bar electrodes 143 are located on the same layer as the plurality of second finger electrodes 141 on the emitter section 120 and electrically connect the plurality of second finger electrodes 141 to each other.

At this time, the plurality of second bus bar electrodes 143 are elongated along the second direction orthogonal to the first direction, that is, the second direction (YY 'direction) shown in FIG. 1, And collects the charges collected and moved by the plurality of second finger electrodes 141 and outputs the collected charges to an external device.

The second bus bar electrode 143 may be formed using the same material as the second finger electrode 141 according to the same method.

The entire rear surface of the second electrode 140 having such a configuration is in direct contact with the emitter section 120.

The backside electrical portion 170 located on the backside of the substrate 110 includes a first backside front layer 170a in contact with the semiconductor substrate.

The first rear whole front layer 170a is formed of an intrinsic amorphous silicon (i a-Si) layer 170a containing no impurities.

Since the intrinsic amorphous silicon layer 170a is capable of uniform growth and stable growth as compared with the silicon carbide layer having many defects in the film, the intrinsic amorphous silicon layer 170a has an excellent interfacial characteristic.

The intrinsic amorphous silicon layer 170a can reduce the recombination of charges generated at the interface due to excellent interface characteristics as described above, thereby suppressing the decrease in the open-circuit voltage (Voc).

The amorphous silicon has an energy band gap of approximately 1.70 to 1.85, and thus can not effectively increase the open-circuit voltage (Voc) and the fill factor (FF).

Thus, to increase the open-circuit voltage and the fill factor, the backside electrical section 170 of the present embodiment further includes a second backside front layer 170b contacting the backside of the first backside front layer 170a, The back front layer 170b is formed of a material having a high energy band gap (1.85 to 2.05), such as an amorphous silicon carbide layer (a-SixCy), as compared with the amorphous silicon layer forming the first rear front layer 170a .

At this time, the second rear front layer 170b together with the first rear front layer 170a does not contain any impurities to serve as a passivation layer.

Therefore, in this embodiment, the first rear rear front layer 170a formed of the intrinsic amorphous silicon layer 170a and the second rear front layer 170b formed of the intrinsic amorphous silicon carbide layer 170b serve as a passivation layer .

The backside electrical section 170 of the present embodiment further includes a third rear front layer 170b contacting the rear side of the second rear front layer 170b and a third rear front layer 170c further comprises a second rear front layer 170b, For example, amorphous silicon carbide (a-SixCy) layer.

The third rear front layer 130c contains impurities of the first conductivity type, for example, n-type, at a higher concentration than the substrate 110. [

Therefore, the n-type amorphous silicon carbide layer (n + a-SixCy) 170c containing the n-type impurity at a higher concentration than the substrate 110 acts as a doping layer in the heterojunction structure.

At this time, the "x" value and "y" in the amorphous silicon carbide layer (a-SixCy) constituting the second rear whole front layer 170b and the third rear front layer 170c correspond to the first electrode 150) having a band gap characteristic suitable for the band gap.

That is, the silicon content (x) and the carbon content (y) of the amorphous silicon carbide layer (a-SixCy) constituting the second rear whole front layer 17b and the third rear front layer 170c are appropriately adjusted, The entire layer 170b and the third rear whole layer 170c may have an energy band gap of 1.85 to 2.05.

The intrinsic amorphous silicon layer 170a may be formed on the entire rear surface of the substrate 110 by Plasma-enhanced chemical vapor deposition (PECVD), and the intrinsic amorphous silicon carbide layer 170b may be formed on the plasma- The n-type amorphous silicon carbide layer 170c may be formed on the entire back surface of the intrinsic amorphous silicon layer 170a by Plasma-enhanced chemical vapor deposition (PECVD). PECVD) on the entire rear surface of the intrinsic amorphous silicon carbide layer 170b.

The thickness T2 of the intrinsic amorphous silicon carbide layer 170b is formed larger than the thickness T3 of the n-type amorphous silicon carbide layer 170c and the thickness T3 of the n-type amorphous silicon carbide layer 170c is larger than the thickness T3 of the intrinsic amorphous silicon carbide layer 170c. Is preferably formed to be larger than the thickness T1 of the silicon layer 170a.

For example, the intrinsic amorphous silicon carbide layer 170b is formed to a thickness T2 of 6 to 15 nm, and the n-type amorphous silicon carbide layer 170c is formed to a thickness of 3 to 10 nm in the intrinsic silicon carbide layer The intrinsic amorphous silicon layer 170a is formed to have a thickness T3 that is thinner than the thickness T3 of the n-type amorphous silicon carbide layer 170c within a range of 3 nm or less T1).

The rear electric field portion 170 having such a three-layer structure performs a back electric field function, so that a potential barrier that generates a potential difference with the substrate 110 can be formed due to a difference in impurity concentration from the substrate 110.

Accordingly, when the substrate 110 has the n-type conductivity type and the emitter section 120 has the p-type conductivity type, the rear electric section 170 forms an n-type electric field higher than the substrate 110, Electrons that are the majority carriers of the substrate 110 can be moved more easily to the second electrode 150 through the rear electric section 170 and holes that are the majority carriers of the emitter section 120 move toward the second electrode 150 As shown in Fig.

In addition, since the rear electric section 170 includes an amorphous silicon material and an amorphous silicon carbide material, the passivation function can be performed together with the rear electric field function described above.

FIG. 4 is a band diagram at the interface of the rear surface electric field portion formed on the n-type substrate, in which the intrinsic thin film constituting the passivation layer of the conventional and rear surface electric field portions, both of the intrinsic thin film and the doped thin film constituting the rear electric field portion are formed of amorphous silicon, An amorphous silicon layer and an intrinsic amorphous silicon carbide layer, and the doped thin film is formed of an amorphous silicon carbide layer containing impurities of the same conductivity type as that of the substrate at a higher concentration than the substrate.

As described above, since the energy band gap of the second rear front layer 170b and the third rear front layer 170c is higher than that of the first rear front layer 170a in the rear electric circuit 170 of the present embodiment, As shown in Fig. 4, the difference DELTA Ev of the conduction band at the interface of the rear electric section 170 of the present embodiment increases compared to the difference DELTA Ev 'of the conduction band at the interface of the conventional rear electric field section.

5, in the case of a p-type substrate, the difference (DELTA Ec) between the valence band (DELTA Ec) and the conduction band of the valence band is different from the difference DELTA Ec 'between the valence band and the difference DELTA Ev' Respectively.

Therefore, the rear electric section 170 of the present embodiment has an excellent passivation characteristic and increases the open-circuit voltage of the device, so that the efficiency of the solar cell is improved as compared with the conventional case.

The second dielectric layer 180 located on the rear surface of the rear electric 170 includes a first rear dielectric layer 180a and a second rear dielectric layer 180a having a positive positive charge opposite to that of the rear electric conductor 170, 180b.

More specifically, the first rear dielectric layer 180a is formed of the same material as the second front dielectric layer 130b, e.g., silicon nitride (SiNx), and the second rear dielectric layer 180b is formed of the same material as the third front dielectric layer 130c For example, a silicon oxide film (SiOx).

Since the silicon nitride film forming the first rear dielectric layer 180a can be formed at a lower processing temperature (between 300 ° C and 400 ° C) than the silicon oxide film, the amorphous silicon (a-Si The thermal damage to the backside electrical < RTI ID = 0.0 > 170 < / RTI >

The first and second rear dielectric layers 180a and 180b reduce the reflectivity of light incident through the back surface of the substrate 110 and increase the selectivity of a specific wavelength region to increase the efficiency of the solar cell.

The second dielectric layer 180 is formed in a planar shape of a line type or a spot type to form a plurality of openings OP2 (not shown) exposing a part of the rear electric section 170, in particular, a part of the n-type amorphous silicon carbide layer 170c. ).

At this time, the interval between the plurality of openings OP2 is formed to be 100 mu m to 500 mu m.

The reason for defining the interval D1 between the plurality of openings OP2 is that when the laser beam is irradiated on the substrate 110 to form the opening OP2, the interval D1 between the openings becomes excessively narrow The area of the substrate 110 irradiated with the laser beam is excessively increased to deteriorate the characteristics of the substrate 110. If the space D1 between the openings is excessively large, ) Is lowered.

The first electrode 150 is formed on the n-type amorphous silicon carbide layer 170c exposed through the opening OP2.

The entire surface of the first electrode 150 directly contacts the n-type amorphous silicon carbide layer 170c and includes a plurality of first finger electrodes 151 and a plurality of first bus bar electrodes 153.

The plurality of first finger electrodes 151 extend in the same first direction X-X 'as the plurality of second finger electrodes 141 and the first bus bar electrode 153 extends to the second bus bar electrode 143 And the first bus bar electrode 153 is located at a position facing the second bus bar electrode 143. The first bus bar electrode 153 is located at a position facing the second bus bar electrode 143. [

The first bus bar electrode 153 is connected to the interconnector in the same manner as the second bus bar electrode 143 and outputs a carrier collected from the substrate 110 to the first finger electrode 151 to an external device.

The interval between the first finger electrodes 151 may be larger than the interval between the second finger electrodes 141.

The first electrode 150 may be formed using a plating method having a relatively lower process temperature than the screen printing method, like the second electrode 140.

In this case, the thermal damage to the film of the rear electric section 170 including the amorphous silicon (a-Si) material is minimized, so that the passivation function of the rear electric section 170 can be prevented from deteriorating.

Since the first finger electrode 151 and the first bus bar electrode 153 are in direct contact with the n-type amorphous silicon carbide layer 170c, the contact resistance of the first electrode is reduced, and thus the fill factor is increased.

When a solar cell having such a configuration is irradiated with light and is incident on the semiconductor substrate 110 through the first dielectric layer 130 and the emitter section 120, electron-hole pairs are generated in the semiconductor substrate 110 by light energy . At this time, the reflection loss of the light incident on the substrate 110 is reduced by the first dielectric layer 130, and the amount of light incident on the substrate 110 is increased.

The electron-hole pairs are separated from each other by the pn junction of the substrate 110 and the emitter section 120, and the separated holes move toward the emitter section 120 having the p-type conductivity type, To the substrate 110 having the conductive type.

The electrons moved toward the emitter section 120 are collected in the second bus bar electrode 143 through the second finger electrode 141 and electrons moved toward the substrate 110 pass through the rear electric section 170 1 finger electrodes 151 and then transferred to the first bus bar electrode 153. [

Accordingly, when the second bus bar electrode 143 of one of two neighboring solar cells is connected to the first bus bar electrode 153 of another solar cell through an inter-connector, a current flows, Power.

Since the first electrode 150 located on the rear surface of the substrate 110 is formed in the same or similar structure as the second electrode 140 located on the front surface of the substrate 110, The light can be incident on the rear surface of the light source. Therefore, the solar cell having the above-described structure can be used as a double-sided light receiving type solar cell.

The solar cell according to the present invention has a three-layer structure of the intrinsic amorphous silicon layer 170a, the intrinsic amorphous silicon carbide layer 170b and the n-type amorphous silicon carbide layer 170c, And performs the back surface electric field function and the passivation function together.

The rear electric conductor 170 of this structure is a carrier which is recombined by a dangling bond near the rear side of the substrate 110 when electrons which are the majority carriers of the substrate 110 move to the rear side of the substrate 110 The magnitude of the dark current (Jo) causing the recombination of carriers can be further reduced, and electrons, which are the majority carriers of the substrate 110, can be transmitted through the rear electric section 170 It is possible to further prevent the positive holes, which are the majority carriers of the emitter section 120, from moving toward the first electrode 150, while moving to the first electrode 150 more easily.

Here, the dark current Jo means a current value that causes recombination of carriers. Therefore, as the dark current Jo increases, the amount of recombination of the carriers increases. As a result, the short circuit current Jsc of the solar cell decreases and the efficiency of the solar cell decreases.

That is, the passivation effect increases as the dark current (Jo) decreases, and the passivation effect decreases as the dark current (Jo) increases. Therefore, as the dark current (Jo) decreases, the solar cell efficiency may be improved.

Since the rear electric field portion 170 includes the n-type amorphous silicon carbide layer 170c, the carrier moving in the direction from the substrate 110 toward the first electrode 150 is more smoothly moved.

A method of manufacturing a solar cell having such a structure will be described with reference to Figs. 6 to 9. Fig.

First, as shown in Fig. 6, an emitter section 120 containing a p-type impurity is formed on the entire surface of a substrate 110 containing an n-type impurity.

Next, as shown in Fig. 7, an intrinsic amorphous silicon layer 170a, an intrinsic amorphous silicon carbide layer 170b and an n-type amorphous silicon carbide layer 170c are sequentially formed on the back surface of the substrate 110. Next, as shown in Fig.

8, aluminum oxide is deposited on the entire surface of the emitter section 120 to form a first front dielectric layer 130a, and silicon nitride, which can be deposited at a lower process temperature than silicon oxide, A second front dielectric layer 130b is deposited over the front dielectric layer 130a and a silicon oxide is deposited over the second front dielectric layer 130b to enable deposition at a higher process temperature than silicon nitride, 130c.

The first rear dielectric layer 180a of the second dielectric layer 180 located on the rear surface of the n-type amorphous silicon carbide layer 170c is formed simultaneously with the second front dielectric layer 130b and the second rear dielectric layer 180b, Is formed simultaneously with the third front dielectric layer 130c.

9, a plurality of openings OP1 are formed in the first dielectric layer 130 located on the front surface of the substrate 110 by laser ablation, A plurality of openings OP2 are formed in the second dielectric layer 180 located on the rear side using laser ablation.

Thereafter, the second electrode 130 is formed in the emitter section 120 exposed by the opening OP1 and the n-type amorphous silicon carbide layer 170c exposed by the opening OP2 The first electrode 140 is formed to manufacture the solar cell shown in FIG.

Hereinafter, a solar cell according to another embodiment of the present invention will be described with reference to FIG. The solar cell described in this embodiment relates to a rear-surface solar cell having a heterojunction structure.

As shown in the drawing, the solar cell according to the present embodiment includes a substrate 210, a front electric part 260 located on the front surface of the substrate 210, a first dielectric layer 230 located on the front electric part 260, A plurality of emitter regions 220 located on the rear surface of the substrate 210, a plurality of rear electric parts 270 located on the rear surface of the substrate 210 and spaced apart from the plurality of emitter portions 220, A plurality of first auxiliary electrodes 251 and a plurality of first auxiliary electrodes 251 and a plurality of second auxiliary electrodes 251 located on the rear surfaces of the plurality of emitter portions 220, And a plurality of first main electrodes 252 and a plurality of second main electrodes 242 located on the second auxiliary electrodes 241, respectively.

The first auxiliary electrode 251 and the first main electrode 252 formed on the first auxiliary electrode 251 form the first electrode 250 and the second auxiliary electrode 241 and the second main electrode 242 The second electrode 240 is formed.

The substrate 210 may be a semiconductor substrate of a first conductivity type, for example, a semiconductor such as silicon of n-type conductivity type.

However, the substrate 210 may be of the p-type conductivity type and may be made of a semiconductor material other than silicon.

In the solar cell of this embodiment, the rear surface of the substrate 210 has a flat surface instead of the textured surface. Here, the flat surface refers to a surface on which a plurality of convex portions or concave portions are not formed.

As a result, the components located on the rear surface of the substrate 210 are more uniformly and stably formed in close contact with the rear surface of the substrate 210, The contact resistance is reduced. Alternatively, however, the rear surface of the substrate 210 may also have a textured surface, such as a front surface, which is an uneven surface.

The front electrical part 260 located on the front side of the substrate 210 may include three layers arranged in the reverse order of the rear electrical part 170 shown in FIG.

For example, although not specifically shown, the front electrical portion 260 includes an intrinsic amorphous silicon layer in contact with the front surface of the substrate 210, an intrinsic amorphous silicon carbide layer in contact with the front surface of the intrinsic amorphous silicon layer, And an n-type amorphous silicon carbide layer in contact with the front surface of the layer.

At this time, the front electric part 260 may be located entirely on the front surface of the substrate 210 or may be positioned on the front surface of the substrate 210 except the edge part of the front surface of the substrate 210.

The front electric field portion 260 having such a configuration forms a potential barrier due to a difference in impurity concentration from the substrate 210, thereby performing a front electric field function which hinders the hole movement toward the front surface of the substrate 210. Therefore, a front field effect is obtained in which the holes moving toward the front side of the substrate 210 by the front electric field portion 260 are returned to the rear side of the substrate 210 by the potential barrier, The output amount of the holes output to the external device through the rear surface increases and the amount of charges lost due to recombination or defects on the front surface of the substrate 210 decreases.

In addition, due to the energy band gap difference due to the heterojunction between the front electric field portion 260 and the substrate 210, that is, the energy band gap difference between the crystalline silicon and the amorphous silicon, in potential difference is increased to increase the open-circuit voltage (Voc) of the solar cell and the fill factor of the solar cell is improved.

The front electric field part 260 performs a passivation function as well as a front electric field function.

The first dielectric layer 230 located on the front electric field 260 has the same structure and functions as the first dielectric layer 130 according to the embodiment of FIG. 1, so that a detailed description of the first dielectric layer 230 It is omitted.

A second rear front layer 270b formed of a first rear front layer 270a formed of an intrinsic amorphous silicon layer 270a and an intrinsic amorphous silicon carbide layer 270b is formed on the rear surface of the substrate 210, do.

Accordingly, the first rear front layer 270a and the second rear front layer 270b function as a passivation layer.

In this embodiment, the rear electric section 270 includes a first rear front layer 270a and a second rear front layer 270b, and a third rear front layer 270b located only in a part of the second rear front layer 270b. Layer 270c and the third rear front layer 270c are formed of an amorphous silicon carbide layer containing impurities of a first conductivity type, for example, n-type, in a higher concentration than the substrate 210. [

 The third rear front layer 270c is spaced apart from the rear side of the substrate 210 in a predetermined direction.

The plurality of emitter portions 220 are spaced apart from one another in a predetermined direction in the rear surface of the substrate 210 and are located in a space between the third rear front layer 270c.

Thus, the plurality of emitter portions 220 and the plurality of third rear front layers 270c are alternately located on the back surface of the substrate 210. [

Each emitter portion 220 is an impurity portion having a second conductivity type opposite to the conductivity type of the substrate 210, for example, a p-type conductivity type, and is formed of a semiconductor different from the substrate 210, for example, amorphous It is made of amorphous silicon which is a semiconductor. Accordingly, the plurality of emitter portions 220 form a hetero junction as well as a p-n junction with the substrate 210. [

At this time, the width of the third rear front layer 270c and the width of the emitter section 220 may be the same or different from each other.

If the width of the third rear front layer 270c and the width of the emitter section 220 are different, the width of the third rear front layer 270c to increase the rear field effect due to the third rear front layer 270c May be formed larger than the width of the emitter portion 220.

However, the width of the emitter layer 220 may be larger than the width of the third rear front layer 270c in order to increase the pn junction region and improve the collection of holes having a lower mobility than the former. .

A plurality of first auxiliary electrodes 251 disposed on the plurality of third rear front layers 270c and a plurality of second auxiliary electrodes 241 disposed on the plurality of emitter portions 220 are electrically connected to the third rear front layer 270c, And extend along the emitter section 121, respectively.

At this time, each of the plurality of first auxiliary electrodes 251 is made of the same material and has the same structure, and each of the plurality of second auxiliary electrodes 241 is made of the same material and has the same structure.

The first auxiliary electrode 251 and the second auxiliary electrode 241 are formed of a transparent conductive oxide film such as a transparent conductive oxide (TCO) and a transparent conductive film doped with a conductive material such as aluminum (Al) .

For example, the first auxiliary electrode 251 and the second auxiliary electrode 241 may be formed of Al-doped ZnO.

The plurality of first auxiliary electrodes 251 are electrically connected to the plurality of third rear front layers 270c and the plurality of second auxiliary electrodes 241 are electrically connected to the plurality of emitter portions 220, .

The plurality of first main electrodes 252 located on the plurality of first auxiliary electrodes 251 are elongated along the plurality of first auxiliary electrodes 251 and are electrically and electrically connected to the plurality of first auxiliary electrodes 251. [ It is physically connected.

A plurality of second main electrodes 242 located on the plurality of second auxiliary electrodes 241 are elongated along the plurality of second auxiliary electrodes 241 and electrically connected to the plurality of second auxiliary electrodes 241 electrically And physically connected.

The first main electrode 252 may have the same planar shape as the first auxiliary electrode 251 located below the first main electrode 252, but may have another planar shape.

Similarly, the second main electrode 242 may have the same planar shape as the second auxiliary electrode 241 located at the lower portion thereof, but may have another planar shape.

The first main electrode 252 moves toward the third rear front layer 270c and collects an electric charge, for example, electrons, transmitted through the first auxiliary electrode 251.

The second main electrode 242 moves toward the emitter unit 220 and collects charges, for example, holes, which are transferred through the second auxiliary electrode 241.

The plurality of first main electrodes 252 and the plurality of second main electrodes 242 may be formed of silver (Ag) or a silver-aluminum alloy (Al-Ag).

10, the intrinsic amorphous silicon layer 270a and the intrinsic amorphous silicon carbide layer 270b of the rear electric field portion 270 are formed on the entire rear surface of the substrate and the n-type amorphous silicon carbide layer 270c is formed on the inter- It is also possible that the intrinsic amorphous silicon layer 270a, the intrinsic amorphous silicon carbide layer 270b and the n-type amorphous silicon carbide layer 270c are both located in the space between the emitter layers 220 .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Claims (15)

A semiconductor substrate containing an impurity of a first conductivity type;
A back electrometer located on a back surface of the substrate and containing an impurity of a first conductivity type; And
A first electrode connected to the rear electric field portion,
/ RTI >
Wherein the rear surface electric field portion includes an intrinsic first rear front layer contacting the rear surface of the semiconductor substrate and containing no impurities, a second rear front surface layer contacting the rear surface of the first rear front layer, And a third backside front layer of a first conductivity type in contact with the backside of the second backside front layer and containing impurities of the first conductivity type at a higher concentration than the semiconductor substrate,
Wherein the first rear whole layer is formed of amorphous silicon and the second rear front layer and the third rear front layer are each formed of amorphous silicon carbide. The method of claim 1,
Wherein the second rear whole layer and the third rear whole layer have an energy band gap higher than that of the first rear whole layer. 3. The method of claim 2,
Wherein the first back front layer has an energy band gap of 1.70 to 1.85 and the second back front layer and the third back front layer have an energy band gap of 1.85 to 2.08. The method of claim 1,
Wherein the entire front surface of the first electrode is in direct contact with the third rear front layer. The method of claim 1,
Wherein the first rear whole layer is formed to a thickness of 3 nm or less. The method of claim 1,
And the second rear whole layer is formed to a thickness of 6 nm to 15 nm. The method of claim 1,
And the third rear whole layer is formed to a thickness of 3 nm to 10 nm. 8. The method according to any one of claims 1 to 7,
Further comprising an emitter section containing an impurity of a second conductivity type opposite to the first conductivity type and a second electrode connected to the emitter section. 9. The method of claim 8,
Wherein the emitter portion is located on a front surface of the substrate, and the second electrode is located on a front surface of the emitter portion. The method of claim 9,
Wherein the second electrode includes a plurality of first finger electrodes extending in a first direction. 11. The method of claim 10,
Wherein the first electrode further comprises a plurality of first bus bar electrodes extending in a second direction orthogonal to the first direction and wherein the first bus bar electrode is physically connected to the first finger electrode. The method of claim 9,
Wherein a dielectric layer is disposed on a front surface of the emitter portion. The method of claim 9,
And the rear surface electric field portion is located on the entire rear surface of the semiconductor substrate. 8. The method according to any one of claims 1 to 7,
Wherein the emitter portion and the second electrode are located on a rear surface of the substrate. The method of claim 14,
Wherein a dielectric layer is disposed on a front surface of the semiconductor substrate.

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