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KR20140086615A - Duty cycle correction circuit and operation method thereof - Google Patents

Duty cycle correction circuit and operation method thereof Download PDF

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Publication number
KR20140086615A
KR20140086615A KR1020120157319A KR20120157319A KR20140086615A KR 20140086615 A KR20140086615 A KR 20140086615A KR 1020120157319 A KR1020120157319 A KR 1020120157319A KR 20120157319 A KR20120157319 A KR 20120157319A KR 20140086615 A KR20140086615 A KR 20140086615A
Authority
KR
South Korea
Prior art keywords
duty
control signal
clock signal
operation type
duty ratio
Prior art date
Application number
KR1020120157319A
Other languages
Korean (ko)
Inventor
장재민
김용주
최해랑
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020120157319A priority Critical patent/KR20140086615A/en
Priority to US13/844,928 priority patent/US9018994B2/en
Publication of KR20140086615A publication Critical patent/KR20140086615A/en
Priority to US14/668,488 priority patent/US9225316B2/en
Priority to US14/668,542 priority patent/US9257968B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The present invention relates to a duty cycle correction circuit correcting a duty rate of a clock signal. Provided is an operating method of a duty cycle correction circuit including a first locking operation step of changing the duty rate of the clock signal into a first target duty rate according to a duty control signal generated through a first operation type and a second locking operation step of changing the duty rate of the clock signal into a second target duty rate according to a duty control signal generated through a second operation type, after the first locking operation step.

Description

[0001] DUTY CYCLE CORRECTION CIRCUIT AND OPERATION METHOD THEREOF [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor design technique, and more particularly, to a duty cycle correction circuit capable of correcting a duty ratio of a clock signal.

In general, a semiconductor device including a DDR SDRAM (Double Data Rate Synchronous DRAM) receives various signals from an external controller such as a central processing unit, for example, and performs a desired operation of the controller. Such a semiconductor device is developed in a direction for high-speed operation according to a demand of a user, and a clock signal of a high frequency is supplied from the outside for this purpose. The external clock signal becomes the source of the internal clock signal used internally, and the frequency of the external clock signal and the internal clock signal becomes the operating frequency of the semiconductor device. Therefore, it is possible to increase the operating speed of the semiconductor device by increasing the frequency of the clock signal. However, there are limitations in raising the frequency of the clock signal, and various methods have been proposed to overcome it. One of them increases the utilization of the clock signal, which is called DDR method.

If the SDR (Single Data Rate) method used in the past is a method of outputting data in response to a rising edge of a clock signal, for example, the DDR method may be applied to both the rising edge and the falling edge of the clock signal And outputs the data in response. That is, two data are output in one period of the clock signal. Therefore, even if the semiconductor device using the DDR method and the semiconductor device using the SDR method are provided with the clock signal of the same frequency, the DDR method can process twice or more times the same time compared to the SDR method. This means that the circuit operation of the semiconductor device is two times faster.

On the other hand, in order to process two data in one period of a clock signal like the DDR method, it is most important to maintain the duty ratio of the clock signal at 50:50. That is, the logic high period and the logic low period of the clock signal must be the same. If the duty ratio of the clock signal deviates much from 50:50 due to the jitter component and other reasons, the reliability of the data output in response to the clock signal can not be guaranteed.

On the other hand, as described above, the operation speed of the semiconductor device is getting faster according to the demand of the user. A faster operating speed means that the frequency of the clock signal is increasingly higher, which means that it becomes increasingly difficult to control the duty ratio of the clock signal. Accordingly, a method for quickly and precisely controlling the duty ratio of the clock signal having such a high frequency to 50:50 must be studied.

A duty cycle correction circuit capable of correcting a duty ratio of a clock signal by using a duty control signal generated by varying an operation type of generating a duty control signal according to a duty ratio of a clock signal is provided.

An operation method of a duty cycle correction circuit capable of reflecting a different operation type in a plurality of bits in generating a duty control signal composed of a plurality of bits is provided.

Also, an operation method of a duty cycle correction circuit capable of generating duty control signals generated in an initial locking operation and a subsequent locking operation in different operation types is provided.

A duty cycle correction circuit according to an embodiment of the present invention includes a control signal generation unit for generating a duty control signal for controlling a duty ratio of a clock signal by reflecting a first or second operation type; An operation type setting unit for setting the first or second operation type in response to an operation type selection signal corresponding to a duty ratio of the clock signal; And a clock correction unit for correcting the clock signal in response to the duty control signal.

Advantageously, the first operation type includes a successive approximation register (SAR) operation type, and the second operation type includes a linear operation type.

According to another aspect of the present invention, there is provided a method of operating a duty cycle correction circuit, the method comprising: generating a duty control signal for correcting a duty ratio of a clock signal with a plurality of bits; Setting a bit in which the first and second operation types of the plurality of bits are reflected according to a duty ratio of the clock signal; Generating a corresponding bit of the plurality of bits as a first operation type; Generating a corresponding bit of the plurality of bits as a second operation type; And correcting a duty ratio of the clock signal in response to a duty control signal generated in the generating of the first and second operation types.

Advantageously, some of the plurality of bits reflect the first operation type and the remaining bits of the plurality of bits reflect the second operation type.

According to another aspect of the present invention, there is provided a method of operating a duty cycle correction circuit, including: a first locking operation step of correcting a duty ratio of a clock signal to a first target duty ratio in accordance with a duty control signal generated through a first operation type; And a second locking operation step of correcting the duty ratio of the clock signal to a second target duty ratio in accordance with the duty control signal generated through the second operation type after the first locking operation step.

Preferably, the first locking operation step and the second locking operation step have different unit operation periods.

The duty cycle correcting circuit according to the embodiment of the present invention corrects the duty ratio of the clock signal by using the duty control signal generated in such a manner that the duty type of the duty control signal is different according to the duty ratio of the clock signal, It is possible to generate the clock signal having the ratio more precisely and quickly.

In addition, it is possible to generate an optimum duty control signal according to the environment by reflecting the first operation type to some bits of the duty control signal and reflecting the second operation type to some remaining bits to generate the duty control signal.

In addition, it is possible to generate an optimum duty control signal in accordance with the environment by generating the duty control signal in different operation types in the initial locking operation and the subsequent locking operation.

A clock signal having a desired target duty ratio can be generated more quickly, and the semiconductor device can be provided with an environment capable of using the clock signal more quickly.

1 is a block diagram illustrating a duty cycle correction circuit according to an embodiment of the present invention.
2 is a block diagram illustrating the control signal generator 120 of FIG.
3 is a block diagram for explaining another embodiment of the control signal generator 120 of FIG.
4 and 5 are flowcharts for explaining an operation method of a duty cycle correction circuit according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

1 is a block diagram illustrating a duty cycle correction circuit according to an embodiment of the present invention.

Referring to FIG. 1, the duty cycle correction circuit includes a clock correction unit 110, a control signal generation unit 120, and an operation type setting unit 130.

The clock correction unit 110 generates the output clock signal CLK_CRR by correcting the duty ratio of the input clock signal CLK_IN in response to the duty control signal CTR_DT. Here, the input clock signal CLK_IN means a pre-correction clock signal, and the output clock signal CLK_CRR means a post-correction clock signal. A predetermined time is required for the output clock signal CLK_CRR to have a desired duty ratio (hereinafter referred to as a target duty ratio). When the control by the duty control signal CTR_DT is not reflected, the output clock signal CLK_CRR Can be said to be substantially equal to the duty ratio of the input clock signal CLK_IN which is the pre-correction clock signal.

The control signal generation unit 120 generates the duty control signal CTR_DT by reflecting the operation type corresponding to the type selection signal SEL_TY. Here, the operation type reflected in generating the duty control signal CTR_DT may include a successive approximation register (SAR) operation type and a linear operation type. The finally generated duty control signal CTR_DT may be a digital signal or an analog signal.

The operation type setting unit 130 is for generating an operation type selection signal SEL_TY corresponding to the duty ratio of the output clock signal CLK_CRR and the control signal generation unit 120 generates the operation type selection signal SEL_TY Generates a duty control signal CTR_DT in response to the SAR operation type or generates a duty control signal CTR_DT in a linear operation type.

The duty cycle correction circuit according to the embodiment of the present invention can generate the duty control signal CTR_DT in the SAR operation type or the linear operation type according to the duty ratio of the output clock signal CLK_CRR. Although the duty control signal CTR_DT is generated using the SAR operation type and the linear operation type according to the duty ratio of the clock signal in the embodiment of the present invention, the present invention generates the duty control signal CTR_DT And includes cases in which various operation types are used.

2 is a block diagram illustrating the control signal generator 120 of FIG.

2, the control signal generator 120 includes a duty ratio detector 210, a first control signal generator 220, a second control signal generator 230, and a selection output unit 240, Respectively.

The duty ratio detector 210 detects the duty ratio of the output clock signal CLK_CRR and provides the corresponding detection information INF_DET to the first and second control signal generators 220 and 230. [ The detection information INF_DET may be duty ratio information, locking information, or the like, and the locking information is information indicating that the output clock signal CLK_CRR has been corrected to a predetermined target duty ratio. The first control signal generation unit 220 generates the first duty control signal CTR1 by reflecting the SAR operation type according to the detection information INF_DET and the second control signal generation unit 230 generates the detection information INF INF_DET) to generate the second duty control signal CTR2. The selection output unit 240 selectively outputs the first duty control signal CTR1 and the second duty control signal CTR2 in response to the operation type selection signal SEL_TY. As will be described later, the second control signal generator 230 may generate the second duty control signal CTR2 using the information INF_CTR of the first duty control signal CTR1 as a default value. Accordingly, in this case, the first control signal generator 220 provides the information (INF_CTR) of the first duty control signal CTR1 to the second control signal generator 230.

A brief circuit operation of the duty cycle correction circuit according to the embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.

First, the clock correction unit 110 receives the input clock signal CLK_IN and generates an output clock signal CLK_CRR. At this time, the output clock signal CLK_CRR is controlled by the duty control signal CTR_DT. In the beginning, since the duty control signal CTR_DT does not reflect the information for correcting the clock signal, the input clock signal CLK_IN remains unchanged And becomes the output clock signal CLK_CRR.

Meanwhile, the type setting unit 130 generates an operation type selection signal SEL_TY corresponding to the duty ratio of the output clock signal CLK_CRR. For example, when the duty ratio of the output clock signal CLK_CRR is relatively large or when the duty ratio changes abnormally, the type setting unit 130 sets the operation type of the control signal generation unit 120 using the operation type selection signal SEL_TY Can be controlled.

The control signal generator 120 generates the first duty control signal CTR1 or the second control signal generator 230 generated in the first control signal generator 220 in response to the operation type selection signal SEL_TY, And outputs the second duty control signal CTR2 generated by the duty control signal CTR_DT. That is, the first duty control signal CTR1 reflecting the SAR operation type is outputted as the duty control signal CTR_DT or the second duty control signal CTR2 reflecting the linear operation type is outputted as the duty control signal CTR_DT . The clock correction unit 110 generates the output clock signal CLK_CRR by correcting the duty ratio of the input clock signal CLK_IN in response to the duty control signal CTR_DT thus outputted.

The duty cycle correction circuit according to the embodiment of the present invention generates the duty control signal CTR_DT reflecting the SAR operation type or the linear operation type according to the duty ratio of the output clock signal CLK_CRR and outputs the duty control signal CTR_DT, It is possible to correct the duty ratio of the input clock signal CLK_IN to control the duty ratio of the output clock signal CLK_CRR to be the target duty ratio.

3 is a block diagram for explaining another embodiment of the control signal generator 120 of FIG.

Referring to FIG. 3, the control signal generator 120 includes a duty ratio detector 310 and first and second control signal generators 320 and 530.

3, the selection output unit 240 of FIG. 2 is removed, and the operation type selection signal SEL_TY that controls the selection output unit 240 is used to perform the first and second control operations And controls the activation of the signal generators 320 and 330. More specifically, the first and second control signal generators 320 and 330 are activated in response to the operation type selection signal SEL_TY. In particular, the first and second control signal generators 320 and 330 are activated in response to the operation type selection signal SEL_TY, (330) are controlled independently of each other. In other words, the second control signal generator 330 is deactivated during the period in which the first control signal generator 320 is activated, and in the period during which the second control signal generator 330 is activated, (320) is deactivated.

For reference, the respective configurations according to the embodiment of FIG. 3 and the corresponding configurations according to the embodiment of FIG. 2 perform the same operation, and the duty control signal CTR_DT finally generated is also the same. However, in the embodiment of FIG. 3, since the first and second control signal generators 320 and 330 perform operations only in a necessary portion, it is possible to reduce unnecessary power consumption.

The duty cycle correction circuit according to the embodiment of the present invention controls the operation period of the first control signal generator 320 operating as a SAR operation type and the second control signal generator 330 operating as a linear operation type, It is possible to minimize the power consumed in the correction operation.

FIG. 4 is a flowchart for explaining an operation method of the duty cycle correcting circuit according to an embodiment of the present invention, and focuses on the relationship between the duty control signal CTR_DT and the first and second operation types. For convenience of explanation, the case where the duty control signal CTR_DT is composed of a plurality of bits is an example.

FIG. 4 is a flowchart illustrating a method of controlling a duty ratio of a clock signal according to an exemplary embodiment of the present invention. Referring to FIG. 4, a duty ratio of a clock signal is detected (S410) A step S440 of determining whether the first operation type is reflected in all the set bits, a step S450 of generating the duty control signal of the second operation type and correcting the duty ratio S450, And determining whether the second operation type is reflected (S460).

Referring to FIGS. 1 and 4, the duty ratio of the output clock signal CTR_CRR is detected in step S410, and the duty ratio of the output clock signal CTR_CRR is detected in step S410. And sets the bit in which the first and second operation types of the plurality of bits of the duty control signal CTR_DT are reflected in accordance with the result of the duty control signal CTR_DT. For example, when the duty control signal CTR_DT is composed of five bits, the SAR operation type, which is the first operation type, is reflected to the two bits according to the result of step S410, and the second operation Type linear operation type is reflected.

In step S430, a first operation type, that is, a SAR operation type is reflected on the bits set in step S420. In step S440, it is determined whether the SAR operation type is reflected in all the bits set. If the SAR operation type is not reflected in the bit (NO), the step 'S430' is performed again, and if the SAR operation type is reflected in all the set bits (YES), the step 'S450' is performed.

In step S450, a second operation type, that is, a linear operation type is reflected on the bit set in step S420. In step S450, it is determined whether the linear operation type is reflected in all bits set. If the linear operation type is not reflected in the bit (No), the step 'S450' is performed again, and if the linear operation type is reflected in all the set bits (Yes), 'S460' is performed.

The duty cycle correction circuit according to the embodiment of the present invention generates the duty control signal CTR_DT through the above method to reflect the SAR operation type in some bits of the duty control signal CTR_DT composed of a plurality of bits, It is possible to reflect the linear motion type. Also, the duty control signal CTR_DT generated in this way can respond more sensitively to a small change in the clock signal, which means that the duty ratio correction operation of the clock signal can be performed more quickly and precisely.

5 is a flowchart for explaining an operation method of the duty cycle correcting circuit according to the embodiment of the present invention, and focuses on the relationship between the duty control signal CTR_DT and the first and second locking operations. Here, the locking operation refers to an operation in which the clock signal is corrected to a predetermined duty ratio.

FIG. 5 is a flowchart illustrating a method for controlling a locking operation according to an exemplary embodiment of the present invention. Referring to FIG. 5, a first locking operation is performed in operation S510, a duty control signal is generated in operation S520, a first locking operation is performed in operation S530, A step S540 of generating a duty control signal with respect to the duty control signal, and a step S550 of performing a second locking operation.

Referring to FIGS. 1 and 5, a first locking operation in step S530 and a second locking operation in step S550 will be described later in step S510. In the first locking operation, Step S520 is performed, and if it is not the initial locking operation (No), step S550 is performed.

In step S520, a duty control signal CTR_DT is generated as a first operation type as a first operation type in step S520, and a duty control signal CTR_DT is generated in a step S530 as a duty control signal The duty ratio of the output clock signal CTR_CRR is corrected according to the duty ratio CTR_DT to perform the first locking operation. Here, the first locking operation means an operation for correcting the duty ratio of the output clock signal CTR_CRR to a predetermined target duty ratio (hereinafter, referred to as 'first target duty ratio'). Accordingly, in step 'S530', the output clock signal CTR_CRR is corrected to the first target duty ratio.

On the other hand, the duty ratio of the output clock signal CTR_CRR after the first locking operation, which is the initial locking operation, can be turned back by the external environment. That is, it is necessary to perform the duty ratio correcting operation again after the first locking operation, and the operation performed at this time is referred to as a 'second locking operation' in the embodiment of the present invention. Here, the first locking operation and the second locking operation have different operation intervals, and in the case of the second locking operation, the duty ratio of the clock signal may be slightly different from the first locking operation.

The duty control signal CTR_DT is generated as a linear operation type which is the second operation type in the step S540, and the duty control signal CTR_DT is generated as the duty control signal CTR_DT in the step S550, The duty ratio of the output clock signal CTR_CRR is corrected according to the second clock signal CTR_DT to perform the second locking operation. Here, the second locking operation means an operation for correcting the duty ratio of the output clock signal CTR_CRR to a predetermined target duty ratio (hereinafter, referred to as a second target duty ratio). Accordingly, in step 'S540', the output clock signal CTR_CRR is corrected to the second target duty ratio.

The duty cycle correction circuit according to the embodiment of the present invention operates by dividing into a first locking operation period for correcting the clock signal to the first target duty ratio and a second locking operation period for correcting the clock signal to the second target duty ratio. In other words, the first locking operation period, which is the initial locking operation, performs the duty correction operation using the duty control signal CTR_DT reflecting the SAR operation type, and then the second locking operation period, which is the locking operation, It is possible to perform the duty correction operation using the duty control signal CTR_DT. Here, the first and second target duty ratios may be set differently or the same depending on the situation. As a result, the duty control signal CTR_DT reflects different operation types according to the locking operation period. Also, the duty control signal CTR_DT generated in this way can respond more sensitively to a small change in the clock signal, which means that the duty ratio correction operation of the clock signal can be performed more quickly and precisely.

As described above, the duty cycle correction circuit according to the embodiment of the present invention can generate the duty control signal CTR_DT by changing the operation type according to the duty ratio of the clock signal. It is possible to perform the duty ratio correcting operation of the clock signal more quickly and precisely by using the duty control signal CTR_DT.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

S510: Step of judging whether or not the initial locking operation is performed
S520: generating a duty control signal with the first operation type
S530: Performing the first locking operation
S540: generating a duty control signal with a second operation type
S550: Performing the second locking operation

Claims (5)

A first locking operation step of correcting the duty ratio of the clock signal to a first target duty ratio in accordance with the duty control signal generated through the first operation type; And
A second locking operation step of correcting the duty ratio of the clock signal to a second target duty ratio in accordance with the duty control signal generated through the second operation type after the first locking operation step
The duty cycle correction circuit comprising:
The method according to claim 1,
Wherein the first locking operation step and the second locking operation step have different unit operation periods.
The method according to claim 1,
Further comprising the step of determining whether the first locking operation step is completed and selecting the first locking operation step or the second locking operation step.
The method according to claim 1,
Wherein the first and second target duty ratios include duty ratios that are equal to each other.
The method according to claim 1,
Wherein the first operation type includes a SAR (Successive Approximation Register) operation type, and the second operation type includes a linear operation type.
KR1020120157319A 2012-12-28 2012-12-28 Duty cycle correction circuit and operation method thereof KR20140086615A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020120157319A KR20140086615A (en) 2012-12-28 2012-12-28 Duty cycle correction circuit and operation method thereof
US13/844,928 US9018994B2 (en) 2012-12-28 2013-03-16 Duty cycle correction circuit and operation method thereof
US14/668,488 US9225316B2 (en) 2012-12-28 2015-03-25 Duty cycle correction circuit and operation method thereof
US14/668,542 US9257968B2 (en) 2012-12-28 2015-03-25 Duty cycle correction circuit and operation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120157319A KR20140086615A (en) 2012-12-28 2012-12-28 Duty cycle correction circuit and operation method thereof

Publications (1)

Publication Number Publication Date
KR20140086615A true KR20140086615A (en) 2014-07-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120157319A KR20140086615A (en) 2012-12-28 2012-12-28 Duty cycle correction circuit and operation method thereof

Country Status (1)

Country Link
KR (1) KR20140086615A (en)

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