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KR20140083592A - Word Line Control Circuit of Semiconductor Memory Device - Google Patents

Word Line Control Circuit of Semiconductor Memory Device Download PDF

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Publication number
KR20140083592A
KR20140083592A KR1020120153523A KR20120153523A KR20140083592A KR 20140083592 A KR20140083592 A KR 20140083592A KR 1020120153523 A KR1020120153523 A KR 1020120153523A KR 20120153523 A KR20120153523 A KR 20120153523A KR 20140083592 A KR20140083592 A KR 20140083592A
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KR
South Korea
Prior art keywords
test mode
signals
word line
control signal
word lines
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KR1020120153523A
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Korean (ko)
Inventor
강경필
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020120153523A priority Critical patent/KR20140083592A/en
Publication of KR20140083592A publication Critical patent/KR20140083592A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/06—Acceleration testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

According to an embodiment of the present invention, a word line control circuit of a semiconductor control circuit includes a test mode decoding block generating first to third test mode signals in response to first and second test mode control signals; an address decoding block generating multiple enable signals to control a dummy word line and all word lines in response to multiple address signals generated from the outside and the first, second, and third test mode signals; and a word line operating signal generating block providing multiple word line operating signals and dummy word line operating signals in response to the enable signals.

Description

[0001] The present invention relates to a word line control circuit for a semiconductor memory device,

The present invention relates to a semiconductor memory device, and more particularly to a word line control circuit of a semiconductor memory device.

In general, when a semiconductor memory device is manufactured, many defects may occur on the wafer due to various causes after the wafer fabrication process. That is, a phenomenon such as a bridge phenomenon in which a pattern formed on a wafer and a pattern are connected to each other, an etching failure of a film formed on the wafer, a defect in an opening of a contact hole connecting the element and the element, This is an example.

Since the semiconductor device in which the above-described problems are generated can be manufactured in a semiconductor memory device and cause a malfunction, the analysis process is performed on the wafers subjected to the wafer fabrication process so that each chip, Of the defects. In particular, a burn-in mode test may be performed to screen initial failures in the wafer state. The burn-in mode test intensively applies high-temperature and high-voltage stress to the inside of the chip to screen for defects that may occur early.

On the other hand, as the technology of the DRAM becomes finer, the pitch and line width of the line may be narrowed. For example, if the pitch interval between the word lines is reduced, A micro-bridge (μ-bridge) may occur. At this time, if the adjacent wordline human microbridge is a normal word in the mat, a screen is possible.

However, when testing without activating the dummy word line, such as the burn-in mode test described above, it is very difficult to screen the micro-bridge defects between the word line located at the edge of the mat and the dummy word line located at the area outside the mat .

An embodiment of the present invention provides a word line control circuit of a semiconductor memory device capable of screening for microbridge failures between a dummy word line and a normal word line in a wafer bunnning mode.

The word line control circuit of the semiconductor memory device according to an embodiment of the present invention includes a test mode for generating first to third test mode signals in response to first and second test mode control signals when the wafer burn- A plurality of address signals generating externally generated address signals, a plurality of enable signals capable of controlling all word lines and dummy word lines in response to the first, second and third test mode signals, And a word line drive signal generating block for providing a plurality of word line drive signals and a dummy word line drive signal in response to the plurality of enable signals.

The word line control circuit of the semiconductor memory device according to another embodiment of the present invention includes a test mode control signal generation block for decoding the burn-in address to generate the first and second test mode control signals when the wafer burn- Generating a plurality of word line driving signals and a dummy word line driving signal in response to a plurality of externally generated address signals and the first and second test mode control signals, thereby activating a plurality of normal word lines and dummy word lines And a mat control block that can control whether or not it is possible.

According to one embodiment of the present invention, by allowing various test modes to be entered, it is possible to activate all word lines, activate all dummy word lines, or control all word lines and all dummy word lines simultaneously . Accordingly, the semiconductor memory device according to an embodiment of the present invention can perform a micro bridge-related test while simultaneously activating a word line and a dummy word line adjacent to the word line, thereby screening a microbridge phenomenon between a word line and an adjacent dummy word line The reliability of the product can be increased.

1 is a block diagram of a word line control circuit of a semiconductor memory device according to an embodiment of the present invention;
Figure 2 is a block diagram of the mat control block according to Figure 1;
Figure 3 is a circuit diagram of a test mode decoding block according to Figure 2, and
4 is a circuit diagram of an address decoding block according to FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, embodiments of the present invention will be described more specifically with reference to the accompanying drawings.

1 is a configuration diagram of a word line control circuit 10 of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a word line control circuit 10 of a semiconductor memory device includes a test mode control signal generation block 100, a mat control block 200, and a core area 300.

In one embodiment of the present invention, a word line control circuit 10 that can be applied in wafer burn-in mode will be described.

As is well known to those skilled in the art, the wafer burn-in mode seeks to increase production yield by screening initial failures that may occur in the wafer state, as well as ensuring a reliable product based on the package state. The wafer burn-in test can realize various purposes by realizing various test circuits inside the chip, and applying the stresses of high temperature and high voltage intensively to the weak parts, thereby effectively screening defects.

The test mode control signal generation block 100 receives the burn-in address (BI-ADD) and outputs the first test mode control signal TALLWD and the second test mode control signal TALLWD to the word line control circuit 10 of the semiconductor memory device. And generates a second test mode control signal (TDUMMY). Here, it is possible that the test mode control signal generation block 100 generates the first test mode control signal TALLWD and the second test mode control signal TDUMMY by decoding the burn-in address BI-ADD. That is, it is possible to decode an address necessary for burn-in and generate a necessary test mode control signal. At this time, the number of the test mode control signals to be generated can be increased or decreased according to the semiconductor memory device. Thus, conventionally, if one test mode control signal is generated by integrally controlling all the normal word lines (activating all or inactivating all) using the burn-in address (BI-ADD) Another test mode control signal is additionally generated so as to control not only the normal word line but also the dummy word line. (Hereinafter, a word line is referred to as a 'normal word line' or a 'main word line'.)

The mat control block 200 generates a plurality of main word line driving signals MWLB <0: M> in response to an address ADD signal, a first test mode control signal TALLWD and a second test mode control signal TDUMMY, ), A plurality of sub word line driver driving signals FXB < 0: N >, and a dummy word line driving signal DWLB. That is, the mat control block 200 is configured to control not only the normal word line but also the activation of the dummy word line unlike the prior art, so that the micro bridge phenomenon between the adjacent normal word line and the dummy word line can also be screened. The mat control block 200 will be described in more detail below.

The core region 300 receives a plurality of main word line driving signals MWLB <0: M>, a plurality of sub word line driver driving signals FXB <0: N> and a dummy word line driving signal DWLB It is possible to control whether or not the main word line (not shown) and the dummy word line (not shown) are activated through the selected sub word line driver. The core region 300 is well known to those skilled in the art and will not be described. That is, the core region 300 is a mat which is controlled by a plurality of main word line driving signals MWLB <0: M> and a plurality of sub word line driver driving signals FXB <0: N> It will be understandable. However, in an embodiment of the present invention, the activation of the dummy word line (not shown) can also be controlled, which is different from the prior art.

2 is a detailed block diagram of the mat control block 200 according to FIG.

Referring to FIG. 2, the mat control block 200 will be described in detail.

The mat control block 200 according to an embodiment of the present invention includes a test mode decoding block 210, an address decoding block 230, and a word line driving signal generating block 250.

First, the test mode decoding block 210 generates the first to third test mode signals TALLWD-D, TDUMMY-D, and TALLWD-D3 by combining the first test mode control signal TALLWD and the second test mode control signal TDUMMY, TDUMALLWD-D).

That is, the test mode decoding block 210 generates a first test mode signal (hereinafter referred to as &quot; test mode signal &quot;) that controls activation of all the word lines in accordance with the combination of the first test mode control signal TALLWD and the second test mode control signal TDUMMY The second test mode signal TALLWD-D controls the activation of all the dummy word lines according to the combination of the first test mode control signal TALLWD and the second test mode control signal TDUMMY. (TDUMMY-D). In addition, the test mode decoding block 210 integrally controls all the word lines and all the dummy word lines according to the combination result of the first test mode control signal TALLWD and the second test mode control signal TDUMMY And provides a third test mode control signal TDUMALLWD-D. In other words, the test mode decoding block 210 may control the plurality of test mode controls (TALWD) and the test mode control signals (TALWD) so as to enter various test modes according to the combination of the first test mode control signal TALLWD and the second test mode control signal Signals TALLWD-D, TDUMMY-D, and TDUMALLWD-D.

On the other hand, the address decoding block 230 decodes the pre-decode word line control signal LAX_MWL-D in response to the plurality of address signals ADD and the first to third test mode signals TALLWD-D, TDUMMY-D, and TDUMALLWD- 0: A &gt;), predecoded subword line driver control signal (LAX_FX <0: B>) and predecoded dummy word line control signal (TDUMMY-DD). The address decoding block 230 may further include an input unit for inputting the first to third test mode signals TALLWD-D, TDUMMY-D, and TDUMALLWD-D to the normal pre-decoder. A detailed description thereof will be described with reference to the detailed circuit diagrams hereinafter.

The word line drive signal generation block 250 includes a predecode word line control signal LAX_MWL <0: A>, a predecoded subword line driver control signal LAX_FX <0: B> A plurality of main word line driving signals MWLB <0: M>, a plurality of sub word line driver driving signals FXB <0: N>, and a dummy word line driving signal DWLB in response to a plurality of sub word line driving signals TDUMMY- do. The word line drive signal generation block 250 can be understood as a normal word line driver. That is, as will be appreciated by those skilled in the art, a driver driven in response to a pre-decoded signal will not be described in detail in an embodiment of the present invention.

However, briefly, the word line driving signal generation block 250 activates a plurality of main word line driving signals MWLB < 0: M > in response to the predecoding word line control signals LAX_MWL <0: A> And activates a plurality of sub word line driver driving signals FXB < 0: N > in response to the predecoding sub word line driver control signals LAX_FX <0: B> -DD) to activate the dummy word line driving signal DWLB.

In other words, the word line drive signal generation block 250 drives the sub word line driver (not shown) to be activated in response to the predecoded sub word line driver control signal (LAX_FX < 0: B & The main word line driving signal MWLB <0: M> can be activated in response to the word line control signal LAX_MWL <0: A>. On the other hand, since one dummy word line (not shown) may be provided on the upper and lower sides of the mat, it is possible to directly control the dummy word line without using a separate dummy word line driver. Accordingly, the word line driving signal generation block 250 can activate the dummy word line driving signal DWLB in response to the activated pre-decoding dummy word line control signal (TDUMMY-DD).

FIG. 3 is a detailed circuit diagram of the test mode decoding block 210 according to FIG.

Referring to FIG. 3, the test mode decoding block 210 includes a first decoding unit 210a, a second decoding unit 210b, and a third decoding unit 210c.

The first decoder 210a combines the first test mode control signal TALLWD and the second test mode control signal TDUMMY to generate a first test mode signal TALLWD-D for controlling activation of all the word lines to provide.

The first decoding unit 210a includes a first inverter IV1, a first NAND gate ND1, and a second inverter IV2. Thus, the first NAND gate ND1 combines the first test mode control signal TALLWD and the inverted second test mode control signal TDUMMY, and inverts the NAND combination result by the second inverter IV2 And provides a first test mode signal TALLWD-D.

The second decoding unit 210b includes a second test mode signal TDUMMY-D for controlling activation of all dummy word lines by combining the first test mode control signal TALLWD and the second test mode control signal TDUMMY, Lt; / RTI &gt;

The second decoding unit 210b includes a third inverter IV1, a second NAND gate ND2, and a fourth inverter IV4. Thus, the NAND gate ND2 combines the inverted first test mode control signal TALLWD and the second test mode control signal TDUMMY, and inverts the NAND combination result by the fourth inverter IV4 And provides a second test mode signal (TDUMMY-D).

The third decoding unit 210c may generate a third test mode control signal (hereinafter, referred to as &quot; test mode control signal &quot;) that integrally controls all word lines and all dummy word lines by combining the first test mode control signal TALLWD and the second test mode control signal TDUMMY TDUMALLWD-D).

The third decoding unit 210c includes a third NAND gate ND3 and a fifth inverter IV5. Thus, the third NAND gate ND3 combines the first test mode control signal TALLWD and the second test mode control signal TDUMMY with NAND and inverts the NAND combination result by the fifth inverter IV5, And provides a test mode control signal TDUMALLWD-D.

The combination result of the test mode decoding block 210 according to an embodiment of the present invention is illustrated in the following Table 1. [

Test mode control signal Test mode signal TALLWD TDUMMY TALLWD-D TDUMMY-D TDUMALLWD-D L L L L L L H L H L H L H L L H H L L H

Referring to Table 1, it can be explained as follows.

When all of the first test mode control signal TALLWD and the second test mode control signal TDUMMY are activated, the third test mode control signal TDUMALLWD-D, which integrally controls all the word lines and all the dummy word lines, And the first test mode control signal TALLWD-D and the second test mode control signal TDUMMY-D are inactivated.

On the contrary, if the first test mode control signal TALLWD and the second test mode control signal TDUMMY are all deactivated, the first to third test mode signals TALLWD-D, TDUMMY-D, and TDUMALLWD-D are inactivated do.

On the other hand, when the first test mode control signal TALLWD is activated and the second test mode control signal TDUMMY is inactivated, only the first test mode signal TALLWD-D is activated and the second and third test mode signals TDUMMY -D, TDUMALLWD-D) are deactivated.

Finally, the first test mode control signal TALLWD is inactivated. When the second test mode control signal TDUMMY is activated, only the second test mode signal TDUMMY-D is activated and the first and second test mode signals TALLWD-D, TDUMALLWD-D) are inactivated.

In other words, depending on the combination of the first test mode control signal TALLWD and the second test mode control signal TDUMMY, all the word lines are activated, all the dummy word lines are activated, It is possible to control activation of all the dummy word lines at the same time. Therefore, according to the embodiment of the present invention, unlike in the conventional wafer burn-in mode, in which the dummy word line can not be controlled, the test mode control signal is added and decoded to control whether the dummy word line is selectively activated or not , It is possible to control whether or not the dummy word line is activated together with the word line. Furthermore, by simultaneously activating and testing the dummy word line adjacent to the word line, the micro bridge phenomenon between the word line and the adjacent dummy word line can be screened, thereby enhancing the reliability of the product.

There are various methods for testing the microbridge phenomenon between adjacent word lines. For example, after activating all of the word lines, a joule heat due to a high voltage between adjacent word lines (including a normal word line and a dummy word line) (Joule? Heat) is detected and the micro bridge can be detected. Or when the application levels are different from one another in the order of even and odd, an abnormal current path is formed and a leakage current is generated so that a micro bridge can be found. This does not exclude various examples of implementing a microbridge test for each semiconductor memory device. [0031] FIG. 4 is a detailed circuit diagram of the address decoding block 230 according to FIG.

Referring to FIG. 4, the address decoding block 230 will be described in detail.

For convenience of explanation, the address signals are not described as all address signals, but only the first and second address signals ADD <0> and ADD <1> will be described. However, it is of course not limited thereto.

Referring to FIG. 4, the address decoding block 230 includes a first test mode input unit 232, an address decoder 234, and a second test mode input unit 236.

The first test mode input unit 232 receives and combines the first through third test mode signals TALLWD-D, TDUMMY-D, and TDUMALLWD-D.

The first test mode input unit 232 includes a NOR gate NR, first and second inverters IIV1 and INV2, and a NAND gate ND1.

More specifically, the NOR gate NR and the second inverter INV2 of the first test mode input unit 232 output the first test mode signal TALLWD-D and the third test mode signal TDUMALLWD- And provides it to the NAND gate ND1. On the other hand, the node a is supplied with the inverted level of the second test mode signal (TDUMMY-D) to the address decoder 234. The NAND gate ND1 provides the node b with the signal of the node a, the first test mode signal TALLWD-D and the third test mode signal TDUMALLWD-D by NANDing the ORing result.

On the other hand, the second test mode input unit 236 receives the predecoded dummy word line control signal TDUMMY-DD in response to the second and third test mode signals TDUMMY-D and TDUMALLWD-D, which are dummy word line related test mode signals. ).

The second test mode input section 236 includes a NOR gate (NOR) and an inverter (I). Thus, even if only one of the second and third test mode signals TDUMMY-D and TDUMALLWD-D is activated by the NOR gate NOR and the inverter I, the second test mode input unit 236 is activated Decoded word line control signal (TDUMMY-DD).

The address decoder 234 includes first to fourth decoders 234a, 234b, 234c, and 234d.

Describing the first decoder 234a in more detail, the inverted first and second address signals ADD <0> and ADD <1> and the signal of the node a are combined and decoded.

The first decoder 234a includes a first NAND gate NAND1, a second NAND gate NAND2, a first inverter INV1, and a second inverter INV2.

The first NAND gate NAND1 combines the inverted first and second address signals / ADD <0> and / ADD <1> and the signal of the node a to provide a second NAND gate NAND2.

The second NAND gate NAND2 receives the output signal of the first NAND gate NAND1 and the signal of the node b and combines the NANDs with each other. The output result is transmitted to the first and second inverters INV1 and INV2 The pre-decode wordline control signal LAX_MWL <0> and the first pre-decoded sub-wordline driver control signal LAX_FB <0>.

The second decoder to the fourth decoders 234b to 234d are different from the received address signals only. The structure of the decoder is similar to that of the first decoder 234a, and the operation principle thereof is similar to that of the first decoder 234a.

The second decoder 234b combines the first inverted address signal / ADD <0> and the second address signal ADD <1> with the signal of the node a to generate a second pre-decode word line control signal LAX_MWL < &Gt;) and a second predecoding subword line driver control signal (LAX_FB < 1 >).

The third decoder 234c combines the first address signal ADD <0> and the second inverted address signal / ADD <1> and the signal of the node a to generate a third predecoder word line control signal LAX_MWL <2 >) And a third predecoding subword line driver control signal (LAX_FB <2>).

The fourth decoder 234b combines the first address signal ADD <0> and the second address signal ADD <1> with the signal of the node a to generate a fourth predecoder word line control signal LAX_MWL <3> And a fourth predecoding subword line driver control signal (LAX_FB <3>).

The pre-decoded word line control signal and the pre-decoded sub-word line driver control signal are, according to the combined address and the number of sub word line drivers configured in the circuit, as described above, Of course, it can be changed.

Referring to FIG. 4 again, the operation of the address decoding block 230 will be described in detail.

For example, it is assumed that only the third test mode signal TDUMALLWD-D is activated and the first and second test mode signals TALLWD-D and TDUMMY-D are inactivated.

At this time, since the node a will be at a high level, a high level is applied to all the decoders 234a to 234d and provided to each of the NAND gates NAND1, NAND3, NAND5 and NAND7. That is, the deactivated second test mode signal TDUMMY-D does not affect the first through fourth decoders 234a through 234d.

Then, in response to the activated third test mode signal TDUMALLWD-D and the deactivated first test mode signal TALLWD-D, the node b becomes low level. Similarly, the signal of the node b is provided to each of the NAND gates NAND2, NAND4, NAND6 and NAND8. Thus, all the pre-decoded word line control signals (LAX_MWL <0: 3>) and all pre-decoded sub-word line control signals (LAX_FX <0: 3>) by the third test mode signal (TDUMALLWD- 0: 3 &gt;) can be activated.

Meanwhile, the second test mode input unit 236 may provide the activated pre-decoding dummy word line control signal (TDUMMY-DD) in response to the activated third test mode signal (TDUMALLWD-D).

In other words, in response to the activated third test mode signal TDUMALLWD-D, all predecode wordline control signals LAX_MWL <0: 3> and all pre-decoded subword line control signals LAX_FX <0: 3> ) Is activated and the predecoded dummy word line control signal (TDUMMY-DD) is activated, so that all the word lines and all dummy word lines can be activated through the subsequent word line drive signal generation block (see 250 in FIG. 2) have. In other words, when any one of the first to third test mode signals TALLWD-D, TDUMMY-D, and TDUMALLWD-D is activated, the plurality of It becomes irrelevant to the address signal.

If the first to third test mode signals TALLWD-D, TDUMMY-D, and TDUMALLWD-D are inactivated, the node a is at a high level and the node b is at a high level to affect the decoding operation of the normal address Therefore, in this case, it operates in the normal mode instead of the test mode.

As described above, according to the embodiment of the present invention, the word line control circuit operates in the normal mode, and in particular, in the wafer burn-in mode, it is possible to control the activation of the dummy word line by entering various test modes. To this end, a test mode control signal is added using a burn-in address (see BI in FIG. 1) required in the burn-in mode, and these signals are combined to enter various test modes to activate all the word lines, Activating a line, or activating all word lines and all dummy word lines simultaneously. Therefore, according to an embodiment of the present invention, micro-bridging phenomenon between a word line and an adjoining dummy word line can be screened by simultaneously testing a word line and a dummy word line adjacent to the word line, Therefore, the reliability of the product can be increased.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: test mode control signal generation block
200: mat control block
300: core region
210: test mode decoding block
230: address decoding block
250: Word line drive signal generation block

Claims (10)

In a semiconductor memory device to which a wafer burn-in mode is applied,
A test mode decoding block for generating first, second and third test mode signals in response to the first and second test mode control signals;
An address decoding block for generating a plurality of externally generated address signals, a plurality of enable signals capable of controlling all word lines and all dummy word lines in response to the first to third test mode signals; And
And a word line drive signal generation block for providing a plurality of word line drive signals and a dummy word line drive signal in response to the plurality of enable signals. The method according to claim 1,
The test mode decoding block includes:
A first decoding unit for providing the first test mode signal for controlling whether all the word lines are activated by combining the first test mode control signal and the second test mode control signal;
A second decoder for providing the second test mode signal for controlling whether all the dummy word lines are activated by combining the first test mode control signal and the second test mode control signal; And
And a third decoding unit for providing the third test mode control signal for simultaneously controlling all the word lines and all dummy word lines by combining the first test mode control signal and the second test mode control signal, Line control circuit. The method according to claim 1,
Wherein the address decoding block comprises:
A first test mode input unit for receiving and combining the first to third test mode signals;
A second test mode input unit for providing a part of the plurality of enable signals in response to the second and third test mode signals which are the dummy word line related test mode signals; And
And an address decoder for decoding the output result of the first test mode input section and the plurality of addresses. The method of claim 3,
Wherein the address decoder comprises:
And a decoder in a normal mode for decoding the input plurality of addresses if the first to third test mode signals are deactivated,
And wherein when any one of the first to third test mode signals is activated, the address decoding operation is controlled as a test mode so that the address decoding operation is independent of the plurality of address signals. In a semiconductor memory device to which a wafer burn-in mode is applied,
A test mode control signal generation block for decoding the burn-in address to generate first and second test mode control signals; And
Generating a plurality of word line driving signals and a dummy word line driving signal in response to a plurality of externally generated address signals and the first and second test mode control signals, thereby activating a plurality of normal word lines and dummy word lines The word line control circuit of the semiconductor memory device including the mat control block. 6. The method of claim 5,
The mat control block may cause all of the normal word lines to be activated, all the dummy word lines to be activated, or all of the dummy word lines to be activated, in response to the first and second test mode control signals, The word line control circuit of the semiconductor memory device controlling to simultaneously activate the normal word line and all the dummy word lines. The method according to claim 6,
The mat control block includes:
A test mode decoding block for generating first to third test mode signals in response to the first and second test mode control signals;
An address decoding block for generating an enable signal capable of controlling all the normal word lines and the dummy word lines in response to the plurality of address signals and the first, second and third test mode signals; And
And a word line drive signal generation block for providing the plurality of word line drive signals and the dummy word line drive signal in response to the plurality of enable signals. 8. The method of claim 7,
The test mode decoding block includes:
A first decoding unit for providing the first test mode signal for controlling whether all the normal word lines are activated by combining the first test mode control signal and the second test mode control signal;
A second decoding unit for providing the second test mode signal for controlling activation of all the dummy word lines by combining the first test mode control signal and the second test mode control signal; And
And a third decoding unit for providing the third test mode control signal for simultaneously controlling all the normal word lines and all the dummy word lines by combining the first test mode control signal and the second test mode control signal, The word line control circuit of the device. 8. The method of claim 7,
Wherein the address decoding block comprises:
A first test mode input unit for receiving and combining the first to third test mode signals;
And a second test mode input unit for providing a portion of the plurality of enable signals capable of controlling all the word lines and dummy word lines in response to the second and third test mode signals which are the dummy word line related test mode signals. ; And
And an address decoder for decoding the output result of the first test mode input section and the plurality of addresses. 10. The method of claim 9,
Wherein the address decoder comprises:
And a decoder in a normal mode for decoding the input plurality of addresses if the first to third test mode signals are deactivated,
And wherein when any one of the first to third test mode signals is activated, the address decoding operation is controlled as a test mode so that the address decoding operation is independent of the plurality of address signals.
KR1020120153523A 2012-12-26 2012-12-26 Word Line Control Circuit of Semiconductor Memory Device KR20140083592A (en)

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KR20190062913A (en) * 2017-11-29 2019-06-07 에스케이하이닉스 주식회사 Semiconductor Memory Apparatus
KR20190107342A (en) * 2018-03-12 2019-09-20 에스케이하이닉스 주식회사 Semiconductor apparatus and test system including the same
US10510429B2 (en) 2017-10-27 2019-12-17 Samsung Electronics Co., Ltd. Memory device performing test on memory cell array and method of operating the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510429B2 (en) 2017-10-27 2019-12-17 Samsung Electronics Co., Ltd. Memory device performing test on memory cell array and method of operating the same
KR20190062913A (en) * 2017-11-29 2019-06-07 에스케이하이닉스 주식회사 Semiconductor Memory Apparatus
US10643731B2 (en) 2017-11-29 2020-05-05 SK Hynix Inc. Semiconductor memory apparatus
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