KR20140080653A

KR20140080653A - Liquid Crystal Display Device

Info

Publication number: KR20140080653A
Application number: KR1020120145143A
Authority: KR
Inventors: 심다혜; 조영직
Original assignee: 엘지디스플레이 주식회사
Priority date: 2012-12-13
Filing date: 2012-12-13
Publication date: 2014-07-01
Also published as: KR102024655B1

Abstract

The present invention relates to a liquid crystal display (LCD) including: a first substrate including an active area and a surrounding area; a gate wire arranged in a first direction in the active area; a data line and a first ground wire alternately arranged in a second direction different from the first direction in the active area; and a second ground wire formed in the surrounding area and connected with the first ground wire. According to the present invention, since the first ground wire is formed in the active area, the area of the second ground wire formed in the surrounding area can be reduced, so that the width of a bezel of the LCD can be reduced.

Description

[0001] The present invention relates to a liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a ground line formed on a lower substrate of a liquid crystal display device.

Liquid crystal display devices have a wide variety of applications ranging from notebook computers, monitors, spacecrafts and aircraft to the advantages of low power consumption and low power consumption and being portable.

The liquid crystal display device includes a lower substrate, an upper substrate, and a liquid crystal layer formed between the two substrates. The arrangement of the liquid crystal layers is adjusted according to whether an electric field is applied or not, .

Hereinafter, a conventional liquid crystal display device will be described with reference to the drawings.

FIG. 1A is a schematic cross-sectional view of a conventional liquid crystal display device, and FIG. 1B is a schematic plan view of a lower substrate constituting a conventional liquid crystal display device.

1A, a conventional liquid crystal display device includes a lower substrate 1, an upper substrate 2, a sealant 3, and a liquid crystal layer 4.

A thin film transistor is formed on the lower substrate 1, and a color filter is formed on the upper substrate 2. The sealant 3 is formed at the edges of the lower substrate 1 and the upper substrate 2 to bond the lower substrate 1 and the upper substrate 2 together. The liquid crystal layer 4 is formed between the lower substrate 1 and the upper substrate 2.

1B, the lower substrate 1 constituting the conventional liquid crystal display device includes an active region and a peripheral region.

The active region means an area for displaying an image. The gate line 10, the data line 20, and the thin film transistor T are formed in the active region.

The gate wirings 10 are arranged in the horizontal direction, and the data wirings 20 are arranged in the vertical direction. In this manner, the gate wiring 10 and the data wiring 20 are arranged in an intersecting manner to define a plurality of pixels. In each of the plurality of pixels, a thin film transistor T is formed as a switching element. Although not shown, pixel electrodes and common electrodes are formed in each of the plurality of pixels to form an electric field for liquid crystal driving.

The peripheral area means an area other than the active area. A common wiring 30, a GIP (Gate In Panel) circuit 40, an anti-static circuit 50, and a ground wiring 60 are formed in the peripheral area Respectively.

The common wiring 30 is formed on the left and right sides of the active region and is electrically connected to a common electrode formed in the pixel region. A common voltage is applied to the common electrode through the common wiring 30 as described above.

The GIP circuit 40 mounts a driver IC (driver IC) for applying a gate signal to each pixel in a panel. The GIP circuit 40 is formed in the vicinity of the common wiring 30.

The antistatic circuit 50 prevents the thin film transistor T from being damaged due to static electricity generated during the manufacturing process. The static electricity prevention circuit 50 is connected to the data line 20 and the ground line 60, respectively.

The ground wiring 60 is connected to the anti-static circuit 50, and particularly to the left side, the lower side, and the right side of the active area. The ground wiring 60 is formed over three sides of the lower substrate 1 in order to perform a smooth grounding function and has a relatively wide width.

However, such conventional liquid crystal display devices have the following problems.

In recent years, a demand for a product with a new design that can appeal to consumers has been increasing. In order to meet such a demand, efforts are being made to reduce the width of a bezel of a liquid crystal display device.

However, in the conventional case, since the ground wiring 60 formed in the peripheral region of the lower substrate 1 is formed to have a relatively wide width over three sides of the lower substrate 1, there is a limitation in reducing the width of the bezel of the liquid crystal display device .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of reducing the bezel width by changing the design of the ground wiring.

According to an aspect of the present invention, there is provided a liquid crystal display comprising: a first substrate having an active region and a peripheral region; A gate wiring arranged in the active region in a first direction; A data line and a first ground line alternately arranged in the active region in a second direction different from the first direction; And a second ground line formed in the peripheral region and connected to the first ground line.

According to the present invention as described above, the following effects can be obtained.

According to the present invention, since the first ground interconnection is formed in the active area, the area of the second ground interconnection formed in the peripheral area can be reduced, thereby reducing the width of the bezel of the liquid crystal display device.

FIG. 1A is a schematic cross-sectional view of a conventional liquid crystal display device, and FIG. 1B is a schematic plan view of a lower substrate constituting a conventional liquid crystal display device.
2 is a schematic plan view of a first substrate constituting a liquid crystal display device according to an embodiment of the present invention.
3 is a plan view of a first substrate constituting a liquid crystal display according to another embodiment of the present invention.
4 is a plan view of a first substrate constituting a liquid crystal display device according to another embodiment of the present invention.
5 is a plan view of a first substrate constituting a liquid crystal display device according to another embodiment of the present invention.
6 is a schematic cross-sectional view of a liquid crystal display device according to an embodiment of the present invention.

The term "on " as used herein is meant to encompass not only when a configuration is formed directly on top of another configuration, but also to the extent that a third configuration is interposed between these configurations.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

2 is a schematic plan view of a first substrate constituting a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 2, the first substrate 1 constituting the liquid crystal display according to the embodiment of the present invention includes an active region and a peripheral region.

The active region is a region for displaying an image. The gate line 100, the data line 200, the first ground line 610, and the thin film transistor T are formed in the active region.

The gate wiring 100 is arranged in a first direction, for example, in a lateral direction.

The gate wiring 100 includes a first gate wiring 100a and a second gate wiring 100b. The first gate wiring 100a corresponds to an odd gate wiring, the second gate wiring 100b corresponds to an even gate wiring, and the first gate wiring 100a and the second gate wiring 100b One pixel is formed.

Each pixel is arranged in a plurality of rows and columns, and the pixel P ₁₁ located in the first row and the pixel P ₂₁ located in the second row are spaced apart by a predetermined space D therebetween. That is, the pixels located on a line (P ₁₁₎ and the pixel which is located in the second line (P ₂₁₎ is a gate wire (100a, 100b) do not share with each other.

In other words, the pixel P ₁₁ located in the first row is formed in the region between the first gate wiring 100a as the first gate wiring and the second gate wiring 100b as the second gate wiring, and the pixel The pixel P ₂₁ located is formed in the region between the first gate wiring 100a as the third gate wiring and the second gate wiring 100b as the fourth gate wiring.

At this time, no pixel is formed in the space D between the second gate wiring 100b as the second gate wiring and the first gate wiring 100a as the third gate wiring. Therefore, compared with the distance between the first gate wiring 100a as the first gate wiring and the second gate wiring 100b as the second gate wiring, the second gate wiring 100b and the third gate wiring 100b, which are the second gate wiring, The distance between the first gate wirings 100a is shortened.

The gate wiring 100 is connected to a GIP circuit 400 described later.

The data line 200 and the first ground line 610 are arranged in a second direction different from the gate line 100, for example, in the longitudinal direction. Particularly, the data line 200 and the first ground line 610 are alternately arranged with a predetermined distance therebetween. Therefore, each pixel is defined by a combination of the first gate wiring 100a, the second gate wiring 100b, the data wiring 200, and the first ground wiring 610. [

Although the data line 200 is connected to a data driving circuit (not shown), the first ground line 610 is not connected to the data driving circuit.

The thin film transistor T is formed in each pixel. The thin film transistor T is connected to the gate wiring 100 and the data wiring 200 and is not connected to the first ground wiring 610. Therefore, the thin film transistor T is formed on the left side and the right side thereof with a single data line 200 as a center.

Specifically, the thin film transistor T formed in the pixel P ₁₁ located in the first column and the thin film transistor T formed in the pixel P ₁₂ located in the second column are formed at different positions from each other.

By way of example, thin film transistor (T) formed in the first pixel (P ₁₁₎ to position the column is connected to the first gate wire (100a) and the date line 200, therefore, upper right in the pixel (P ₁₁₎ As shown in Fig. On the other hand, the second thin film transistor (T) formed in the pixel (P ₁₂₎ to position the column is connected to the second gate wire (100b) and the date line 200, therefore, the lower left in the pixel (P ₁₂₎ As shown in Fig.

Although not shown, a pixel electrode and a common electrode which form an electric field for liquid crystal driving are formed in each pixel, and a detailed description thereof will be given later.

The peripheral area means an area other than the active area. A common wiring 300, a GIP (Gate In Panel) circuit 400, an anti-static circuit 500, and a second ground wiring 620 Is formed.

The common wiring 300 may be formed on the left and right sides of the active region and is electrically connected to a common electrode formed in the active region. Therefore, a common voltage is applied to the common electrode through the common wiring 300.

The GIP circuit 400 mounts a driver IC for applying a gate signal to each pixel in a panel. The GIP circuit 400 is formed in the vicinity of the common wiring 300. The GIP circuit 400 may be located closer to the edge of the first substrate 1 than the common wiring 300. However, the GIP circuit 400 is not limited to the GIP circuit 400, The first substrate 1 may be located closer to the center of the first substrate 1 than the first substrate 1. On the other hand, in some cases, the GIP circuit 400 may be omitted.

The anti-static circuit 500 prevents the thin film transistor T from being damaged due to static electricity generated during the manufacturing process. The static electricity prevention circuit 500 is connected to the data line 200.

More specifically, the data line 200 extends from the active area to the peripheral area and is connected to the static electricity prevention circuit 500. The static electricity prevention circuit 500 includes the second ground line 620, It is connected.

The second ground wiring 620 is connected to the first ground wiring 610. That is, the first ground wiring 610 extends from the active area to the peripheral area and is connected to the second ground wiring 620. As described above, according to the present invention, since the plurality of first ground wirings 610 are formed in the active region, the area of the second ground wirings 620 formed in the peripheral region can be reduced.

Therefore, it is not necessary to form the second ground wiring 620 in a large area on the left side, the right side and the lower side of the active region as in the conventional case, and it is possible to form the second ground wiring 620 only on the lower side of the active region, have.

Hereinafter, the configuration of the first substrate 1, particularly the pixel configuration, will be described in more detail with reference to FIG.

3 is a plan view of a first substrate 1 constituting a liquid crystal display device according to another embodiment of the present invention, which corresponds to region A in Fig. A detailed description of a configuration overlapping with the above-described configuration will be omitted.

3, the first gate wiring 100a and the second gate wiring 100b are formed in the first direction and the data wiring 200 and the first ground wiring 610 are formed in the second direction in the first direction, And a pixel is defined by the first gate wiring 100a, the second gate wiring 100b, the data wiring 200, and the first ground wiring 610. [

The first gate wiring 100a and the second gate wiring 100b are formed of the same material in the same layer and the data wiring 200 and the first ground wiring 610 are formed of the same material, As shown in FIG.

A gate insulating film is formed in an intermediate layer between the first / second gate wirings 100a and 100b and the data / first ground wirings 200 and 610, thereby insulating the two.

The data line 200 and the first ground line 610 are alternately arranged while being parallel to each other. In particular, the data line 200 and the first ground line 610 are arranged in a curved straight line shape to obtain a multi-domain effect.

A thin film transistor T is formed on the left and right sides of the data line 200. The thin film transistor T includes a gate electrode, an active layer, a source electrode 210, and a drain electrode 220.

The first gate wiring 100a or the second gate wiring 100b functions as the gate electrode. For example, in the case of a pixel on the left side with respect to the data line 200, the first gate line 100a functions as a gate electrode, and in the case of a pixel on the right side of the data line 200, And the two gate wirings 100b function as a gate electrode.

The source electrode 210 is formed by being branched from the data line 200. For example, in the case of a pixel on the left side with respect to the data line 200, the source electrode 210 is branched to the left side in the data line 200, and the source electrode 210 is branched to the right side of the data line 200 The source electrode 210 is branched from the data line 200 to the right. Although the source electrode 210 may be formed in a U-shape as shown in the figure, the source electrode 210 may be formed in various shapes known in the art without limitation.

The drain electrode 220 is spaced apart from the source electrode 210.

The active layer (not shown) is formed in the intermediate layer between the gate electrode and the source / drain electrodes 210 and 220. The active layer may be made of a silicon-based semiconductor or an oxide semiconductor.

The thin film transistor T described above can be modified into various forms known in the art. For example, the thin film transistor T may have a bottom gate structure, but may have a top gate structure.

A pixel electrode 230 and a common electrode 240 are formed in a pixel defined by the first gate wiring 100a, the second gate wiring 100b, the data wiring 200 and the first ground wiring 610 .

The pixel electrode 230 and the common electrode 240 are arranged in parallel with each other. A horizontal electric field is formed between the pixel electrode 230 and the common electrode 240 arranged in parallel, The direction of the liquid crystal can be adjusted by the liquid crystal layer.

The pixel electrode 230 is connected to the drain electrode 220 through a predetermined contact hole. The common electrode 240 is connected to the common electrode connection wiring 250 through a predetermined contact hole. Although not shown, the common electrode connection wiring 250 is connected to the above-described common wiring (refer to reference numeral 300 in FIG. 2).

The common electrode connection line 250 may be formed to overlap the curved region of the data line 200 and the first ground line 610, as shown in FIG. That is, in the curved region, a dislocation may occur, so that the common electrode connection wiring line 250 may be formed in the front line generation region to prevent generation of a front line. However, the common electrode connection wiring 250 is not necessarily formed in the curved region.

The common electrode connection line 250 may be formed of the same material in the same layer as the first and second gate lines 100a and 100b, but is not limited thereto.

An antistatic circuit 500 and a second ground line 620 are formed in the peripheral area outside the active area.

The static electricity prevention circuit 500 can effectively prevent the damage of the thin film transistor T by static electricity generated during the manufacturing process and should not interfere with the driving signal system in the state where static electricity is not generated . Accordingly, the anti-static circuit 500 may include a plurality of driving elements, for example, a plurality of transistors or a plurality of diodes to perform such a function.

The second ground wiring 620 is connected to the first ground wiring 610. The second ground interconnection 620 may be formed in a different layer from the first ground interconnection 610. The second ground interconnection 620 may be formed on the first ground interconnection 620 through a predetermined contact hole, 610).

The second ground wiring 620 may be formed of the same material in the same layer as the first and second gate wirings 100a and 100b, but is not limited thereto.

4 is a plan view of a first substrate 1 constituting a liquid crystal display device according to another embodiment of the present invention.

4 is the same as the previous embodiment except that the connection structure between the first ground wiring 610 and the second ground wiring 620 is changed. Therefore, the same reference numerals are assigned to the same components, and only the different components will be described below.

4, according to another embodiment of the present invention, the first ground wiring 610 and the second ground wiring 620 are connected to each other through a ground connection wiring 625. [

2 and 3, the first ground wiring 610 extends to the second ground wiring 620, and the first ground wiring 610 is electrically connected to the second ground wiring 610. In other words, 620).

4, the first ground interconnection 610 does not extend to the second ground interconnection 620, but instead the first ground interconnection 610 is connected to the ground interconnection 625 And the ground connection wiring 625 is connected to the second ground wiring 620.

The ground connection wirings 625 are arranged so as to cross the plurality of first ground wirings 610 and are connected to the first ground wirings 610. A part of the ground connection wiring 625 may be arranged in parallel with the gate wiring 100 and the rest of the ground connection wiring 625 may extend toward the second ground wiring 620.

The ground connection wiring 625 and the first ground wiring 610 are formed on different layers so that the ground connection wiring 625 and the first ground wiring 610 are connected through a contact hole. The ground connection wiring 625 may be formed of the same material in the same layer as the first and second gate wirings 100a and 100b.

The ground connection wiring 625 and the second ground wiring 620 may be formed in the same layer but are not necessarily limited to each other and may be formed in different layers and may be connected to each other through the contact hole.

5 is a plan view of a first substrate 1 constituting a liquid crystal display device according to another embodiment of the present invention.

The first substrate 1 according to Fig. 5 is the same as the embodiment according to Figs. 2 and 3 described above except that the structure of the second ground wiring 620 is changed. Therefore, the same reference numerals are assigned to the same components, and only the different components will be described below.

5, the second ground wiring 620 may be formed not only on the lower side of the active region but also on the left and right sides of the active region. However, as described above, since the plurality of first ground wirings 610 are formed in the active region according to the present invention, the width of the second ground wirings 620 can be minimized.

On the other hand, the second ground wiring 620 may be formed only on the lower side and the left side of the active region, or on the lower side and the right side of the active region.

FIG. 6 is a schematic cross-sectional view of a liquid crystal display device according to an embodiment of the present invention, and FIG. 6 schematically shows a peripheral region outside an active region.

6, the liquid crystal display according to an embodiment of the present invention includes a first substrate 1, a second substrate 2, a sealant 3, and a liquid crystal layer 4 .

Various structures may be formed on the first substrate 1 as described in the above embodiments, and repetitive description thereof will be omitted.

The second substrate 2 faces the first substrate 1 and a black matrix 700 and a color filter 710 are formed on the second substrate 2. The black matrix 700 is formed entirely in the peripheral region, and the color filter 710 is formed in the active region.

The sealant 3 is formed at the edges of the peripheral region of the first substrate 1 and the second substrate 2 to bond the first substrate 1 and the second substrate 2 together. At this time, the sealant 3 may be overlapped with the second ground wiring 620 formed on the first substrate 1.

The liquid crystal layer 4 is formed between the first substrate 1 and the second substrate 2.

The liquid crystal display according to the present invention as described above is related to the IPS mode. The liquid crystal display according to the present invention can be applied to a liquid crystal display device such as a twisted nematic (TN) mode, a vertical alignment (VA) mode, a fringe field switching And can be modified into various modes.

1: first substrate
100, 100a, 100b: a gate wiring, a first gate wiring, a second gate wiring
200: data wiring 300: common wiring
400: GIP circuit 500: Antistatic circuit
610: first ground wiring 620: second ground wiring
625: Ground connection wiring

Claims

A first substrate having an active region and a peripheral region;
A gate wiring arranged in the active region in a first direction;
A data line and a first ground line alternately arranged in the active region in a second direction different from the first direction; And
And a second ground line formed in the peripheral region and connected to the first ground line.

The method according to claim 1,
Wherein the gate wiring includes a first gate wiring and a second gate wiring, a plurality of pixels are defined by the first gate wiring, the second gate wiring, the data wiring, and the first ground wiring,
Wherein the first pixel and the second pixel among the plurality of pixels are spaced apart from each other by a predetermined space.

The method according to claim 1,
Wherein the data line and the first ground line are formed in the same layer of the same material and are arranged in parallel with each other.

The method according to claim 1,
Wherein the first ground line extends to the second ground line and is connected to the second ground line through a predetermined contact hole.

The method according to claim 1,
Wherein the first ground wiring and the second ground wiring are connected to each other through a ground connection wiring.

6. The method of claim 5,
Wherein a part of the ground connection wiring is arranged parallel to the gate wiring and the rest of the ground connection wiring is extended toward the second ground wiring.

The method according to claim 1,
Wherein the data line is connected to an electrostatic discharge prevention circuit formed in the peripheral region, and the electrostatic discharge prevention circuit is connected to the second ground line.

The method according to claim 1,
And the second ground wiring is formed on the same layer with the same material as the gate wiring.

The method according to claim 1,
And a thin film transistor is connected to the left and right sides of the data line.

The method according to claim 1,
A second substrate facing the first substrate;
A sealant for bonding the first substrate and the second substrate; And
Wherein the sealant further comprises a liquid crystal layer formed between the first substrate and the second substrate, wherein the sealant overlaps with the second ground wiring.