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KR20140077464A - Tspc dynamic flip flop having leakage current compensation function - Google Patents

Tspc dynamic flip flop having leakage current compensation function Download PDF

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Publication number
KR20140077464A
KR20140077464A KR1020120146304A KR20120146304A KR20140077464A KR 20140077464 A KR20140077464 A KR 20140077464A KR 1020120146304 A KR1020120146304 A KR 1020120146304A KR 20120146304 A KR20120146304 A KR 20120146304A KR 20140077464 A KR20140077464 A KR 20140077464A
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node
terminal
logic value
logic
signal
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KR1020120146304A
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Korean (ko)
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장영찬
이한열
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금오공과대학교 산학협력단
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356165—Bistable circuits using complementary field-effect transistors using additional transistors in the feedback circuit

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Abstract

The present invention relates to a technique for enabling a TS PC dynamic flip-flop including a CMOS transistor fabricated in a microprocessing process to be performed from a low-speed operation to a high-speed operation by adding a leakage current compensation circuit of a feedback circuit structure to a TS PC dynamic flip- .
According to another aspect of the present invention, there is provided a logic circuit comprising: a first logic unit for outputting logic values according to input data and a clock signal to an A node; A second logic unit for outputting a logic value according to the clock signal and the signal supplied from the node A to the node B; A third logic unit for outputting a signal supplied from the B node and a logic value according to the clock signal to the C node; An output unit for outputting the corresponding data to the Q node according to a logic value supplied from the C node; And when any one of the nodes A to C of the first to third logic units is in a floating state, a signal of a downstream node having a logic value opposite to that of the corresponding node is fed back to the corresponding node, And a compensating leakage current compensating unit.

Description

TECHNICAL FIELD [0001] The present invention relates to a TSPC DYNAMIC FLIP FLOP HAVING LEAKAGE CURRENT COMPENSATION FUNCTION with a leakage current compensation function,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design technique of a TSPC Dynamic Flip / Flop (TSPC), and more particularly, to a method of designing a dynamic flip flop including a CMOS transistor fabricated in a fine process, The present invention relates to a TS flip flop having a leakage current compensation function.

FIG. 1 is a circuit diagram of a TSPC (True Single Pulse Clocked) dynamic flip-flop circuit according to the related art. As shown in FIG. 1, the 1-3 logic unit 11-13 and the output unit 14 Respectively.

The first logic unit 11 includes first and second PMOS transistors PM1 and PM2 and a first NMOS transistor NM1 connected in series between a power supply terminal VDD and a ground terminal, And outputs a logic value according to the clock signal (D) and the clock signal (clk) to the node A

When the data D supplied to the gates of the first PMOS transistor PM1 and the first NMOS transistor NM1 is "1 ", the logic value of the A node becomes" 0 ". The logic value of the node A becomes the inverted value of the data D when the logic value of the clock signal clk supplied to the gate of the second PMOS transistor PM2 is "0 ". When the logic value of the clock signal clk is "1 ", and the logic value of the data D is" 0 ", the A node is floated to hold (store) the previous logic value.

The second logic section 12 includes a third PMOS transistor PM3 and second and third NMOS transistors NM2 and NM3 connected in series between the power supply terminal VDD and the ground terminal, And outputs a logic value supplied from the A node and a logic value corresponding to the clock signal clk to the B node.

The logic value of the B node is "1" when the logic value of the clock signal clk supplied to the gates of the third PMOS transistor PM3 and the third NMOS transistor NM3 is "0 ". The logic value of the B node is "0" when the logic value of the clock signal clk is "1 ", and the logic value supplied from the A node to the gate of the second NMOS transistor NM2 is & to be. When the logic value of the A node is "0 ", the B node is floated and retains the previous logic value.

The third logic section 13 includes a fourth PMOS transistor PM4 and fourth and fifth NMOS transistors NM4 and NM5 connected in series between the power supply terminal VDD and the ground terminal, And outputs the data supplied from the B node and the logic value according to the clock signal clk to the C node.

The logic value of the C node is "1" when the logic value of the B node supplied to the gates of the fourth PMOS transistor PM4 and the fifth NMOS transistor NM5 is "0 ". The logic value of the C node becomes the inverted logic value of the logic value of the B node when the logic value of the clock signal clk supplied to the gate of the fourth NMOS transistor NM4 is "1 ". When the logic value of the clock signal clk is "0" and the logic value of the B-node is "1 ", the C-node floats to maintain the previous logic value.

The output section 14 includes a fifth PMOS transistor PM5 and a sixth NMOS transistor NM6 connected in series between the power supply terminal VDD and the ground terminal and is connected to the logic value supplied from the C node And outputs the corresponding data to the Q node which is an output terminal.

The inverted logic value of the logic value supplied from the C node to the gates of the fifth PMOS transistor PM5 and the sixth NMOS transistor NM6 is outputted to the Q node.

As a result, as described above, the A to C nodes store the previous logic value when they are in the floating state (interval), and the stored logic values are sequentially transmitted to the Q node side, and one of the clock signals clk Lt; / RTI >

FIG. 2 is a timing chart of the nodes A, B, and C, the node Q, the data D, and the clock signal clk in FIG. In FIG. 2, a solid line indicates a waveform when the TSPC dynamic flip-flop 10 shown in FIG. 1 operates normally, and a dotted line indicates a malfunction waveform due to a leakage current due to a long floating time.

As described above, the floating period of the node A is when the logic value of the clock signal clk is "1 ", the logic value of the data D is" 0 ", and the logic value of the node B and the inverted value . The floating period of the B-node is when the logic value of the clock signal clk is "1", the logic value of the A-node is "0", and the logic value of the C-node is inverted. The floating period of the C node is when the logic value of the clock signal clk is "0 ", the logic value of the B node is" 1 ", and the logic value of the Q node is inverted.

As a result, each floating interval of the nodes A, B, and C is determined by the clock signal clk and the logic value of the immediately preceding node, and the determined logic value has a value inverted from the next node value.

The TSPC dynamic flip-flop 10 as described above is used in a digital system requiring high-speed operation. This TSPC dynamic flip-flop 10 operates by the charge that is charged and discharged to the parasitic capacitor of the floating node as described above. The floating node is a node (A, B, and C nodes) connected to a power supply terminal VDD through a CMOS transistor such as the PMOS transistors PM2, PM3, and PM4 when the corresponding CMOS transistor is turned off The connection to the power supply terminal VDD is cut off, in which the amount of charge corresponding to the previous logic value is maintained in the parasitic capacitor of the node.

Ideally, the amount of charge stored in the parasitic capacitor of the node must be maintained constantly, but a leakage current is generated by the turned-off CMOS transistor and the amount of charge gradually decreases. If the floating time of the floating node becomes long, a malfunction may be caused by the leakage current as described above. When a CMOS transistor is manufactured in a fine process, line width or the like becomes denser and malfunction due to the leakage current is more frequently generated.

Nevertheless, the conventional TSPC dynamic flip-flop does not have a proper countermeasure function against the leakage current, so that it can be used only for high-speed operation and can not be used for low-speed operation.

A problem to be solved by the present invention is to add a leakage current compensation circuit of a feedback circuit structure to a TS flip-flop so that a DSF dynamic flip-flop including a CMOS transistor fabricated in a microprocess can be operated from a low speed operation to a high speed operation have.

A first and a second PMOS transistors serially connected in series between a power terminal and a ground terminal, and a first PMOS transistor connected in series between the power terminal and the ground terminal, A first logic unit for outputting a logic value according to the data and the clock signal to the node A; And a third PMOS transistor and a second and third NMOS transistors serially connected in series between the power supply terminal and the ground terminal, wherein a logic value according to the clock signal and a signal supplied from the A node is supplied to the B node A second logic section for outputting the second logic section; And a fourth PMOS transistor and fourth and fifth NMOS transistors serially connected in series between the power supply terminal and the ground terminal, wherein a signal supplied from the B node and a logic value according to the clock signal are supplied to the C node A third logic unit for outputting the third logic unit; An output unit having a fifth PMOS transistor and a sixth NMOS transistor serially connected in series between the power supply terminal and the ground terminal and outputting the corresponding data to the Q node according to a logic value supplied from the C node; And when any one of the nodes A to C of the first to third logic units is in a floating state, a signal of a downstream node having a logic value opposite to that of the corresponding node is fed back to the corresponding node, And a compensating leakage current compensating unit.

The present invention is advantageous in that a DSC dynamic flip flop including a CMOS transistor fabricated in a fine process is enabled from a low speed operation to a high speed operation by adding a leakage current compensation circuit of a feedback circuit structure to a TS PC dynamic flip flop, There is an effect that a malfunction due to a leakage current can be reliably prevented.

1 is a circuit diagram of a TS flip flop having a leakage current compensation function according to the related art.
2 is a timing chart of each part of Fig.
3 is a circuit diagram of a TS flip-flop having a leakage current compensation function according to the present invention.
Fig. 4 (a) is a detailed circuit diagram of the inverter of Fig. 3; Fig.
4 (b) is a simplified diagram showing input and output signals and control signals in the inverter of FIG. 3. FIG.
FIG. 5 is a waveform diagram of a result of a simulation to compare a TSPC dynamic flip flop according to the present invention and a conventional TSPC dynamic flip flop.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a DSC dynamic flip-flop having a leakage current compensation function according to an embodiment of the present invention. As shown in FIG. 3, the first logic unit 31, the second logic unit 32, An output section 34, and a leakage current compensating section 35. The leakage current compensating section 35 includes:

The first logic unit 31 includes first and second PMOS transistors PM1 and PM2 and a first NMOS transistor NM1 connected in series between the power supply terminal VDD and the ground terminal, A logic value D2 corresponding to the data D supplied to the gates of the first PMOS transistor PM1 and the first NMOS transistor NM1 and the clock signal clk supplied to the gate of the second PMOS transistor PM2 To the A node which is the common connection node between the other terminal of the second PMOS transistor PM2 and one terminal of the first NMOS transistor NM1.

The second logic unit 32 includes a third PMOS transistor PM3 and second and third NMOS transistors NM2 and NM3 connected in series between the power supply terminal VDD and the ground terminal, The logic value according to the logic value supplied from the A node to the gate of the second NMOS transistor NM2 and the clock signal clk supplied to the gate of the third PMOS transistor PM3, To the node B which is the common connection node between the other terminal of the second PMOS transistor PM3 and one terminal of the second NMOS transistor NM2.

The third logic section 33 includes a fourth PMOS transistor PM4 and fourth and fifth NMOS transistors NM4 and NM5 connected in series between the power supply terminal VDD and the ground terminal, The logic value supplied from the B node to the gates of the fourth PMOS transistor PM4 and the fifth NMOS transistor NM5 and the clock signal clk supplied to the gate of the fourth NMOS transistor NM4 And outputs a logic value to the other node of the fourth PMOS transistor PM4 and the node C which is a common connection node of one terminal of the fourth NMOS transistor NM4.

The output section 34 includes a fifth PMOS transistor PM5 and a sixth NMOS transistor NM6 connected in series between the power supply terminal VDD and the ground terminal, The common terminal of the other terminal of the fifth PMOS transistor PM5 and the terminal of one terminal of the sixth NMOS transistor NM6 in accordance with the logic value supplied to the gate of the transistor PM5 and the sixth NMOS transistor NM6, And outputs the corresponding data to the Q node (output node) which is a node.

The leakage current compensating unit 35 includes a first inverter 36A, a second inverter 36B and a third inverter 36C so that when the nodes A, B, and C are in a floating state, Is fed back to the node of the previous stage, thereby preventing malfunction due to the leakage current.

The operation principle of the first logic unit 31, the second logic unit 32, the third logic unit 33 and the output unit 34 is similar to that of a conventional TS flip-flop. As follows.

 When the data D supplied to the gates of the first PMOS transistor PM1 and the first NMOS transistor NM1 is "1" in the first logic unit 31, the logic value of the A node is "0 ". The logic value of the node A becomes the inverted value of the data D when the logic value of the clock signal clk supplied to the gate of the second PMOS transistor PM2 is "0 ". When the logic value of the clock signal clk is "1 ", and the logic value of the data D is" 0 ", the A node is floated to hold (store) the previous logic value.

 When the logic value of the clock signal clk supplied to the gates of the third PMOS transistor PM3 and the third NMOS transistor NM3 is "0" in the second logic section 32, Is "1 ". The logic value of the B node is "0" when the logic value of the clock signal clk is "1 ", and the logic value supplied from the A node to the gate of the second NMOS transistor NM2 is & to be. When the logic value of the A node is "0 ", the B node is floated and retains the previous logic value.

In the third logic section 13, when the logic value of the B-node supplied to the gates of the fourth PMOS transistor PM4 and the fifth NMOS transistor NM5 is "0 ", the logic value of the C- Quot; 1 ". The logic value of the C node becomes the inverted logic value of the logic value of the B node when the logic value of the clock signal clk supplied to the gate of the fourth NMOS transistor NM4 is "1 ". When the logic value of the clock signal clk is "0" and the logic value of the B-node is "1 ", the C-node floats to maintain the previous logic value.

In the output section 14, the inverted logic value of the logic value supplied from the C node to the gates of the fifth PMOS transistor PM5 and the sixth NMOS transistor NM6 is output to the Q node.

As a result, as described above, the A to C nodes store the previous logic value in the floating interval, and the stored logic value is sequentially transmitted to the Q node side and is stored for one period of the clock signal clk.

As described above, the floating period of the node A is when the logic value of the clock signal clk is "1 ", the logic value of the data D is" 0 ", and the logic value of the node B and the inverted value . The floating period of the B-node is when the logic value of the clock signal clk is "1", the logic value of the A-node is "0", and the logic value of the C-node is inverted. The floating period of the C node is when the logic value of the clock signal clk is "0 ", the logic value of the B node is" 1 ", and the logic value of the Q node is inverted.

Each floating interval of the nodes A, B, and C is determined by the clock signal clk and the logic value of the immediately preceding node, and the determined logic value has a value inverted from the next node value.

Meanwhile, the leakage current compensating unit 35 compensates (suppresses) leakage currents of the nodes A, B, and C, which will be described in detail as follows.

The leakage current compensating unit 35 includes a first to third inverters 36A to 36C. FIG. 4A shows an example in which the first to third inverters 36A to 36C are implemented by CMOS transistors will be.

4A, the inverter 35 includes sixth and seventh PMOS transistors PM6 and PM7 connected in series between the power supply terminal VDD and the ground terminal, and seventh and eighth NMOS transistors NM7, and NM8. An input voltage Vin is supplied to the gate of the sixth PMOS transistor PM6 and the gate of the eighth NMOS transistor NM8. The control signal a is supplied to the gate of the seventh PMOS transistor PM7 and the control signal b is supplied to the gate of the seventh NMOS transistor NM7. An output voltage Vout is generated from a common connection point between the other terminal of the seventh PMOS transistor PM7 and one terminal of the seventh NMOS transistor NM7.

4 (b) is a block diagram of FIG. 4 (a). Here, "a" is a control signal supplied to the gate of the seventh PMOS transistor PM7, The node signal A, and the clock signal clk. "B" corresponds to one of the node signal B and the clock signal clk in FIG. 3 as a control signal supplied to the gate of the seventh NMOS transistor NM7.

The operation of the inverter 35 shown in FIG. 4 (a) is the same as the truth table shown in [Table 1] below. For example, if the logic value of the control signal a is '0' and the logic value of the control signal b is '1', the logic value of the output voltage Vout is the inverted logic of the input voltage Vin Lt; / RTI > The logic value of the output voltage Vout becomes '1' when the logic values of the input voltage Vin and the control signals a and b are '0'. When the logic values of the input voltage Vin and the control signals a and b are both '1', the logic value of the output voltage Vout becomes '0'. In the remaining case, the terminal of the output voltage Vout becomes an open state (High Impedance = High-Z).

Figure pat00001

Table 2 below shows a truth table of the TS flip flop 30 shown in FIG.

Figure pat00002

The operation of compensating the leakage currents of the nodes A, B, and C using the first to third inverters 36A to 36C will be described below.

When node A is in a floating state, node B is not in a floating state. In this state, the input data D and the clock signal clk are used as the control signal of the first inverter 36A, and the signal of the node B having the inverted logic value of the node A is input to the first inverter 36A To the A node. This compensates for the fact that the A node is driven by the inverted signal of the B node (e.g., "1") and the amount of charge stored in the parasitic capacitor of the A node is reduced by the leakage current.

When the B node is in the floating state, the C node is not in the floating state. In this state, the signal of the node A and the clock signal clk are used as the control signal of the second inverter 36B, and the signal of the node C having the inverted logic value of the node B is transmitted through the second inverter 36B Feedback to the B node. This compensates for the fact that the B node is driven by the inverted signal of the C node (e.g., "1") and the amount of charge stored in the parasitic capacitor of the B node is reduced by the leakage current.

When the C node is in the floating state, the B node is not in the floating state. In this state, the signal of the node B and the clock signal clk are used as the control signal of the third inverter 36C to feed back the signal of the node Q to the node C through the third inverter 36C. By doing so, it is compensated that the C node is driven by the inverted signal of the Q node (e.g., "1") and the amount of charge stored in the C node parasitic capacitor is reduced by the leakage current.

The leakage current compensating unit 35 operates only when the corresponding node among the nodes A to C is in the floating state or both the input signal and the control signal are "0" or "1 " (High-Z) in the remaining case, and thus does not affect the operation of the TSPC dynamic flip-flop 30. [ In addition, the leakage current compensating unit 35 is connected in parallel with the portion excluding the self-refreshing flip-flop 30 in the TSPC dynamic flip-flop 30, so that the operation speed of the TSPC dynamic flip-flop 30 is not affected.

5 is a waveform diagram showing a result of simulation for a conventional TSPC dynamic flip-flop and a TSPC dynamic flip-flop 30 according to the present invention under the condition that the frequency of the clock signal clk is 1 MHz. As shown in FIG. 5, the conventional TSPC dynamic flip flop malfunctions due to the leakage current, whereas the TSPC dynamic flip flop according to the present invention operates normally.

Table 3 below shows the simulation results of a comparative analysis of setup time, hold time, input / output delay time, and power consumption for the TSPC dynamic flip-flop according to the prior art and the TSPC dynamic flip-flop according to the present invention. As shown in the figure, the power consumption of the DSC dynamic flip-flop having the leakage current compensation function according to the present invention is 8.8% higher than that of the TSPC dynamic flip-flop according to the related art.

Figure pat00003

Although the preferred embodiments of the present invention have been described in detail above, it should be understood that the scope of the present invention is not limited thereto. These embodiments are also within the scope of the present invention.

31: first logic unit 32: second logic unit
33: third logic section 34: output section
35: Leakage current compensating unit 36A: First inverter
36B: second inverter 36C: third inverter

Claims (7)

And first and second PMOS transistors serially connected in series between a power supply terminal and a ground terminal, wherein a logic value according to input data and a clock signal is connected to the other terminal of the second PMOS transistor To a node A which is a common connection node of one terminal of the first NMOS transistor;
And a third PMOS transistor and a second and third NMOS transistors serially connected in series between the power supply terminal and the ground terminal, wherein the logic value according to the clock signal and the signal supplied from the A node, A second logic section for outputting the other terminal of the PMOS transistor to a node B which is a common connection node of one terminal of the second NMOS transistor;
And a fourth PMOS transistor and fourth and fifth NMOS transistors serially connected in series between the power supply terminal and the ground terminal, wherein a signal supplied from the B node and a logic value according to the clock signal are supplied to the fourth A third logic section for outputting the other terminal of the PMOS transistor to a node C which is a common connection node of one terminal of the fourth NMOS transistor;
And a fifth PMOS transistor and a sixth NMOS transistor serially connected in series between the power supply terminal and the ground terminal, wherein the other terminal of the fifth PMOS transistor and the second terminal of the fifth PMOS transistor, An output section for outputting the corresponding data to a Q node which is a node of a common node of one terminal of the sixth MOS transistor; And
When any one of nodes A to C of the first to third logic units is in a floating state, a signal of a rear node having a logic value opposite to that of the corresponding node is fed back to the corresponding node, And a leakage current compensating unit for compensating a leakage current of the TS flip flop.
2. The TS dynamic flip-flop according to claim 1, wherein a signal of a rear-end node that feeds back the leakage current compensating section to the corresponding node has a logic value of "1 ".
The apparatus of claim 1, wherein the leakage current compensation unit
A first inverter for receiving the signal of the node B having the inverted logic value of the node A, and feeding the signal of the node B to the node A under the control of the input data and the clock signal when the node A is in a floating state;
A second inverter for receiving the signal of the node A and the clock signal to feed back the signal of the node C having the inverted logic value of the node B to the node B when the node B is in a floating state; And
And a third inverter for receiving the signal of the B node and the clock signal to feed back the signal of the Q node to the C node when the C node is in a floating state. Equipped TS flip flop.
4. The inverter of claim 3, wherein the first to third inverters include an inverter having a sixth and seventh PMOS transistors and a seventh and eighth NMOS transistors serially connected in series between a power supply terminal and a ground terminal , The inverter is supplied with the input voltage to the gate of the sixth PMOS transistor and the gate of the eighth NMOS transistor, and the respective control signals are supplied to the gates of the seventh PMOS transistor and the seventh NMOS transistor And an output voltage is generated from a common connection point between the other terminal of the seventh PMOS transistor and one terminal of the seventh NMOS transistor.
The apparatus of claim 3, wherein the first inverter has an input terminal connected to the B node, an output terminal connected to the A node, a terminal of the input data connected to one control terminal, And the terminal of the signal is connected to the terminal of the TS flipflop.
4. The method of claim 3, wherein the second inverter has an input terminal connected to the C node, an output terminal connected to the B node, the A node connected to one control terminal, And the terminal is connected to the terminal of the TS flip flop.
4. The method of claim 3, wherein the third inverter has an input terminal connected to the Q node, an output terminal connected to the C node, a terminal of the clock signal connected to one control terminal, And a node is connected to the first and second flip-flops.
KR1020120146304A 2012-12-14 2012-12-14 Tspc dynamic flip flop having leakage current compensation function KR20140077464A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105162438A (en) * 2015-09-28 2015-12-16 东南大学 TSPC (True Single Phase Clock) type data flip-flop (DFF) capable of reducing glitch
CN109756207A (en) * 2018-11-21 2019-05-14 西北工业大学 A kind of TSPC edge triggered flip flop with automatic feedback gated clock
CN110677141A (en) * 2019-09-30 2020-01-10 杭州嘉楠耘智信息科技有限公司 Dynamic D trigger, data operation unit, chip, force calculation board and computing equipment
CN110690887A (en) * 2019-09-30 2020-01-14 杭州嘉楠耘智信息科技有限公司 Dynamic latch, data operation unit, chip, force calculation board and computing equipment
CN110708041A (en) * 2019-09-30 2020-01-17 杭州嘉楠耘智信息科技有限公司 Electric leakage feedback dynamic D trigger, data operation unit, chip, force calculation board and computing equipment
CN110706731A (en) * 2019-09-30 2020-01-17 杭州嘉楠耘智信息科技有限公司 Electric leakage compensation dynamic register, data arithmetic unit, chip, force calculation board and computing equipment
CN111769826A (en) * 2020-06-19 2020-10-13 易兆微电子(杭州)股份有限公司 TSPC trigger with setting and resetting functions

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105162438A (en) * 2015-09-28 2015-12-16 东南大学 TSPC (True Single Phase Clock) type data flip-flop (DFF) capable of reducing glitch
CN109756207A (en) * 2018-11-21 2019-05-14 西北工业大学 A kind of TSPC edge triggered flip flop with automatic feedback gated clock
CN110677141A (en) * 2019-09-30 2020-01-10 杭州嘉楠耘智信息科技有限公司 Dynamic D trigger, data operation unit, chip, force calculation board and computing equipment
CN110690887A (en) * 2019-09-30 2020-01-14 杭州嘉楠耘智信息科技有限公司 Dynamic latch, data operation unit, chip, force calculation board and computing equipment
CN110708041A (en) * 2019-09-30 2020-01-17 杭州嘉楠耘智信息科技有限公司 Electric leakage feedback dynamic D trigger, data operation unit, chip, force calculation board and computing equipment
CN110706731A (en) * 2019-09-30 2020-01-17 杭州嘉楠耘智信息科技有限公司 Electric leakage compensation dynamic register, data arithmetic unit, chip, force calculation board and computing equipment
CN111769826A (en) * 2020-06-19 2020-10-13 易兆微电子(杭州)股份有限公司 TSPC trigger with setting and resetting functions
CN111769826B (en) * 2020-06-19 2023-11-07 易兆微电子(杭州)股份有限公司 TSPC trigger with setting and resetting functions

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