KR20140054624A - Power semiconductor device - Google Patents

Abstract

A power semiconductor device according to an embodiment includes a substrate, a source and a drain which are arranged separately from each other on the substrate, a gate finger which is arranged between the source and the drain, a gate pad which is separated from the gate finger by the source and has N gate feeding points (where N is two or more positive integers) which are connected to a gate voltage, N gate connection parts which electrically connect the N gate feeding points and the gate finger, and N gate landing pads which electrically connect the N gate connection parts and the gate finger.

Description

[0001] Power semiconductor device [0002]

An embodiment relates to a power semiconductor device.

Gallium nitride (GaN) materials with broad energy bandgap characteristics are suitable for power semiconductor devices such as power switches, such as excellent forward characteristics, high breakdown voltage, and low intrinsic carrier density.

As a power semiconductor device, a Schottky barrier diode, a metal semiconductor field effect transistor, or a high electron mobility transistor (HEMT) are available.

As the application range of power semiconductor devices extends to radio frequency (RF) radio transmission systems such as base stations, satellite communications, and defense, there is a demand for power semiconductor devices that simultaneously satisfy not only high frequency characteristics but also high power characteristics .

1 shows a plan view of a conventional HEMT.

The conventional HEMT shown in Fig. 1 includes source pads 12, 14, drain pads 22, gate pads 32 and gate fingers 34, 36. The source 16,18, the drain 24 and the gate 35,37 are located within the active area 40. [ The gate fingers 34 and 36 correspond to the gates 35 and 37 located in the active region 40, respectively. The conventional HEMT shown in Fig. 1 has one gate feeding point 50, 52 per unit gate finger 34, 36. That is, the gate finger 34 has one gate feeding point 50, and the gate finger 36 has one gate feeding point 52.

Figure 2 is a graph showing the general relationship between the gate width (W _g) and the gate resistance (R _g), 3 is a graph showing the general relationship between the gate width (W _g) and the maximum resonant frequency (f _max).

Referring to Figs. 1 to 3, in order to satisfy a high power characteristic, it is necessary to increase the breakdown voltage and current amount of the HEMT. When the gate width W _g is increased, the amount of current of the HEMT is increased, but the gate resistance R _g increases as shown in FIG. 2, and the maximum resonance frequency f _max decreases as shown in FIG. 3 There is a problem. Therefore, in order to increase the amount of current, it is necessary to lower the increase of the gate resistance (R _g ) in order to prevent the deterioration of the high-frequency characteristics when increasing the gate width (W _g ).

The embodiment provides a power semiconductor device capable of compensating for phase difference as well as high frequency characteristics as well as high power characteristics.

A power semiconductor device of an embodiment includes: a substrate; A source and a drain spaced apart from each other on the substrate; A gate finger disposed between the source and the drain; A gate pad spaced apart from the gate finger by the source and having N gate coupling points connected to the gate voltage, wherein N is a positive integer greater than or equal to 2; N gate connections electrically connecting the N gate feeding points to the gate finger; And N gate landing pads electrically connecting the N gate connections to the gate fingers.

The N gate landing pads may be spaced apart from one another by a predetermined distance.

The N gate connections may include N wires electrically connecting the N gate feeding points and the gate landing pad in an air bridge fashion.

Alternatively, the power semiconductor device may further include an insulating layer disposed over the gate pad, the source, the drain, and the gate landing pad, the insulating layer having a through hole exposing an upper surface of the gate pad and an upper surface of the gate landing pad. And the N gate connections may be embedded in the through holes to electrically connect the exposed upper surface of the gate pad to the exposed upper surface of the gate landing pad.

The gate landing pad has a sloped outer surface, and the first distance that the outer surface and the source are spaced apart from each other may increase as the distance from the source increases. Or / and the gate landing pad has a sloped outer surface, and the second distance, in which the outer peripheries and the drains are spaced apart from each other, may increase as the distance is away from the drain. For example, the outer edge of the gate landing pad may have a rhombus shape.

N may be determined as follows according to the resistance value of the gate.

Here, R _g represents a resistance value of the gate, and R _ref represents a resistance value of the gate when N = 1.

The power semiconductor device according to the embodiment can provide a plurality of gate feeding points per one gate finger to lower the rate of increase of the gate resistance value R _g even though the increased gate width W _g is increased Not only high power characteristics and high frequency characteristics can be satisfied at the same time, but also the phase difference can be compensated.

1 shows a plan view of a conventional HEMT.
Figure 2 is a graph showing the general relationship between gate width and gate resistance.
3 is a graph showing the general relationship between the gate width and the maximum resonant frequency.
4 is a plan view of the power semiconductor device according to the embodiment.
5 is a plan view of a power semiconductor device according to another embodiment.
6 is a plan view of a power semiconductor device according to another embodiment.
7 is a graph showing the relationship of the gate resistance value to the gate width.
FIGS. 8A and 8B are partial cross-sectional views of an embodiment of the power semiconductor device taken along line 7-7 'shown in FIGS.
FIG. 9 is a plan view showing an enlarged view of the portion 'A' in FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate understanding of the present invention. However, the embodiments according to the present invention can be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the invention are provided to more fully describe the present invention to those skilled in the art.

In the description of embodiments according to the present invention, in the case of being described as being formed "on" or "under" of each element, the upper or lower (lower) (on or under) all include that two elements are in direct contact with each other or that one or more other elements are indirectly formed between the two elements. Also, when expressed as "on" or "under", it may include not only an upward direction but also a downward direction with respect to one element.

The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not entirely reflect the actual size.

Fig. 4 shows a plan view of the power semiconductor element 100A according to the embodiment, where N = 2.

The power semiconductor device 100A illustrated in Figure 4 includes source pads 112 and 114, a drain pad 122A, a gate pad 132, a gate finger 134, two gate landing pads 162 , 164 and two gate connections 172, 174.

The source 116 is defined within an active area 140 and the drain pad 122A within the active area 140 is defined as the drain 124 and the gate finger 134 in the active area 140 Is defined as the gate 136. This is because the source 116, the drain 124 and the gate 136 located in the active region 140 have a major influence on the operation of the power semiconductor device 100A.

The source pads 112 and 114, the drain pad 122A and the gate pad 132 are connected to the power semiconductor device 100A illustrated in FIG. 4 by another power semiconductor device (not shown), a transistor (not shown), a diode (Not shown), a resistor (not shown) or a capacitor (not shown), or a bonding area for packaging. The length of the gate 136 (L _g) with a width (W _g) are actually ㎛ or ㎚ because it is difficult to connect directly to the other element and the gate 136 of the outside, the size of gate 136 also as a bonding for packaging Is very small. Therefore, the gate pad 132 is used for connecting the gate 136 to another external element or for bonding for packaging.

The gate landing pads 162 and 164 are used as an area for connecting the gate finger 134 and the gate pad 132 since the gate 136 is very small.

On the other hand, the gate finger 134 is disposed between the source 116 and the drain 124.

The gate pad 132 is spaced apart from the gate finger 134 via the source 116. In addition, the gate pad 132 has N gate feeding points 150, 152. The gate feeding points 150 and 152 are defined as the points where the gate voltage is applied. Here, N is a positive integer of 2 or more. The embodiment illustrated in FIG. 4 shows, but is not limited to, N = 2.

Each of the gate pads 132 and the gate fingers 134 described above may include a metal material, for example, a refractory metal or a mixture of such refractory metals. Alternatively, each of the gate pad 132 and the gate finger 134 may be formed of at least one of Ta (Tantalum), TaN (Tantalum Nitride), TiN (Titanium Nitride), Pd (Palladium), W (tungsten) and WSi ₂ It may contain one substance. The constituent material of the gate finger 134 and the constituent material of the gate pad 132 may be the same or different from each other.

Each of the source pads 112 and 114, the source 116 drain pads 122A, and the drain 124 may be formed of a metal. Each of the source pads 112 and 114, the source 116, the drain pad 122A and the drain 124 may include the same material as the gate pad 132 or the gate finger 134. Each of the source pads 112 and 114, the source 116, the drain pad 122A and the drain 124 may be formed of a reflective electrode material having an ohmic characteristic and may be formed of, for example, aluminum (Al), titanium Layer structure including at least one of titanium (Ti), chrome (Cr), nickel (Ni), copper (Cu), and gold (Au). The constituent materials of the source pads 112 and 114, the source 116, the drain pad 122A, and the drain 124 may be different from each other or may be the same.

According to the embodiment illustrated in FIG. 4, two gate feeding points 150, 152 are provided per gate finger 134.

The two gate connections 172 and 174 electrically connect the two gate feeding points 150 and 152 to the gate finger 134.

At this time, the gate finger 134 is electrically connected to the two gate connections 172 and 174 by the two gate landing pads 162 and 164, respectively. In the case of FIG. 4, the gate landing pads 162 and 164 are spaced apart from each other by a certain distance, but the embodiment is not limited to this.

5 is a plan view of the power semiconductor device 100B according to another embodiment, and shows a case where N = 3. And W _g1 and W _g2 represent the widths of the gates 134-1 and 134-2, respectively.

The power semiconductor device 100B illustrated in Figure 5 includes source pads 112 and 114, a drain pad 122B, a gate pad 132, a gate finger 134, three gate landing pads 162,164 and 166, And three gate connections 172, 174, and 176.

In Figure 5, the sources 116-1 and 116-2 are respectively defined in the active regions 142 and 144 and the drain pad 122B located in the active regions 142 and 144 is connected to the drains 124-1 and 124 -2 and gate fingers 134 located within active regions 142 and 144 are defined as gates 134-1 and 134-2, respectively.

Within active region 142, gate 134-1 is disposed between source 116-1 and drain 124-1. Within active region 144, gate 134-2 is disposed between source 116-2 and drain 124-2.

The gate pad 132 is disposed apart from the gate finger 134 via the source 116, which is the same as that of FIG. In addition, the gate pad 132 has three gate feeding points 150, 152, 154.

Here, the number of the gate fingers 134 is one, and three gate landing pads (150, 152, 154) are provided to connect one gate finger 134 to the three gate feeding points 150, 152, 154 on the gate pad 132 162, 164, and 166 are disposed on top of the gate finger 134.

The three gate connections 172, 174 and 176 also electrically connect the three gate feeding points 150, 152 and 154 to the gate finger 134.

At this time, the gate finger 134 is electrically connected to the three gate connections 172, 174 and 176 by the three gate landing pads 162, 164 and 166, respectively. In the case of FIG. 5, the three gate landing pads 162, 164 and 166 are spaced apart from one another by a certain distance, but the embodiment is not limited to this.

In addition, the drain pad 122A of FIG. 4 does not have a groove, whereas the drain pad 122B of FIG. 5 may have a single groove 123. Here, the groove 123 contributes to forming a space for the gate landing pad 166.

Other parts of the power semiconductor device 100B illustrated in FIG. 5 are the same as those of the power semiconductor device 100A illustrated in FIG. 4, and thus a detailed description thereof will be omitted.

FIG. 6 shows a plan view of a power semiconductor device 100C according to another embodiment, where N = 4. W _g1 , W _g2 And W _g2 represent the widths of the gates 134-1, 134-2, and 134-3, respectively.

The power semiconductor device 100C illustrated in FIG. 6 includes source pads 112 and 114, a drain pad 122C, a gate pad 132, a gate finger 134, four gate landing pads 162, 164, 167, 168, and four gate connections 172, 174, 177, 178.

In Figure 6, the sources 116-1, 116-2, and 116-3 are defined within the active regions 142, 144, and 146, respectively, and the drain pads 122C located within the active regions 142, 144, And gate fingers 134 located within the active regions 142, 144 and 146 are respectively defined as gates 134-1, 134-2, 134-3 Respectively.

Within active region 142, gate 134-1 is disposed between source 116-1 and drain 124-1. Within active region 144, gate 134-2 is disposed between source 116-2 and drain 124-2. In the active region 146, a gate 134-3 is disposed between the source 116-3 and the drain 124-3.

The gate pad 132 is disposed apart from the gate finger 134 via the source 116, which is the same as that of FIG. In addition, the gate pad 132 has four gate feeding points 150, 152, 156, 158.

Here, the number of the gate fingers 134 is one and four gate landings 150, 152, 156, and 158 are provided to connect one gate finger 134 to the four gate feeding points 150, 152, 156, and 158 on the gate pad 132. [ Pads 162, 164, 167 and 168 are disposed on top of the gate finger 134.

The four gate connections 172, 174, 177 and 178 electrically connect the four gate feeding points 150, 152, 156 and 158 to the gate finger 134.

At this time, the gate finger 134 is electrically connected to the four gate connections 172, 174, 177 and 178 by the four gate landing pads 162, 164, 167 and 168, respectively. In the case of FIG. 6, the four gate landing pads 162, 164, 167, and 168 are spaced apart from each other at regular intervals, but the embodiment is not limited to this.

In addition, the drain pad 122A of FIG. 4 does not have a groove, whereas the drain pad 122C of FIG. 6 may have two grooves 125 and 127. Here, the grooves 125, 127 contribute to forming a space for the gate landing pads 167, 168.

Other parts of the power semiconductor device 100C illustrated in FIG. 6 are the same as those of the power semiconductor device 100A illustrated in FIG. 4, and thus a detailed description thereof will be omitted.

The embodiments illustrated in Figs. 4 to 6 described above are cases where N is 2, 3 or 4, respectively. However, it goes without saying that the present invention can be easily applied even when N is 5 or more at the level of those skilled in the art.

In the case of the conventional power semiconductor device shown in Fig. 1, one gate feeding point 50 is arranged for one gate finger 34 and one gate feeding point 52 is provided for one gate finger 36 do. On the other hand, in the case of the power semiconductor device 100A illustrated in FIG. 4, two gate feeding points 150 and 152 are provided per one gate finger 134 (N = 2) Three gate feeding points 150, 152 and 154 per gate finger 134 are provided for the device 100B and one gate finger 134 for the power semiconductor device 100C illustrated in FIG. Four gate feeding points (150, 152, 156, 158) per one are provided. Thus, according to the embodiment, since a plurality of gate feeding points 150, 152, 154, 156, and 158 are disposed per one gate finger 134, the gate widths W _g , W _g1 , W _g2 , W _g3 ), The gate resistance R _g can be lowered. The gate resistance (R _g ) and N have the following relationship (1).

Here, R _ref represents a resistance value of the gates 35 and 37 (hereinafter referred to as "reference resistance value ") when N = 1.

Referring to Equation 1, when N = 2, the resistance value R _g of the gate 136 illustrated in FIG. 4 is 1/4 of the reference resistance value R _ref . When N = 3, The resistance value R _g of the gates 134-1 and 134-2 illustrated in Fig. 6A becomes 1/16 of the reference resistance value R _ref , and when N = 4, the gate 134-1 , the resistance value (R _g) of 134-2, 134-3) is the 1/36 of the reference resistance (R _ref). As described above, the resistance value R _g of the gates 136, 134-1, 134-2, and 134-3 becomes lower than the reference resistance value R _ref as N increases.

Fig. 7 is a graph showing the relationship of the gate resistance value (R _g ) to the gate width (W _g ).

Referring to FIG. 7, as the gate width W _g increases, the rate of increase of the gate resistance value R _g decreases to 302 when N = 2 as compared with the reference resistance value R _ref 300 (304) than when N = 2 (302) and N = 3 (304).

Generally, when the power semiconductor device is a HEMT, the maximum resonant frequency (f _max ) and the resistance value (R _g ) of the gate have the relationship expressed by the following equation (2).

Where f _T has a unit of GHz as a cut-off frequency, G _ds has a unit of mS as a drain conductance or an output conductance, R _s denotes a source resistance value, and R _i denotes an intrinsic ) Denotes a resistance value, g _{m , int} denotes a specific transconductance, C _gs denotes a gate-to-source capacitance, and C _gd denotes a gate and drain capacitance. R _g , R _s , and R _i each have units of ohms (Ω), and C _gs and C _gd each have units of pF.

Equation (2) may be approximated as Equation (3).

In the above-described expressions (2) and (3), it can be seen that the resistance value (R _g ) of the gate and the maximum resonance frequency (f _max ) are in inverse proportion. Therefore, if the gate width W _g is increased to increase the amount of current, the gate resistance value R _g increases and the maximum resonant frequency f _max decreases.

However, according to the embodiment, since the N gate feeding points 150, 152, 154, 156 and 158 are provided per one gate finger 134, the gate resistance value R _g is obtained as shown in the above- . Therefore, the maximum resonant frequency f _max can be increased by decreasing the gate resistance value R _g as shown in the above-mentioned expressions (2) and (3). That is, in order to increase the amount of current in the power semiconductor devices 100A, 100B, and 100C according to the embodiment, the maximum resonant frequency f _max can be increased even though the gate width W _g is increased. Therefore, in the case of the power semiconductor devices 100A to 100C according to the embodiments, high power characteristics and high frequency characteristics can be satisfied together, and the phase difference can be compensated.

Meanwhile, the gate connection portions 172, 174, 176, 177, and 178 may have various shapes.

FIGS. 8A and 8B are partial cross-sectional views taken along line 7-7 'of the power semiconductor devices 100A to 100C illustrated in FIGS. Here, reference numerals 116, 124, and 134 correspond to the sources 116 and 116-1, the drains 124 and 124-1, and the gates 136 and 134-1 illustrated in FIGS. 4 and 6, respectively. Also, each of reference numerals 172A and 172B corresponds to the gate connection portion 172 illustrated in Figs.

8A, the gate connection 172A electrically connects the gate feeding point 150, 152, 154, 156, 158 of the gate pad 132 and the gate landing pad 162 in the form of an air bridge You can connect.

8B, the gate connecting portion 172A may electrically connect the gate feeding pad 150 and the gate landing pad 162 of the gate pad 132 using an insulator rather than an air bridge method. In this case, the power semiconductor device further includes an insulating layer 250. An insulating layer 250 is disposed over the barrier layer 240 covering the gate pad 132, the source 116, the drain 124 and the gate landing pad 162. The insulating layer 250 has a through hole 252 exposing the upper surface of the gate pad 132 and a through hole 254 exposing the upper surface of the gate landing pad 162. The gate connecting portion 172B is disposed on the insulating layer 250 while filling the through holes 252 and 254 to electrically connect the exposed top surface of the gate pad 132 and the exposed top surface of the gate landing pad 162 Connect.

The power semiconductor device illustrated in FIGS. 8A and 8B further includes a substrate 210, a transition layer 220, a buffer layer 230, and a barrier layer 240.

The substrate 210 may be a silicon substrate, a silicon carbide substrate, a GaN substrate, or a sapphire substrate, but the embodiment is not limited to the type of the substrate 210.

The buffer layer 230 is disposed on the substrate 210. The buffer layer 230 may be an undoped semiconductor layer. The buffer layer 230 may be formed of a semiconductor compound. 3-group-5 or group-6-group compound semiconductors. For example, a semiconductor material having a composition formula of Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1, 0? _X + y? 1). The buffer layer 230 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP.

A channel layer 232 may be formed on top of the buffer layer 230 adjacent to the barrier layer 240. That is, the channel layer 232 is disposed on the buffer layer 230 below the interface between the barrier layer 240 and the buffer layer 230.

In addition, a transition layer 220 may be further disposed between the substrate 210 and the buffer layer 230. The transition layer 220 may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or the like, but the embodiment is not limited thereto and the transition layer 220 may be omitted.

The barrier layer 240 is disposed on the buffer layer 230. The barrier layer 240 is a layer disposed to assist in the formation of the channel layer 232, and serves to warp band gap energy. The barrier layer 240 may have a more uniform bandgap energy than the channel layer 232 and may have a uniform polarization density across the layer and may have a different band gap energy of the barrier layer 240 and the buffer layer 230. [ 2-Dimensional Electron Gas (2DEG) can be generated as the channel layer 232 by the heterojunction with the heterojunction.

For example, the barrier layer 240 may be implemented with compound semiconductors such as Group 3-Group 5 or Group 2-Group 6. For example, a semiconductor material having a composition formula of Al _x In _y Ga _(1-xy) N (0? X? 1, 0? _Y? 1, 0? _X + y? 1). The barrier layer 240 may be formed of one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP.

The substrate 210, the intermediate layer 220, the buffer layer 230, and the barrier layer 240 illustrated in FIGS. 8A and 8B are only one example of constituting a power semiconductor device, , 220, 230, 240).

On the other hand, in the power semiconductor devices 100A, 100B and 100C of the embodiment illustrated in Figs. 4 to 6, the sources 116 and 116-1 to 116-3 and the gate landing pads 162, 164, 166, 167 and 168, The parasitic capacitance between the source 116, 116-1 to 116-3 and the gate landing pad 162, 164, 166, 167, 168 can be increased.

In order to prevent this, the gate landing pads 162, 164, 166, 167, and 168 in the power semiconductor device according to the embodiment have inclined outlines, and sloped outer edges and sources 116 and 116-1 to 116-3, May be increased as the distance from the source 116, 116-1 to 116-3 is increased.

The spacing between the drain pads 122A, 122B and 122C and the gate landing pads 162, 164, 166, 167 and 168 in the power semiconductor devices 100A, 100B and 100C of the embodiment illustrated in Figs. The parasitic capacitance caused between the drain pads 122A, 122B and 122C and the gate landing pads 162, 164, 166, 167 and 168 can be increased.

The drain pads 122A, 122B and 122C adjacent to the gate landing pads 162, 164, 166, 167 and 168 also have active areas 140, 142, 144 and 146 illustrated in FIGS. May be defined as the drains 124, 124-1, 124-2, and 124-3. In this case, the drains 124, 124-1 to 124-3 and the gate landing pads 162, 164, 166, 167, 168 in the power semiconductor devices 100A, 100B, 100C of the embodiment illustrated in Figs. The parasitic capacitance caused between the drains 124, 124-1 to 124-3 and the gate landing pads 162, 164, 166, 167, 168 may be large.

In order to prevent this, the gate landing pads 162, 164, 166, 167, 168 have inclined outlines and sloping outer pads and drain pads 122A, 122B, 122C (or drains 124, 1 to 124-3 may face each other and the second distance may increase as the distance from the drain pads 122A, 122B and 122C (or the drains 124 and 124-1 to 124-3) increases.

FIG. 9 is a plan view showing an enlarged view of the portion 'A' in FIG.

In general, the capacitance of the capacitor has a relationship represented by the following equation (4).

Here, S represents the area of the two conductive plates constituting the capacitor, d represents the distance between the two conductive plates, and? Represents the dielectric constant of the material filled between the two conductive plates.

Referring to FIG. 9 and Equation (4), when the outer shape of the gate landing pad 162 is a rectangle 162E as illustrated in FIGS. 4 to 6, the outer edge of the gate landing pad 162 The distance D2, D4, and D6 between the outlines 116A and 116B of the source 116 may be small and the parasitic capacitance between the source 116 and the gate landing pad 162 may increase.

However, according to the embodiment, the planar shape of the outer periphery of the gate landing pad 162 is inclined. That is, the first distances D1, D3, and D5 where the sloping outer edges 162A, 162B, and 162C of the gate landing pad 162 and the sources 116A and 116B are spaced apart from each other are distant from the sources 116A and 116B The better. Thus, the parasitic capacitance between the source 116 and the gate landing pad 162 can be reduced.

Similarly, when the planar shape of the outer edge of the gate landing pad 162 is a quadrangle 162E as illustrated in FIGS. 4 to 6, a gap between the outer edge 162D of the gate landing pad 162 and the drain pad 122A The parasitic capacitance between the drain pad 122A and the gate landing pad 162 can be increased.

However, if the planar shape of the outer edge of the gate landing pad 162 is inclined according to the embodiment, a second distance D7 where the outer edge 162D of the gate landing pad 162 is spaced apart from the drain pad 122A And increases as the distance from the drain pad 122A increases. Therefore, the parasitic capacitance between the drain pad 122A and the gate landing pad 162 can be reduced.

In order to reduce the parasitic capacitance as described above, the outline of the gate landing pad 162 has an inclined shape. Considering this, the gate landing pads 166, 167, 168 located in the middle of the gate fingers 134 of the gate landing pads 162, 164, 166, 167, 168 illustrated in FIGS. And the gate landing pads 162, 164, 166, 167, 168 may have inclined outlines in various forms.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

100A, 100B, 100C: power semiconductor element 112, 114: source pad
116, 116-1, 116-2, 116-3: sources 122A, 122B, 122C: drain pads
124, 124-1, 124-2, 124-3: drain 132: gate pad
134: gate finger 134-1 to 134-2, 136: gate
140, 142, 144, 146: active region
150, 152, 154, 156, 158: gate feeding point
162, 164, 166, 167, 168: gate landing pads
172, 172A, 172B, 174, 176, 177, 178:
210: substrate 220: transition layer
230: buffer layer 232: channel layer
240: barrier layer 250: insulating layer

Claims (8)

Board;
A source and a drain spaced apart from each other on the substrate;
A gate finger disposed between the source and the drain;
A gate pad spaced apart from the gate finger by the source and having N gate coupling points connected to the gate voltage, wherein N is a positive integer greater than or equal to 2;
N gate connections electrically connecting the N gate feeding points to the gate finger; And
And N gate landing pads electrically connecting the N gate connections to the gate fingers. The power semiconductor device of claim 1, wherein the N gate landing pads are spaced apart from one another by a predetermined distance. 2. The apparatus of claim 1, wherein the N gate connections
And N wires electrically connecting the N gate feeding points and the gate landing pad in an air bridge manner. The semiconductor device of claim 1, further comprising an insulating layer disposed over the gate pad, the source, the drain, and the gate landing pad, the insulating layer having a through hole exposing an upper surface of the gate pad and an upper surface of the gate landing pad and,
Wherein the N gate connections are buried in the through holes to electrically connect the exposed upper surface of the gate pad to the exposed upper surface of the gate landing pad. 2. The power semiconductor device of claim 1, wherein the gate landing pads have a sloped outer surface, wherein a first distance that the outer perimeter and the source are spaced apart from each other is increased away from the source. 2. The power semiconductor device of claim 1, wherein the gate landing pad has a sloped outer surface, the second distance of which is opposite to the drain and is spaced away from the drain. The power semiconductor device according to claim 5 or 6, wherein the outer edge of the gate landing pad has a rhombic shape. The power semiconductor device according to claim 1, wherein N is determined according to a resistance value of the gate as follows.

(Where R _g represents the resistance value of the gate and R _ref represents the resistance value of the gate when N = 1).

Images