KR20130137773A - Semiconductor device - Google Patents

Abstract

The semiconductor of an embodiment includes a substrate, a buffer layer on the substrate, and a transfer layer with at least one AlN/AlxGa1-xN (0 < x < 1) superlattice unit layer while capable of improving the mobility of electrons with cracks eliminated, effectively fusing pits, improving surface morphology and crystallizability.

Description

Semiconductor device

Embodiments relate to semiconductor devices.

III-V compound semiconductors such as GaN are widely used in optoelectronics due to their many advantages such as wide and easy-to-adjust bandgap energy. Such GaN is usually grown on a sapphire substrate or a silicon carbide (SiC) substrate. Such a substrate is not suitable for a large diameter, and in particular, a SiC substrate is expensive.

Fig. 1 is a view showing a general semiconductor device, which is composed of a silicon substrate 5 and a GaN layer 7. Fig.

In order to solve the above-mentioned problems, a silicon substrate 5 which is cheaper than a sapphire substrate or a silicon carbide substrate, has a large diameter, and has excellent thermal conductivity, is used. However, when the GaN layer 7 is disposed on the silicon substrate 5, the lattice mismatch between GaN and silicon is very large and the thermal expansion coefficient difference between them is also very large, thereby deteriorating crystallinity. Various problems arise, such as melt-back, cracks, pit, surface morphology defects, and the like.

For example, cracks may be caused by a tensile strain occurring during cooling of the GaN layer 7 grown at a high temperature. Further, when forming a buffer layer (not shown) such as AlN on the silicon substrate 5, pits may occur due to the growth temperature of AlN, large lattice mismatch between silicon and AlN, and the like.

For the reasons stated above, there is a demand for a semiconductor device having a structure capable of providing good characteristics that does not cause such problems even if the silicon substrate 5 is used.

The embodiment provides a semiconductor device capable of eliminating the occurrence of cracks and / or pits and having good surface morphology and excellent crystallinity.

The semiconductor device of the embodiment includes a substrate; A buffer layer disposed on the substrate; And a transition layer having at least one AlN / Al _x Ga _1-x N (0 <x <1) superlattice unit layer disposed on the buffer layer. The substrate may be a silicon substrate having a (111) crystal plane as a main surface.

The transition layer includes a plurality of AlN / Al _x Ga _1-x N superlattice unit layers, and the transition layer has a concentration gradient of Al and Ga depending on the distance from the buffer layer. In the plurality of AlN / Al _x Ga _{1 - x} N superlattice unit layers, the x value gradually decreases as the distance from the buffer layer increases.

The transition layer is a first AlN / Al _x Ga _{1 - x} N superlattice unit layer of 0.7 <x <1; A second AlN / Al _x Ga _{1 - x} N superlattice unit layer with 0.5 <x ≦ 0.7; A third AlN / Al _x Ga _{1 - x} N superlattice unit layer, wherein 0.3 <x ≦ 0.5; And a fourth AlN / Al _x Ga _1-x N superlattice unit layer having 0 <x ≦ 0.3, wherein the first to fourth superlattice unit layers are sequentially stacked from the buffer layer.

The plurality of AlN / Al _x Ga _1-x N superlattice unit layers each have a different or the same thickness.

In addition, the transition layer includes a plurality of superlattice unit layer groups disposed on the buffer layer, and each of the plurality of superlattice unit layer groups has at least one AlN / Al _x Ga _1-x N superlattice having the same composition. The unit layer may include a structure in which the unit layers are continuously repeated, and the plurality of superlattice unit layer groups have different x values. In the superlattice unit layer group, the number of repetitions may gradually decrease as the distance from the buffer layer increases. For example, the number of repetitions may be 5 to 15.

The transition layer may include a first superlattice unit layer group including an AlN / Al _x Ga _1-x N superlattice unit layer having 0.7 <x <1; A second superlattice unit layer group comprising an AlN / Al _x Ga _1-x N superlattice unit layer having 0.5 <x ≦ 0.7; A third superlattice unit layer group comprising an AlN / Al _x Ga _1-x N superlattice unit layer having 0.3 <x ≦ 0.5; And a fourth superlattice unit layer group including an AlN / Al _x Ga _1-x N superlattice unit layer having 0 <x ≦ 0.3, wherein the first to fourth superlattice unit layer groups are sequentially formed from the buffer layer. Are stacked.

The buffer layer includes at least one of an AlN layer, an AlAs layer, and a SiC layer.

The buffer layer is made of an AlN layer, and the AlN layer of the buffer layer and the AlN superlattice layer constituting the AlN / Al _x Ga _1-x N superlattice unit layer have different content ratios between Al and N.

The semiconductor device may further include a device layer disposed on the transition layer. The device layer may include a III-V compound semiconductor.

For example, the device layer includes a light emitting structure, and the light emitting structure is

A first conductivity type semiconductor layer disposed on the transition layer; An active layer disposed on the first conductivity type semiconductor layer; And a second conductivity type semiconductor layer disposed on the active layer.

The AlN / Al _x Ga _1-x N seconds, the thickness of the AlN super lattice layer in the grid unit layer is 2 ㎚ to 5 ㎚, the AlN / Al _x Ga _1-x N second Al _x Ga _1-x in the lattice unit layer The thickness of the N superlattice layer can be 3 nm to 10 nm.

Embodiment of the semiconductor element is a silicon substrate and the AlN between GaN and Ⅲ-Ⅴ compound semiconductor layer, such as / Al _x Ga _{1 - x} N second place the grating unit layer, AlN / Al _x down to the GaN device layers from the silicon substrate A plurality of AlN / Al _x Ga _{1 - x} N superlattice unit layers having a concentration gradient of aluminum (Al) and gallium (Ga) in the Ga _{1 - x} N superlattice unit layer or having the same composition are successively stacked a plurality of times However, by varying the number of laminations for each group of superlattice unit layers, the lattice constant is induced to be slowly transferred by the transition layer. Accordingly, the compressive stress applied to the GaN device layer may be gradually increased to effectively compensate for the tensile stress, thereby eliminating the possibility of cracking and increasing electron mobility. It also effectively merges pit caused in AlN buffer layer disposed on silicon substrate, improves GaN surface morphology due to offset of crystal lattice mismatch, and dislocation It can be reduced by bending to improve the crystallinity in the path from the buffer layer to the device layer, to secure a flat surface morphology, group III-V compounds such as silicon substrates and GaN Since the AlN / Al _x Ga _{1 - x} N superlattice unit layer is disposed between the semiconductor layers, it is possible to easily and accurately control the Al content ratio.

1 is a view showing a general semiconductor device.
2 is a cross-sectional view of a semiconductor device according to an exemplary embodiment.
3 is a cross-sectional view of a semiconductor device according to another embodiment.
4 is a cross-sectional view of a semiconductor device according to an embodiment in which a light emitting device is implemented using the semiconductor device illustrated in FIGS. 2 and 3.
5A through 5E are diagrams for describing a method of manufacturing a semiconductor device according to the exemplary embodiment illustrated in FIG. 2.
6 is a cross-sectional view of a semiconductor device according to an embodiment in which an HEMT is implemented using the semiconductor devices illustrated in FIGS. 2 and 3.
7 is a cross-sectional view of a light emitting device package according to the embodiment.
8 is a perspective view of a lighting unit according to an embodiment.
9 is an exploded perspective view of a backlight unit according to an embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate understanding of the present invention. However, the embodiments according to the present invention can be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the invention are provided to more fully describe the present invention to those skilled in the art.

In the description of the embodiment according to the present invention, when described as being formed at the "on" or "under" of each element, the upper (up) or the lower (down) (on or under) includes both the two elements are in direct contact with each other (directly) or one or more other elements are formed indirectly formed between the two (element). In addition, when expressed as “on” or “under,” it may include the meaning of the downward direction as well as the upward direction based on one element.

The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. In addition, the size of each component does not necessarily reflect the actual size.

Fig. 2 shows a cross-sectional view of the semiconductor device 100A according to one embodiment.

The semiconductor device 100A illustrated in FIG. 2 includes a substrate 10, a buffer layer 20, a transition layer 30, and a device layer 40.

The substrate 10 may be a silicon substrate having a (111) crystal plane as a principal plane.

The buffer layer 20 is disposed on the substrate 10 and may include at least one of an AlN layer, an AlAs layer, and a SiC layer. When the buffer layer 20 has a threshold thickness or more, diffusion of silicon atoms from the silicon substrate 10 may be prevented and thus meltback may be prevented. Here, the critical thickness means a thickness at which silicon atoms from the silicon substrate 10 can be diffused. To this end, the buffer layer 20 may have a thickness of tens or hundreds of nanometers, for example, may have a thickness of less than 300 nm and greater than 10 nm.

The transition layer 30 is disposed on the buffer layer 20 and has at least one AlN / Al _x Ga _1-x N superlattice unit layer. Here, the AlN / Al _x Ga _{1 -x} N superlattice unit layer may be a bi-layer structure composed of an AlN superlattice layer and an Al _x Ga _{1 -x} N superlattice layer. Where 0 <x <1. In the AlN / Al _x Ga ₁ -xN superlattice unit layer, the relative positions of the AlN superlattice layer and the Al _x Ga _{1 -x} N superlattice layer are not limited. For example, AlN superlattice layer member teomcheung (bottom layer) and Al _x Ga _{1 - x} N may be a super lattice layer is a tapcheung (top layer) layered on the AlN layer superlattice. Alternatively, in the AlN / Al _x Ga _{1 - x} N superlattice unit layer, the Al _x Ga _{1 - x} N superlattice layer is a bottom layer and the AlN superlattice layer is stacked on the Al _x Ga _1-x N superlattice layer. It may be a top layer.

In addition, in the AlN / Al _x Ga _1-x N superlattice unit layer, the content ratio of Al and N in the AlN superlattice layer may be the same as or different from the content ratio of Al and N in the AlN layer constituting the buffer layer 20. It may be.

In addition, the transition layer 30 may include a plurality of AlN / Al _x Ga _1-x N superlattice unit layers 32 to 38. At this time, the transition layer 30 has a concentration gradient of Al and Ga according to the distance from the buffer layer 20. For example, the plurality of AlN / Al _x Ga _{1 - x} N superlattice unit layers 32 to 38 may have a smaller x value as the distance from the buffer layer 20 increases.

In FIG. 2, when the transition layer 30 includes first to fourth AlN / Al _x Ga _1-x N superlattice unit layers 32 to 38 that are sequentially stacked from the buffer layer 20, the first AlN. The x value in the / Al _x Ga _1-x N superlattice unit layer 32 is 0.7 <x <1 and the x value in the second AlN / Al _x Ga _1-x N superlattice unit layer 34 is 0.5 <x <0.7, x value in the third AlN / Al _x Ga _1-x N superlattice unit layer 36 is 0.3 <x <0.5, and the fourth AlN / Al _x Ga _1-x N superlattice The x value in the unit layer 38 may be 0 <x ≦ 0.3.

In addition, the plurality of AlN / Al _x Ga _1-x N superlattice unit layers 32 to 38 may have different thicknesses or the same thickness.

3 is a sectional view of a semiconductor device 100B according to another embodiment.

According to another embodiment illustrated in FIG. 3, the transition layer 30 may include a plurality of superlattice unit layer groups 30A to 30D formed on the buffer layer 20. At least one group of the plurality of superlattice unit layer groups 30A to 30D may have a structure in which at least one AlN / Al _x Ga _1-x N superlattice unit layer having the same composition is continuously repeated a predetermined number of times. . For example, the predetermined number may be 5 to 15. In addition, the plurality of superlattice unit layer groups 30A to 30D may have different x values.

Also, in the superlattice unit layer groups 30A to 30D, as the distance from the buffer layer 20 increases, the predetermined number may gradually decrease. That is, the first predetermined number of times the AlN / Al _x Ga _{1 - x} N superlattice unit layer is repeated in the superlattice unit layer group having a small distance from the buffer layer 20 is a superlattice unit having a large distance from the buffer layer 20. The AlN / Al _x Ga _{1 - x} N superlattice unit layer in the layer group may be greater than a second predetermined number of times.

As illustrated in FIG. 3, when the transition layer 30 includes the first to fourth superlattice unit layer groups 30A, 30B, 30C, and 30D sequentially stacked from the buffer layer 20, the first candle may be used. The lattice unit layer group 30A includes an AlN / Al _x Ga _{1 - x} N superlattice unit layer 31 with 0.7 <x <1, and the second superlattice unit layer group 30B has a 0.5 <x <0.7 AlN / Al _x Ga _1-x N superlattice unit layer 33, and the third superlattice unit layer group 30C is AlN / Al _x Ga _{1 - x} N superlattice unit having 0.3 <x ≤ 0.5 The fourth superlattice unit layer group 30D including the layer 35 may include an AlN / Al _x Ga _1-x N superlattice unit layer 37 having 0 <x ≦ 0.3.

In the AlN / Al _x Ga _{1 - x} N superlattice unit layer constituting the transition layer 30 illustrated in FIG. 2 or 3, the thickness of the AlN superlattice layer and the thickness of the Al _x Ga _{1 - x} N superlattice layer are appropriate. If out of the range, the compensating force of the compressive strain that compensates for the tensile strain may be weakened. To prevent this, in each of the AlN / Al _x Ga _1-x N superlattice unit layers constituting the transition layer 30, the thickness of the AlN superlattice layer may be 2 nm to 5 nm, and Al _x Ga _{1 - x} The thickness of the N superlattice layer can be 3 nm to 10 nm.

As illustrated in FIGS. 2 and 3, the semiconductor devices 100A and 100B according to the embodiment may further include an element layer 40 disposed on the transition layer 30. For example, the device layer 40 may include a III-V compound semiconductor, and may include various types of compound semiconductor layers depending on the field in which the semiconductor device is used.

4 is a cross-sectional view of a semiconductor device 100C according to an embodiment in which a light emitting device is implemented using the semiconductor devices 100A and 100B illustrated in FIGS. 2 and 3. Hereinafter, the same reference numerals as in FIGS. 2 and 3 denote the same elements, and detailed descriptions thereof will be omitted to avoid redundant description.

Referring to FIG. 4, the semiconductor device 100C includes a substrate 10, a buffer layer 20, a transition layer 30, and a device layer 40A. The element layer 40A is an element corresponding to the element layer 40 illustrated in FIG. 2 or 3. However, the element layer 40A includes a light emitting structure.

The light emitting structure of the element layer 40A includes a first conductive semiconductor layer 42 disposed on the transition layer 30, an active layer 44 disposed on the first conductive semiconductor layer 42, and an active layer 44 And a second conductive semiconductor layer 46 disposed on the second conductive semiconductor layer.

The first conductivity type semiconductor layer 42 may include a III-V compound semiconductor doped with the first conductive type dopant, and Al _y In _z Ga _(1-yz) N (0? Y? 1, z? 1, 0? y + z? 1). For example, the first conductive semiconductor layer 42 may be formed of at least one selected from the group consisting of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP . When the first conductivity type semiconductor layer 42 is an n-type semiconductor layer, the first conductivity type dopant may include Si, Ge, Sn, Se or Te as an n-type dopant, but is not limited thereto.

The active layer 44 is formed so that electrons (or holes) injected through the first conductivity type semiconductor layer 42 and holes (or electrons) injected through the second conductivity type semiconductor layer 46 meet with each other, Emitting layer 44 is a layer that emits light having energy determined by the energy band inherent to the material.

The active layer 44 may be formed of at least one of a single well structure, a multiple well structure, a single quantum well structure, a multi quantum well (MQW) structure, a quantum-wire structure or a quantum dot structure . For example, the active layer 44 is formed by injecting trimethyl gallium (TMG) gas, ammonia (NH ₃ ) gas, nitrogen gas (N ₂ ), and trimethyl indium (TMIn) But is not limited thereto.

The well layer / barrier layer of the active layer 44 may have any one or more pairs of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs and GaP But is not limited thereto. The well layer may be formed of a material having a band gap smaller than the band gap of the barrier layer.

The second conductive semiconductor layer 46 may include a III-V compound semiconductor doped with a second conductive dopant, and In _y Al _z Ga _1-yz N (0 ≦ y ≦ 1, 0 ≦ z ≦ And 1, 0 ≦ y + z ≦ 1). For example, when the second conductivity type semiconductor layer 46 is a p-type semiconductor layer, the second conductivity type dopant may be a p-type dopant including but not limited to Mg, Zn, Ca, Sr, or Ba. Do not.

In the above-described light emitting structure, the first conductivity type semiconductor layer 42 is formed of an n-type semiconductor layer and the second conductivity type semiconductor layer 46 is formed of a p-type semiconductor layer. However, the first conductivity type semiconductor layer 42 may be a p-type semiconductor layer, and the second conductivity type semiconductor layer 46 may be an n-type semiconductor layer. That is, the light emitting structure may be implemented as any one of an n-p junction structure, a p-n junction structure, an n-p-n junction structure, and a p-n-p junction structure.

Although not shown, first and second electrodes (not shown) electrically connected to the first and second conductivity type semiconductor layers 42 and 46, respectively, may be disposed. As described above, the light emitting device may be completed using a metal material and / or an insulating material other than the semiconductor material in the semiconductor device 100C illustrated in FIG. 4. The process of completing the light emitting device using the above-described semiconductor device is a well-known technique, and thus a detailed description thereof will be omitted.

Hereinafter, a method for manufacturing the semiconductor device 100A illustrated in Fig. 2 will be described with reference to Figs. 5A to 5E. In this example, the substrate 10 is a silicon substrate, the buffer layer 20 includes an AlN layer, and the transition layer 30 includes the first to fourth AlN / Al _x Ga _1-x N superlattice unit layers 32, 34, 36, 38, and the device layer 40 illustrates the case of an undoped GaN (hereinafter referred to as uGaN) layer 40B. However, of course, the semiconductor device 100A illustrated in FIG. 2 is not limited to the method described in this example but may be manufactured by various other methods.

Referring to FIG. 5A, a silicon substrate 10 is prepared.

The silicon nitride 10 is formed on the surface of the silicon substrate 10 by exposing the silicon substrate 10 to trimethylaluminum (TMA) gas for 15 seconds in the absence of ammonia gas to deposit an ultra-aluminum film &Lt; / RTI &gt; In some cases, a step of removing the native oxide film on the silicon substrate 10 by rapid annealing the silicon substrate 10 to a temperature of, for example, about 900 캜 may be additionally performed. However, the silicon substrate 10 can be prepared in various forms without being limited thereto.

Thereafter, an AlN buffer layer 20 having a predetermined thickness is formed on the silicon substrate 10 at a temperature of about 900 ° C. using ammonia. At this time, when the thickness of the AlN buffer layer 20 is increased beyond the crystal thickness, the AlN island is changed from the three-dimensional growth mode to the two-dimensional growth mode by the fusion of AlN islands. Since the AlN island thus fused can completely cover the silicon substrate 10, diffusion of silicon atoms can be prevented. Alternatively, the AlN buffer layer 20 may be formed on the silicon substrate 10 by various methods instead of the above-described method.

Thereafter, as shown in FIG. 5B, a first AlN / Al _a Ga _1-a N superlattice unit layer 32 is formed on the AlN buffer layer 20.

Thereafter, as illustrated in FIG. 5C, a second AlN / Al _b Ga _1-b N superlattice unit layer 34 is formed on the first AlN / Al _a Ga _1-a N superlattice unit layer 32. 5D, the third AlN / Al _c Ga _1-c N superlattice unit layer 36 and the fourth AlN are disposed on the second AlN / Al _b Ga _1-b N superlattice unit layer 34. / Al _d Ga _1-d N superlattice unit layer 38 is formed sequentially.

As described above, the content ratio (x = a, b, c, d) of Al in the plurality of AlN / Al _x Ga _{1 - x} N superlattice unit layers 32, 34, 36, 38 is AlN buffer layer 20. The farther the distance from), the smaller it becomes. That is, the first AlN / Al _a Ga _{1 -} a to d are the following relation equation (1) at _d N superlattice unit layer (38), _{- a} N superlattice unit layer (32) to claim 4 AlN / Al _d Ga ₁ Has

As described above, as the distance from the AlN buffer layer 20 to the AlN / Al _x Ga _1-x N superlattice unit layer 32, 34, 36, 38 increases, the content ratio of Al decreases and the content ratio of Ga increases.

Subsequently, as shown in FIG. 5E, uGaN may be formed on the fourth AlN / Al _d Ga _{1 - d} N superlattice unit layer 38 as the device layer 40B.

For example, in the process described above with reference to FIGS. 5A-5E, Ga, Al, and N may be grown by Metal Organic Chemical Vapor Deposition (MOCVD). That is, a structure including Ga, Al, and N may be formed by MOCVD using a precursor material including TMG, TMA, and NH ₃ .

According to the above-described embodiment, the superlattice unit layer composed of the AlN superlattice layer and the Al _x Ga _{1 - x} N superlattice layer has a greater distance from the buffer layer 20, that is, the element layer 40 from the superlattice unit layer. The smaller the distance to) is, the smaller the content ratio (x) of Al in the Al _x Ga _{1 - x} N superlattice unit layer is. Alternatively, in the superlattice unit layer group, the longer the distance from the buffer layer 20, that is, the smaller the distance from the superlattice unit layer to the element layer 40 is, the AlN / Al _x Ga _1-x N seconds having the same composition. The number of repetitions in which the lattice unit layers are repeatedly stacked becomes smaller gradually. Accordingly, the transition layer 30 causes the lattice constant to be smoothly transferred from the layer close to the buffer layer 20 to the layer close to the device layer 40, thereby gradually increasing the compressive stress to the device layer 40 of GaN. It can be given. In addition, in the transition layer 30, each superlattice layer is grown to a thickness thinner than a critical thickness, for example, 3 nm to 10 nm, so that no misfit occurs at the interface between AlN and the superlattice layer. , More compressive stress can be effectively applied to the device layer 40 of GaN. Therefore, it is possible to effectively compensate for the tensile stress caused from the silicon substrate 10 due to the difference in thermal expansion coefficient, and to improve the crystallinity by eliminating the possibility of cracking. In addition, it is possible to effectively merge the pit caused in the AlN buffer layer and to reduce the threading dislocation (TD), thereby improving the surface morphology of the GaN device layer 40, and bending the dislocation. Since bending is reduced, a structure having improved crystallinity from the buffer layer 20 to the device layer 40 can be obtained.

In addition, in view of the fact that cracks serve as traps and carriers are easily trapped by the traps, the semiconductor device according to the embodiment can eliminate the possibility of cracking, so that the electron mobility You can also increase

2 or 3 may include a high electron mobility transistor (HEMT), a heterostructure field effect transistor (HFET), a double HFET (DHFET), and the like. Can be used for power devices.

Hereinafter, the HEMT 100D using the semiconductor device illustrated in FIG. 2 or FIG. 3 will be described with reference to the accompanying drawings as follows. Here, the same reference numerals as in FIG. 2 or FIG. 3 denote the same elements, and thus redundant descriptions thereof will be omitted.

6 is a cross-sectional view of a semiconductor device 100D according to an embodiment in which an HEMT is implemented using the semiconductor devices 100A and 100B illustrated in FIGS. 2 and 3.

Referring to FIG. 6, the semiconductor device 100D includes a substrate 10, a buffer layer 20, a transition layer 30, and a device layer 40C. The element layer 40C is an element corresponding to the element layer 40 illustrated in FIG. 2 or 3. However, the device layer 40C may include a channel layer 47, an undoped AlGaN (hereinafter referred to as uAlGaN) layer 48, an n-type or p-type GaN layer 49, a gate G, and a plurality of contacts. It consists of (S, D).

The channel layer 47 may be formed to include undoped GaN, and may be disposed on the transition layer 30. The uAgAN layer 48 is disposed on top of the channel layer 47 through the heterojunction 50. In addition, a gate electrode G, which may be embodied including a material such as gold (Au), is disposed over the uAgAN layer 48.

When the channel formed by the channel layer 47 is an n-type channel, an n-type GaN layer 49 is disposed on both sides of the uAlGaN layer 48 at the top of the channel layer 47. However, when the channel formed by the channel layer 47 is a p-type channel, a p-type GaN layer 49 is disposed on both sides of the uAlGaN layer 48 at the top of the channel layer 47. The GaN layer 49 is buried in the channel layer 47.

At least one contact (S, D) is disposed on both sides of the uAgAN layer 48 on the GaN layer 49. Here, the at least one contact may include a source contact S that may be implemented with Al and a drain contact D that may be implemented with Al. The source contact S is disposed on the GaN layer 49 disposed on the channel layer 47, and the drain contact D is disposed on the GaN layer 40 spaced apart from the source contact D. .

In addition, the semiconductor devices 100A and 100B illustrated in FIGS. 2 and 3 may include a photodetector, a gated bipolar junction transistor, a gated hot electron transistor, and a gate heterostructure bipolar. Gated heterostructure bipolar junction transistors, gas sensors, liquid sensors, pressure sensors, multi-function sensors such as pressure and temperature, power switching transistors It may be applied to various fields such as transistors, microwave transistors, or lighting devices.

Hereinafter, the configuration and operation of the light emitting device package including the light emitting device using the semiconductor device 100C described above will be described.

7 is a cross-sectional view of a light emitting device package 200 according to the embodiment.

The light emitting device package 200 according to the embodiment includes the package body 205, the first and second lead frames 213 and 214 provided on the package body 205, and the package body 205 A light emitting device 220 electrically connected to the first and second lead frames 213 and 214 and a molding member 240 surrounding the light emitting device 220.

The package body portion 205 may be formed of silicon, synthetic resin, or metal, and may be formed with an inclined surface around the light emitting device 220.

The first and second lead frames 213 and 214 are electrically separated from each other and serve to supply power to the light emitting device 220. The first and second lead frames 213 and 214 may function to increase light efficiency by reflecting the light generated from the light emitting device 220. The heat generated from the light emitting device 220 may be transmitted to the outside It may also serve as a discharge.

The light emitting device 220 may include the semiconductor device 100C illustrated in FIG. 4, but is not limited thereto.

As illustrated in FIG. 7, the light emitting device 220 may be disposed on the first or second lead frames 213 and 214 or may be disposed on the package body 205.

The light emitting device 220 may be electrically connected to the first and / or second lead frames 213 and 214 by a wire, a flip chip, or a die bonding method. The light emitting device 220 illustrated in FIG. 7 is electrically connected to the first lead frame 213 and the wire 230, and is directly connected to the second lead frame 214, but is not limited thereto.

The molding member 240 can surround and protect the light emitting device 220. In addition, the molding member 240 may include a phosphor to change the wavelength of light emitted from the light emitting device 220.

A plurality of light emitting device packages according to embodiments may be arranged on a substrate, and a light guide plate, a prism sheet, a diffusion sheet, a fluorescent sheet, or the like may be disposed on a path of light emitted from the light emitting device package. The light emitting device package, the substrate, and the optical member may function as a backlight unit or function as a lighting unit. For example, the lighting system may include a backlight unit, a lighting unit, a pointing device, a lamp, and a streetlight.

8 is a perspective view of a lighting unit 300 according to an embodiment. However, the lighting unit 300 of FIG. 8 is an example of a lighting system, but is not limited thereto.

The illumination unit 300 includes a case body 310, a connection terminal 320 installed in the case body 310 and supplied with power from an external power source, a light emitting module unit 330 installed in the case body 310, ).

The case body 310 is formed of a material having a good heat dissipation property, and may be formed of metal or resin.

The light emitting module unit 330 may include a substrate 332 and at least one light emitting device package 200 mounted on the substrate 332.

The substrate 332 may be a printed circuit pattern on an insulator and may be a printed circuit board (PCB), a metal core PCB, a flexible PCB, a ceramic PCB, or the like .

In addition, the substrate 332 may be formed of a material that efficiently reflects light, or may be formed of a color whose surface is efficiently reflected, for example, white, silver, or the like.

At least one light emitting device package 200 may be mounted on the substrate 332. Each of the light emitting device packages 200 may include at least one light emitting device 220, for example, a light emitting diode (LED). The light emitting diode may include a colored light emitting diode that emits red, green, blue, or white colored light, and a UV light emitting diode that emits ultraviolet (UV) light.

The light emitting module unit 330 may be arranged to have a combination of various light emitting device packages 200 to obtain colors and brightness. For example, a white light emitting diode, a red light emitting diode, and a green light emitting diode may be combined to secure high color rendering (CRI).

The connection terminal 320 may be electrically connected to the light emitting module unit 330 to supply power. In the embodiment, the connection terminal 320 is connected to the external power source by being inserted in a socket manner, but the present invention is not limited thereto. For example, the connection terminal 320 may be formed in a pin shape and inserted into an external power source, or may be connected to an external power source through wiring.

9 is an exploded perspective view of the backlight unit 400 according to the embodiment. However, the backlight unit 400 of FIG. 9 is an example of an illumination system, but is not limited thereto.

The backlight unit 400 includes a light guide plate 410, a reflective member 420 under the light guide plate 410, a bottom cover 430, a light emitting module unit 440 for providing light to the light guide plate 410 ). The bottom cover 430 houses the light guide plate 410, the reflection member 420, and the light emitting module unit 440.

The light guide plate 410 serves to diffuse light to make a surface light source. The light guide plate 410 is made of a transparent material, and may be made of, for example, acrylic resin such as PMMA (polymethyl methacrylate), polyethylene terephthalate (PET), polycarbonate (PC), cycloolefin copolymer (COC), and polyethylene naphthalate As shown in FIG.

The light emitting module unit 440 provides light to at least one side of the light guide plate 410, and ultimately acts as a light source of the display device in which the backlight unit is installed.

The light emitting module 440 may be in contact with the light guide plate 410, but is not limited thereto. Specifically, the light emitting module unit 440 includes a substrate 442 and a plurality of light emitting device packages 200 mounted on the substrate 442. The substrate 442 may be in contact with the light guide plate 410, but is not limited thereto.

The substrate 442 may be a PCB including a circuit pattern (not shown). However, the substrate 442 may include not only general PCB but also metal core PCB (MCPCB), flexible PCB, and the like, but the present invention is not limited thereto.

The plurality of light emitting device packages 200 may be mounted on the substrate 442 such that the light emitting surface on which the light is emitted is spaced apart from the light guiding plate 410 by a predetermined distance.

A reflective member 420 may be formed under the light guide plate 410. The reflective member 420 reflects the light incident on the lower surface of the light guide plate 410 so as to face upward, thereby improving the brightness of the backlight unit. The reflective member 420 may be formed of, for example, PET, PC, PVC resin or the like, but is not limited thereto.

The bottom cover 430 may house the light guide plate 410, the light emitting module 440, the reflective member 420, and the like. To this end, the bottom cover 430 may be formed in a box shape having an opened top surface, but the present invention is not limited thereto.

The bottom cover 430 may be formed of a metal or a resin, and may be manufactured using a process such as press molding or extrusion molding.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

5, 10: silicon substrate 20: buffer layer
30: transition layer 30A, 30B, 30C, 30D: superlattice unit layer group
31, 32, 33, 34, 35, 36, 37, 38: AlN / Al _x Ga _{1 - x} N superlattice unit layer
40, 40A, 40B: device layer 42: first conductive semiconductor layer
44: active layer 46: second conductive semiconductor layer
47: channel layer 48: undoped AlGaN layer
49: GaN layer 100A, 100B, 100C, 100D: semiconductor device
200: light emitting device package 205: package body portion
213, 214: lead frame 220: light emitting element
230: wire 240: molding member
300: illumination unit 310: case body
320: connection terminal 330, 440: light emitting module part
332, 442: substrate 400: backlight unit
410: light guide plate 420: reflective member
430: bottom cover 440: light emitting module part

Claims (10)

Board;
A buffer layer on the substrate; And
And a transition layer having at least one AlN / Al _x Ga _1-x N (0 <x <1) superlattice unit layer on the buffer layer. The semiconductor device according to claim 1, wherein the substrate is a silicon substrate having a (111) crystal plane as a principal plane. The method of claim 1, wherein the transition layer comprises a plurality of AlN / Al _x Ga _1-x N superlattice unit layer,
The transition layer has a concentration gradient of Al and Ga in accordance with the distance from the buffer layer. The semiconductor device of claim 3, wherein the plurality of AlN / Al _x Ga _1-x N superlattice unit layers become smaller in value as the distance from the buffer layer increases. The method of claim 4, wherein the transition layer
A first AlN / Al _x Ga _1-x N superlattice unit layer with 0.7 <x <1;
A second AlN / Al _x Ga _1-x N superlattice unit layer having 0.5 <x ≦ 0.7;
A third AlN / Al _x Ga _1-x N superlattice unit layer having 0.3 <x ≦ 0.5; And
A fourth AlN / Al _x Ga _1-x N superlattice unit layer, wherein 0 <x ≤ 0.3,
The first to fourth superlattice unit layers are sequentially stacked from the buffer layer. The method of claim 1 or 3, wherein the transition layer comprises a plurality of superlattice unit layer groups on the buffer layer,
Each of the plurality of superlattice unit layer groups includes a structure in which at least one AlN / Al _x Ga _1-x N superlattice unit layer having the same composition is continuously repeated.
The plurality of superlattice unit layer groups have different x values. The semiconductor device of claim 6, wherein the superlattice unit layer group is gradually smaller as the distance from the buffer layer increases. The method of claim 6, wherein the transition layer
A first superlattice unit layer group comprising an AlN / Al _x Ga _{1 - x} N superlattice unit layer having 0.7 <x <1;
A second superlattice unit layer group comprising an AlN / Al _x Ga _{1 - x} N superlattice unit layer, wherein 0.5 <x <0.7;
A third superlattice unit layer group comprising an AlN / Al _x Ga _{1 - x} N superlattice unit layer, wherein 0.3 <x ≦ 0.5; And
A fourth superlattice unit layer group comprising an AlN / Al _x Ga _{1 - x} N superlattice unit layer, wherein 0 <x ≤ 0.3,
The first to fourth superlattice unit layer groups are sequentially stacked from the buffer layer. The semiconductor device of claim 1, wherein the buffer layer comprises at least one of an AlN layer, an AlAs layer, and an SiC layer. 10. The AlN superlattice layer according to any one of claims 1 to 5 and 9, wherein the thickness of the AlN superlattice layer in the AlN / Al _x Ga _{1 - x} N superlattice unit layer is 2 nm to 5 nm, and Al _x Ga. _{1 - x} N superlattice layer has a thickness of 3 nm to 10 nm.

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