KR20130089561A - Power mixing circuit, and semiconductor memory device including the same - Google Patents

Abstract

PURPOSE: A power mixing circuit and a semiconductor memory device including the same are provided to prevent data transmission errors by stabilizing a voltage of an output node in a deep-power-down mode. CONSTITUTION: An input buffer (110) operates using a first power voltage and generates a first voltage signal by buffering an input signal. A power mixing control circuit (150) generates a power mixing control signal in response to a power-up signal and a deep-power-down mode signal. A power mixing unit (120) operates using an external power voltage and a second power voltage, performs power mixing for the first voltage signal in response to the power mixing control signal, and generates a second voltage signal. An output buffer (140) operates using the second power voltage and generates an output signal by buffering the second voltage signal.

Description

Power mixing circuit and semiconductor memory device including the same {POWER MIXING CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME}

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a power mixing circuit.

In the semiconductor memory device, an external power supply voltage, a power supply voltage used for an output driving circuit, and a power supply voltage used in internal circuit blocks other than the output driving circuit are used. The semiconductor memory device may include a power mixing circuit to prevent data transfer error between circuit blocks using different power supply voltages.

As the electronic industry develops, semiconductor memory devices used in electronic devices are required to have low power consumption. In particular, semiconductor memory devices used in mobile devices such as cell phones have a deep powerdown mode to reduce power consumption. The semiconductor memory devices included in the mobile device in the deep power down mode do not operate some circuits by turning off the internal power supply voltage.

In a semiconductor memory device having a power mixing circuit, a voltage of an output node may be unstable in a deep power down mode.

It is an object of the present invention to provide a power mixing circuit capable of maintaining an output node at a stable voltage level in deep power down mode.

Another object of the present invention is to provide a semiconductor memory device including the power mixing circuit.

In order to achieve the above object, a power mixing circuit according to one embodiment of the present invention includes an input buffer, a power mixing control circuit, a power mixing unit, and an output buffer.

The input buffer operates using the first power supply voltage, and buffers the input signal to generate the first voltage signal. The power mixing control circuit generates a power mixing control signal in response to the power up signal and the deep power down mode signal. The power mixing unit operates using an external power supply voltage and a second power supply voltage, performs power mixing on the first voltage signal in response to the power mixing control signal, and generates a second voltage signal. The output buffer operates using the second power supply voltage, and buffers the second voltage signal to generate an output signal.

According to one embodiment of the invention, the power mixing circuit can generate a stable output voltage even if the magnitude of the first power supply voltage changes.

According to one embodiment of the invention, the power mixing control circuit may operate using the external power supply voltage.

According to an embodiment of the present invention, the input buffer may invert the phase of the input signal to generate the first voltage signal, and the output buffer may invert the phase of the second voltage signal to output the output signal. May occur.

According to one embodiment of the present invention, the power mixing unit may include a first NOR circuit, a first inverter, a second NOR circuit, and a second inverter.

The first NOR circuit operates using the external power supply voltage, and performs a non-logical operation on the power mixing control signal and the first voltage signal. The first inverter operates using the second power supply voltage, and inverts the phase of the output signal of the first NOR circuit. The second NOR circuit operates using the second power supply voltage, and performs a non-logical sum operation on the power mixing control signal and the first voltage signal. The second inverter operates using the second power supply voltage, and inverts the phase of the output signal of the second NOR circuit.

According to an embodiment of the present invention, the power mixing unit may include a first NAND circuit, a first inverter, a second NAND circuit, and a second inverter.

The first NAND circuit operates using the external power supply voltage, and performs a non-logical operation on the power mixing control signal and the first voltage signal. The first inverter operates using the second power supply voltage, and inverts the phase of the output signal of the first NAND circuit. The second NAND circuit operates using the second power supply voltage, and performs a non-logical operation on the power mixing control signal and the first voltage signal. The second inverter operates using the second power supply voltage and inverts the phase of the output signal of the second NAND circuit.

According to an embodiment of the present invention, the power mixing control signal may be in a logic low state in the deep power down mode.

A semiconductor memory device according to an embodiment of the present invention includes a memory cell array, an address input buffer, a row decoder, a column decoder, an input / output sense amplifier, a power-up signal generating circuit that operate in response to a word line enable signal and a column select signal. And an output circuit.

The address input buffer generates a row address signal and a column address signal based on the external address. The row decoder decodes the row address signal to generate a wordline enable signal. The column decoder decodes the column address signal to generate the column select signal. The input / output sense amplifier amplifies data output from the memory cell array to generate first data, and transmits data input from the outside to the memory cell array. The power up signal generation circuit generates a power up signal based on the external power supply voltage. The output circuit performs power mixing on the output signal of the input / output sense amplifier based on a deep power down mode signal, the power up signal, and the external power supply voltage, and generates output data. The semiconductor memory device generates a power mixing control signal based on the deep power down mode signal and the power up signal in a deep power down mode, and outputs a stable output even when an internal power supply voltage changes in response to the power mixing control signal. Voltage can be generated.

According to an embodiment of the present invention, the output circuit may include an ordering circuit, a first multiplexer, a second multiplexer, and an output driving circuit.

An ordering circuit determines the output order for the first data. The first multiplexer selects an output bit structure and outputs second data in response to an output signal of the ordering circuit. The second multiplexer performs parallel-serial conversion on the second data to generate third data. The output driving circuit performs power mixing on the third data and generates output data.

According to an embodiment of the present invention, the semiconductor memory device may be a stacked memory device in which a plurality of chips that transmit and receive data and control signals through a through electrode (TSV: ThroughSiliconVia) are stacked.

The power mixing circuit according to the embodiments of the present invention generates a power mixing control signal in response to a power up signal and a deep power down mode signal, performs power mixing on an input signal in response to the power mixing control signal, and outputs the output signal. Generate a signal.

Thus, the power mixing circuit stabilizes the voltage at the output node in deep power down mode. In addition, the semiconductor memory device including the power mixing circuit is insensitive to noise and has little data transfer error.

1 is a circuit diagram illustrating a power mixing circuit according to one embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a power mixing control circuit included in the power mixing circuit of FIG. 1.
3 is a circuit diagram illustrating an example of a latch circuit included in the power mixing control circuit of FIG. 2.
4 is a timing diagram illustrating an operation of the power mixing circuit of FIG. 1 in a normal operation mode.
FIG. 5 is a timing diagram illustrating an operation of the power mixing circuit of FIG. 1 in deep power down. FIG.
6 is a circuit diagram illustrating a power mixing circuit according to another embodiment of the present invention.
FIG. 7 is a circuit diagram illustrating an example of a power mixing control circuit included in the power mixing circuit of FIG. 6.
8 is a block diagram illustrating an example of a semiconductor memory device including a power mixing circuit according to example embodiments of the inventive concepts.
9 is a block diagram illustrating an example of an output circuit included in the semiconductor memory device of FIG. 8.
10 is a diagram illustrating an example of a memory system including a semiconductor memory device according to an embodiment of the present invention.
11 is a simplified perspective view showing one of the laminated semiconductor devices including the semiconductor memory device according to the embodiment of the present invention.
12 is a block diagram illustrating another example of a memory system including a semiconductor memory device according to an embodiment of the present invention.
13 is a block diagram illustrating an example of an electronic system including a semiconductor memory device according to an embodiment of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, And should not be construed as limited to the embodiments described in the foregoing description.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprising ", or" having ", and the like, are intended to specify the presence of stated features, integers, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

On the other hand, if an embodiment is otherwise feasible, the functions or operations specified in a particular block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be performed at substantially the same time, and depending on the associated function or operation, the blocks may be performed backwards.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a circuit diagram illustrating a power mixing circuit 100 according to an embodiment of the present invention.

Referring to FIG. 1, the power mixing circuit 100 includes an input buffer 110, a power mixing unit 120, an output buffer 140, and a power mixing control circuit 150.

The input buffer 110 operates using the first power voltage VDD1 and receives the input signal DIN through the input node NIN. The input buffer 110 generates the first voltage signal V1 by buffering the input signal DIN and outputs the first voltage signal V1 to the first node N1. The power mixing control circuit 150 generates the power mixing control signal CON_PM in response to the power up signal VCCHB and the deep power down mode signal PDPD. The power mixing control circuit 150 may operate using an external power supply voltage VEXT.

 The power mixing unit 120 operates using the external power supply voltage VEXT and the second power supply voltage VDD2, and receives the first voltage signal V1 from the first node N1. The power mixing unit 120 performs power mixing on the first voltage signal V1 in response to the power mixing control signal CON_PM, generates a second voltage signal, and converts the second voltage signal to the second node N2. Output to. The output buffer 140 operates using the second power supply voltage VDD2, and receives the second voltage signal from the second node N2. The output buffer 140 buffers the second voltage signal to generate an output signal DOUT, and output the output signal DOUT to the output node NOUT.

The input buffer 110 may include a PMOS transistor MP1 and an NMOS transistor MN1. The PMOS transistor MP1 has a gate to which the input signal DIN is applied, and a source connected to the first power voltage VDD1. The NMOS transistor MN1 has a gate to which the input signal DIN is applied, a source connected to the ground VSS, and a drain connected to the drain of the PMOS transistor MP1.

The power mixing unit 120 may include a first NOR circuit 121, a first inverter 122, a second NOR circuit 123, and a second inverter 124.

The first NOR circuit 121 operates by using the external power supply voltage VEXT, and performs an NOR operation on the power mixing control signal CON_PM and the first voltage signal V1. The first inverter 122 operates using the second power supply voltage VDD2, and inverts the phase of the output voltage signal V2 of the first NOR circuit 121. The second NOR circuit 123 operates using the second power supply voltage VDD2, and performs a non-logical operation on the power mixing control signal CON_PM and the first voltage signal V1. The second inverter 124 operates using the second power supply voltage VDD2, and inverts the phase of the output voltage signal V4 of the second NOR circuit 123. The second voltage signal, which is a voltage signal of the second node N2, is a signal obtained by adding the output voltage signal V3 of the first inverter 122 and the output voltage signal V5 of the second inverter 124.

The first NOR circuit 121 operates in the deep power down mode because the first NOR circuit 121 operates using the external power supply voltage VEXT.

The output buffer 140 may include a PMOS transistor MP2 and an NMOS transistor MN2. The PMOS transistor MP2 has a gate to which the voltage signal of the second node N2 is applied, and a source connected to the second power supply voltage VDD2. The NMOS transistor MN2 has a gate to which the voltage signal of the second node N2 is applied, a source connected to the ground VSS, and a drain connected to the drain of the PMOS transistor MP2. The node connected to the drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN2 is the output node NOUT, and the output signal DOUT is output from the output node NOUT.

The power mixing circuit 100 of FIG. 1 may maintain the voltage of the output node NOUT at a stable constant value in response to the power mixing control signal CON_PM in a logic low state in the deep power down mode. In the example of FIG. 1, when the power mixing control signal CON_PM is in a logic high state, the power mixing unit 120 may output the output node regardless of the voltage level of the first voltage signal V1, which is the voltage of the first node N1. The voltage at (NOUT) can be held at logic low. Conventionally, when the first power supply voltage VDD1 is in the deep power down mode and the second power supply voltage VDD2 is in the on state, the voltages of the input terminal and the output terminal of the power mixing unit 120 are unstable. The power mixing circuit 100 according to the embodiment of the present invention shown in FIG. 1 is a power mixing control signal enabled in response to a power-up signal VCCHB or a deep power-down mode signal PDPD in a deep power-down mode. CON_PM) can be used to stabilize the output voltage of the power mixing circuit 100.

FIG. 2 is a circuit diagram illustrating an example of a power mixing control circuit 150 included in the power mixing circuit 100 of FIG. 1.

2, the power mixing control circuit 150 includes a NOR circuit 151, a first inverter 152, a first PMOS transistor MP4, a first NMOS transistor MN4, and a first latch circuit 157. The second latch circuit 153, the second inverter 154, the second PMOS transistor MP3, the second NMOS transistor MN3, the third inverter 155, and the OR circuit 156 may be included.

The NOR circuit 151 performs an NOR operation on the power up signal VCCHB and the deep power down mode signal PDPD. The first inverter 152 inverts the phase of the output signal of the NOR circuit 151. The first PMOS transistor MP4 has a gate connected to the output terminal of the NOR circuit 151, and a source connected to the external power supply voltage VEXT. The first NMOS transistor MN4 has a gate connected to the output terminal of the first inverter 152, and a source connected to the ground VSS. The first latch circuit 157 is connected to the drain of the first PMOS transistor MP4 and the drain of the first NMOS transistor MN4. The second latch circuit 153 latches the voltage of the drain of the first PMOS transistor MP4 and inverts the phase of the voltage of the drain. The second latch circuit 153 may include two inverters 158 and 159. The second inverter 154 inverts the phase of the output signal of the second latch circuit 153. The second PMOS transistor MP3 has a gate connected to the output terminal of the second inverter 154, and a source connected to the external power supply voltage VEXT. The second NMOS transistor MN3 has a drain connected to the drain of the second PMOS transistor MP3, a gate connected to the output terminal of the first inverter 152, and a source connected to the ground VSS. The third inverter 155 inverts the phase of the voltage of the drain of the second NMOS transistor MN3. The OR circuit 156 performs a logical sum operation on the output signal of the second latch circuit 153 and the output signal of the third inverter 155 and generates a power mixing control signal CON_PM.

3 is a circuit diagram illustrating an example of the first latch circuit 157 included in the power mixing control circuit 150 of FIG. 2.

Referring to FIG. 3, the first latch circuit 157 may include a first latch unit 161, a second latch unit 162, and a current supply unit 163.

The first latch unit 161 is connected to an external power supply voltage VEXT, a node N3 connected to the drain of the first PMOS transistor MP4, and a node N4 connected to the drain of the first NMOS transistor MN4. And two PMOS transistors MP5 and MP6 cross-coupled with a drain and a gate thereof. The second latch unit 162 includes two NMOS transistors MN5 and MN6 connected to the node N3 and the node N4, and having a drain and a gate connected to each other. The current supply unit 163 forms a current path between the first node N3 and the ground VSS and between the second node N4 and the ground VSS.

4 is a timing diagram illustrating an operation of the power mixing circuit 100 of FIG. 1 in a normal operation mode. 4 is a diagram illustrating an example of power mixing when the second power supply voltage VDD2 has a lower voltage level than the first power supply voltage VDD1. 4 illustrates an input signal DIN, a first voltage signal V1, an output voltage signal V2 of the first NOR circuit 121, an output voltage signal V3 of the first inverter 122, and a second NOR circuit. An output voltage signal V4 of 123 and an output voltage signal V5 of the second inverter 124 are shown. In FIG. 4, an inverted signal and a non-inverted signal are shown together for each signal, and the thick line represents the non-inverted signal and the thin line represents the inverted signal.

Referring to FIG. 1, V1 is an output voltage signal of an input buffer 110 operating using a first power supply voltage VDD1, and V2 is a first NOR circuit 121 operating using an external power supply voltage VEXT. ) Is an output voltage signal, and V3 is an output voltage signal of the first inverter 122 operating using the second power supply voltage VDD2. Since the first inverter 122 operates using the second power supply voltage VDD2 that is lower than the external power supply voltage VEXT, the time point when V3 falls from the high state to the low state is accelerated. Since the second NOR circuit 123 operates using the second power supply voltage VDD2 that is lower than the first power supply voltage VDD1, the time point at which V4 falls from the high state to the low state becomes faster, and from the low state to the high state. The falling point is late. Since the second inverter 124 operates using the same second power supply voltage VDD2 as the second NOR circuit 123, V5 becomes a signal in phase out of V4. The voltage signal of the second node N2, which is an output node of the power mixing unit 120, is a sum of V3 and V5. The output signal DOUT of the power mixing circuit 100 becomes a voltage signal having the same form as the input signal DIN.

FIG. 5 is a timing diagram illustrating an operation of the power mixing circuit 100 of FIG. 1 in a deep power down mode. 5 illustrates an external power supply voltage VEXT, a deep power down mode signal PDPD, a first power supply voltage VDD1, a second power supply voltage VDD2, a power-up signal VCCHB, and a power mixing control signal CON_PM. Is shown.

Referring to FIG. 5, in the deep power down mode, the deep power down mode signal PDPD and the power up signal VCCHB maintain a logic high state, and the first power voltage VDD1 is turned off and the second power voltage VDD2) is in the on state.

The semiconductor memory device used in a mobile system such as a mobile phone has a deep power down mode in which some circuits included in the semiconductor memory device are turned off in order to save power voltage. In the deep power down mode, the internal power supply voltage VINT supplied to the semiconductor memory device is turned off, and the driver power supply voltage VDDQ supplied to a portion of the output driver circuit is in an on state. The first power supply voltage VDD1 corresponds to an internal power supply voltage VINT, and the second power supply voltage VDD2 corresponds to a driver power supply voltage VDDQ.

6 is a circuit diagram illustrating a power mixing circuit 200 according to another embodiment of the present invention.

Referring to FIG. 6, the power mixing circuit 200 includes an input buffer 110, a power mixing unit 120a, an output buffer 140, and a power mixing control circuit 150a.

The input buffer 110 and the output buffer 140 may have the same configuration as the input buffer 110 and the output buffer 140 included in the power mixing circuit 200 shown in FIG. 1, respectively.

The power mixing control circuit 150a generates the inverted power mixing control signal CON_PM_B in response to the power-up signal VCCHB or the deep power-down mode signal PDPD. The inverted power mixing control signal CON_PM_B is a signal in phase opposite to the power mixing control signal CON_PM generated by the power mixing control circuit 150 in FIG. 1. The power mixing control circuit 150 may operate using an external power supply voltage VEXT.

The power mixing unit 120a may include a first NAND circuit 125, a first inverter 122, a second NAND circuit 126, and a second inverter 124.

The first NAND circuit 125 operates by using the external power supply voltage VEXT, and performs a non-logical (NAND) operation on the inverted power mixing control signal CON_PM_B and the first voltage signal V1. The first inverter 122 operates using the second power supply voltage VDD2, and inverts the phase of the output voltage signal V2 of the first NAND circuit 125. The second NAND circuit 126 operates using the second power supply voltage VDD2, and performs non-logical operation on the inverted power mixing control signal CON_PM_B and the first voltage signal V1. The second inverter 124 operates using the second power supply voltage VDD2, and inverts the phase of the output voltage signal V4 of the second NAND circuit 126. The second voltage signal, which is a voltage signal of the second node N2, is a signal obtained by adding the output voltage signal V3 of the first inverter 122 and the output voltage signal V5 of the second inverter 124.

Since the first NAND circuit 125 operates using the external power supply voltage VEXT, the first NAND circuit 125 is in an on state in the deep power down mode.

 The power mixing unit 120a operates using the external power supply voltage VEXT and the second power supply voltage VDD2, and receives the first voltage signal V1 from the first node N1. The power mixing unit 120a performs power mixing on the first voltage signal V1 in response to the power mixing control signal CON_PM, generates a second voltage signal, and converts the second voltage signal to the second node N2. Output to.

The power mixing circuit 200 of FIG. 6 may maintain the voltage of the output node NOUT at a stable constant value in response to the inversion power mixing control signal CON_PM_B in a logic low state in the deep power down mode. In the example of FIG. 6, when the inversion power mixing control signal CON_PM_B is in a logic low state, the power mixing unit 120a outputs the voltage regardless of the voltage level of the first voltage signal V1, which is the voltage of the first node N1. The voltage at the node NOUT can be maintained at a logic high state. Conventionally, when the first power supply voltage VDD1 is turned off and the second power supply voltage VDD2 is turned on in the deep power down mode, the voltages of the input terminal and the output terminal of the power mixing unit 120a are unstable. The power mixing circuit 200 according to the embodiment of the present invention shown in FIG. 6 is an inverted power mixing control signal enabled in response to the power-up signal VCCHB or the deep power-down mode signal PDPD in the deep power-down mode. By using CON_PM_B, the output voltage of the power mixing circuit 200 may be maintained at a constant value.

FIG. 7 is a circuit diagram illustrating an example of the power mixing control circuit 150a included in the power mixing circuit 200 of FIG. 6.

Referring to FIG. 7, the power mixing control circuit 150a may include a NOR circuit 151, a first inverter 152, a first PMOS transistor MP4, a first NMOS transistor MN4, and a first latch circuit 157. The second latch circuit 153, the second inverter 154, the second PMOS transistor MP3, the second NMOS transistor MN3, the third inverter 155, and the NOR circuit 165 may be included.

The NOR circuit 151 performs an NOR operation on the power up signal VCCHB and the deep power down mode signal PDPD. The first inverter 152 inverts the phase of the output signal of the NOR circuit 151. The first PMOS transistor MP4 has a gate connected to the output terminal of the NOR circuit 151, and a source connected to the external power supply voltage VEXT. The first NMOS transistor MN4 has a gate connected to the output terminal of the first inverter 152, and a source connected to the ground VSS. The first latch circuit 157 is connected to the drain of the first PMOS transistor MP4 and the drain of the first NMOS transistor MN4. The second latch circuit 153 latches the voltage of the drain of the first PMOS transistor MP4 and inverts the phase of the voltage of the drain. The second latch circuit 153 may include two inverters 158 and 159. The second inverter 154 inverts the phase of the output signal of the second latch circuit 153. The second PMOS transistor MP3 has a gate connected to the output terminal of the second inverter 154, and a source connected to the external power supply voltage VEXT. The second NMOS transistor MN3 has a drain connected to the drain of the second PMOS transistor MP3, a gate connected to the output terminal of the first inverter 152, and a source connected to the ground VSS. The third inverter 155 inverts the phase of the voltage of the drain of the second NMOS transistor MN3. The NOR circuit 165 performs an NOR operation on the output signal of the second latch circuit 153 and the output signal of the third inverter 155 and generates an inverted power mixing control signal CON_PM_B.

FIG. 8 is a block diagram illustrating an example of a semiconductor memory device 1000 including a power mixing circuit according to example embodiments.

Referring to FIG. 8, a semiconductor memory device may include a memory cell array 1500, an address input buffer 1100, a row decoder 1200 that operate in response to a word line enable signal WL and a column select signal CSL. A column decoder 1300, an input / output sense amplifier 1600, a power-up signal generation circuit 1400, and an output circuit 1700.

The address input buffer 1100 generates the row address signal ADDR_X and the column address signal ADDR_Y based on the external address ADDR. The row decoder 1200 decodes the row address signal ADDR_X to generate a word line enable signal WL. The column decoder 1300 decodes the column address signal ADDR_Y to generate the column select signal CSL. The input / output sense amplifier 1600 amplifies the data output from the memory cell array 1500 to generate first data SAO, and transmits data input from the outside to the memory cell array 1500. The power up signal generation circuit 1400 generates the power up signal VCCHB based on the external power supply voltage VEXT.

The output circuit 1700 may include an output driving circuit having a configuration of a power mixing circuit according to the embodiments of the present invention. Based on the deep power down mode signal PDPD, the power up signal VCCHB, and the external power supply voltage VEXT, power mixing is performed on the first data SAO, which is an output signal of the input / output sense amplifier 1600, and output data ( DOUT).

The semiconductor memory device 1000 generates a power mixing control signal CON_PM based on the deep power down mode signal PDPD and the power up signal VCCHB in the deep power down mode, and applies the power mixing control signal CON_PM to the power mixing control signal CON_PM. In response, even if the magnitude of the internal power supply voltage changes, a stable output voltage can be generated.

9 is a block diagram illustrating an example of an output circuit 1700 included in the semiconductor memory device 1000 of FIG. 8.

Referring to FIG. 9, the output circuit 1700 may include an ordering circuit 1710, a first multiplexer 1720, a second multiplexer 1730, and an output driving circuit 1740.

The ordering circuit 1710 determines the output order for the first data SAO. The first multiplexer 1720 selects an output bit structure and outputs second data in response to an output signal of the ordering circuit 1710. The second multiplexer 1730 generates third data by performing parallel-serial conversion on the second data in response to the output clock signal CLKDQ. The output driving circuit 1740 performs power mixing on the third data and generates output data.

The semiconductor memory device 1000 illustrated in FIG. 8 may include a volatile memory chip such as a dynamic random access memory (DRAM) and a static random access memory (SRAM), a flash memory, and a phase change memory (SRAM). non-volatile memory chips such as phase change memory, magnetic random access memory (MRAM), or resistive random access memory (RRAM), or a combination thereof.

10 is a diagram illustrating an example of a memory system including a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 10, the memory system 30 may include a motherboard 31, a chipset (or controller) 40, slots 35_1 and 35_2, memory modules 50 and 60, and transmission lines 33 and 34. ) May be included. Buses 37 and 39 connect chipset 40 to slots 35_1 and 35_2. The terminal resistor Rtm may terminate each of the buses 37 and 39 on the PCB of the motherboard 31.

10 illustrates two slots 35_1 and 35_2 and two memory modules 50 and 60 for convenience, the memory system 30 may include any number of slots and memory modules.

The chipset 40 may be mounted on the PCB of the motherboard 31 and control the operation of the memory system 30. Chipset 40 may include connectors 41_1 and 41_2 and converters 43_1 and 43_2.

The converter 43_1 receives the parallel data generated by the chipset 40, converts the parallel data into serial data, and outputs the parallel data to the transmission line 33 through the connector 411. The converter 43_1 receives serial data through the transmission line 33, converts the serial data into parallel data, and outputs the serial data to the chipset 40.

The converter 43_2 receives parallel data generated by the chipset 40, converts the parallel data into serial data, and outputs the parallel data to the transmission line 34 through the connector 412. The converter 43_2 receives serial data through the transmission line 34, converts the serial data into parallel data, and outputs the serial data to the chipset 40. The transmission lines 33 and 34 included in the memory system 30 may be a plurality of optical fibers.

The memory module 50 may include a plurality of memory devices 55_1 to 55_n, a first connector 57, a second connector 51, and converters 53. The memory module 60 may include a plurality of memory devices 65_1 ˜ 65_n, a first connector 57 ′, a second connector 51 ′, and converters 53 ′.

The first connector 57 may transmit the low speed signal received from the chip set to the memory devices, and the second connector 51 may be connected to the transmission line 33 for transmitting the high speed signal.

The converter 53 receives serial data through the second connector 51, converts the serial data into parallel data, and outputs the serial data to the plurality of memory devices 55_1 to 55_n. In addition, the converter 53 receives parallel data from the plurality of memory devices 55_1 to 55_n, converts the parallel data into serial data, and outputs the parallel data to the second connector 51.

The plurality of memory devices 55_1 to 55_n and 65_1 to 65_n of FIG. 10 may include semiconductor memory devices according to example embodiments of the inventive concept. Thus, the plurality of memory devices 55_1 to 55_n and 65_1 to 65_n may include an output circuit according to embodiments of the present invention. The output circuit included in the memory devices 55_1 to 55_9 has a power mixing function, and a power mixing control signal based on the deep power down mode signal PDPD and the power up signal VCCHB in the deep power down mode. Even when the CON_PM is enabled and the magnitude of the internal power supply voltage changes in response to the power mixing control signal CON_PM, a stable output voltage may be generated.

 The plurality of memory devices 55_1 to 55_n and 65_1 to 65_n may include volatile memory chips such as dynamic random access memory (DRAM) and static random access memory (SRAM), flash memory, and image. Non-volatile memory chips such as phase change memory, magnetic random access memory (MRAM), or resistive random access memory (RRAM), or a combination thereof.

11 is a simplified perspective view illustrating one of the stacked semiconductor devices 2100 including the semiconductor memory device 1000 according to an embodiment of the present invention.

Referring to FIG. 11, the stacked semiconductor device 2100 may include an interface chip 2110 and memory chips 2120, 2130, 2140, and 2150 electrically connected by a through silicon via 2160. 22 illustrates a through electrode 2160 disposed in two rows, but the stacked semiconductor device 2100 may have any number of through electrodes.

The memory chips 2120, 2130, 2140, and 2150 included in the multilayer semiconductor device 2100 may include an output circuit according to example embodiments. The output circuit included in the memory chips 2120, 2130, 2140, and 2150 has a power mixing function, and controls power mixing based on the deep power down mode signal PDPD and the power up signal VCCHB in the deep power down mode. Even when the signal CON_PM is enabled and the magnitude of the internal power supply voltage changes in response to the power mixing control signal CON_PM, a stable output voltage may be generated. The interface chip 2110 performs an interface between the memory chips 2120, 2130, 2140, and 2150 and an external device.

12 is a block diagram illustrating another example of a memory system 2200 including a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 12, the memory system 2200 includes a memory controller 1210 and a semiconductor memory device 2220.

The memory controller 2210 generates an address signal ADD and a command CMD and provides the address signal ADD and a command CMD to the semiconductor memory device 2220 through buses. The data DQ is transferred from the memory controller 2210 to the semiconductor memory device 2220 through a bus or from the semiconductor memory device 2220 to the memory controller 2210 through a bus.

The semiconductor memory device 2220 may be a semiconductor memory device including an output circuit having a power mixing function according to embodiments of the present invention. The semiconductor memory device 2220 may generate a stable output voltage even when the magnitude of the internal power supply voltage changes.

13 is a block diagram illustrating an example of an electronic system 2300 including a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 13, an electronic system 2300 according to an embodiment of the present disclosure may include a controller 2310, an input / output device 2320, a memory device 2330, an interface 2340, and a bus 2350. have. The memory device 2330 may be a semiconductor memory device including an output circuit having a power mixing function according to embodiments of the present invention. The bus 2350 may serve to provide a path through which data moves between the controller 2310, the input / output device 2320, the memory device 2330, and the interface 2340.

The controller 2310 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing functions similar thereto. The input / output device 2320 may include at least one selected from a keypad, a keyboard, a display device, and the like. The memory device 2330 may store data and / or instructions executed by the controller 2310.

The memory device 2330 may include volatile memory chips such as dynamic random access memory (DRAM) and static random access memory (SRAM), flash memory, phase change memory, and RAM. nonvolatile memory chips, such as magnetic random access memory (MRAM), or random random access memory (RRAM), or a combination thereof. The memory device 2330 may be a semiconductor memory device including an output circuit having a power mixing function according to embodiments of the present invention. The memory device 2330 may generate a stable output voltage even when the magnitude of the internal power supply voltage changes. The interface 2340 may serve to transmit data to or receive data from the communication network. The interface 2340 may include an antenna or a wired / wireless transceiver, and may transmit and receive data by wire or wirelessly. In addition, the interface 2340 may include an optical fiber, and may transmit and receive data through the optical fiber. The electronic system 2300 may further include an application chipset, a camera image processor, and an input / output device.

The electronic system 2300 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, mobile systems may include personal digital assistants (PDAs), portable computers, web tablets, mobile phones, wireless phones, laptop computers, memory cards, It may be one of a digital music system and an information transmission / reception system. When the electronic system 2300 is a device capable of performing wireless communication, the electronic system 2300 may include code division multiple access (CDMA), global system for mobile communication (GSM), north american digital cellular (NADC), and ETDMA. It can be used in communication systems such as Enhanced Time Division Multiple Access (WDDMA), Wideband Code Division Multiple Access (WCDMA), and CDMA2000.

The present invention can be applied to a semiconductor device, in particular a semiconductor memory device for mobile and a memory system including the same.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

100, 200: power mixing circuit 110: input buffer
120: power mixing unit 140: output buffer
150: power mixing control circuit 1000: semiconductor memory device
1100: address input buffer 1200: row decoder
1300: column decoder 1400: power-up signal generating circuit
1500: memory cell array 1600: input / output sense amplifiers
1700 and output circuit 2100: laminated semiconductor device
30, 2200: memory system 2300: electronic system

Claims (10)

An input buffer operating using a first power supply voltage and buffering an input signal to generate a first voltage signal;
A power mixing control circuit for generating a power mixing control signal in response to the power up signal and the deep power down mode signal;
A power mixing unit which operates using an external power supply voltage and a second power supply voltage, performs power mixing on the first voltage signal in response to the power mixing control signal, and generates a second voltage signal; And
And an output buffer configured to operate using the second power supply voltage and to buffer the second voltage signal to generate an output signal. The method of claim 1, wherein the power mixing circuit
And a stable output voltage even when the magnitude of the first power supply voltage changes. The power mixing control circuit of claim 1, wherein the power mixing control circuit comprises:
And operating using the external power supply voltage. The method of claim 1, wherein the power mixing unit
A first NOR circuit operating using the external power supply voltage and performing a non-logical sum operation on the power mixing control signal and the first voltage signal;
A first inverter operating using the second power supply voltage and inverting a phase of an output signal of the first NOR circuit;
A second NOR circuit operating using the second power supply voltage and performing a non-logical sum operation on the power mixing control signal and the first voltage signal; And
And a second inverter operating by using the second power supply voltage and inverting a phase of an output signal of the second NOR circuit. The power mixing control circuit of claim 1, wherein the power mixing control circuit comprises:
A NOR circuit for performing an illogical operation on the power up signal and the deep power down mode signal;
A first inverter for inverting a phase of an output signal of the NOR circuit;
A first PMOS transistor having a gate connected to an output terminal of the NOR circuit, and a source connected to the external power supply voltage;
A first NMOS transistor having a gate connected to an output terminal of the first inverter, and a source connected to ground;
A first latch circuit coupled to the drain of the first PMOS transistor and the drain of the first NMOS transistor;
A second latch circuit for latching a voltage of the drain of the first PMOS transistor and inverting a phase of the voltage of the drain;
A second inverter for inverting a phase of an output signal of the second latch circuit;
A second PMOS transistor having a gate connected to an output terminal of the second inverter and a source connected to the external power supply voltage;
A second NMOS transistor having a drain connected to the drain of the second PMOS transistor, a gate connected to an output terminal of the first inverter, and a source connected to the ground;
A third inverter for inverting the phase of the voltage of the drain of the second NMOS transistor; And
And an OR circuit for performing an OR operation on the output signal of the second latch circuit and the output signal of the third inverter and generating the power mixing control signal. The method of claim 1, wherein the power mixing unit
A first NAND circuit operating using the external power supply voltage and performing a non-logical operation on the power mixing control signal and the first voltage signal;
A first inverter operating by using the second power supply voltage and inverting a phase of an output signal of the first NAND circuit;
A second NAND circuit operating using the second power supply voltage and performing a non-logical operation on the power mixing control signal and the first voltage signal; And
And a second inverter operating by using the second power supply voltage, and inverting a phase of an output signal of the second NAND circuit. The method according to claim 6,
And the power mixing control signal is in a logic low state in a deep power down mode. A memory cell array operative in response to a word line enable signal and a column select signal;
An address input buffer for generating a row address signal and a column address signal based on an external address;
A row decoder to decode the row address signal to generate a wordline enable signal;
A column decoder for providing a column selection signal by decoding the column address signal;
An input / output sense amplifier configured to amplify data output from the memory cell array to generate first data, and to transfer data input from the outside to the memory cell array;
A power up signal generation circuit for generating a power up signal based on an external power supply voltage; And
An output circuit for performing power mixing on the output signal of the input / output sense amplifier based on a deep power down mode signal, the power up signal, and the external power supply voltage, and generating output data;
In the deep power down mode, a power mixing control signal is generated based on the deep power down mode signal and the power up signal, and stable output voltage is generated even when an internal power supply voltage changes in response to the power mixing control signal. A semiconductor memory device, characterized in that. The method of claim 8, wherein the output circuit
An ordering circuit that determines an output order for the first data;
A first multiplexer for selecting an output bit structure and outputting second data in response to an output signal of the ordering circuit;
A second multiplexer for performing third-to-serial conversion on the second data to generate third data; And
And an output driving circuit which performs power mixing on the third data and generates the output data. The method of claim 8, wherein the semiconductor memory device
A semiconductor memory device comprising: a stacked memory device in which a plurality of chips for transmitting and receiving data and control signals through a through electrode (TSV: ThroughSiliconVia) are stacked.

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