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KR20130075552A - Semiconductor package and method for manufacturing semiconductor package - Google Patents

Semiconductor package and method for manufacturing semiconductor package Download PDF

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Publication number
KR20130075552A
KR20130075552A KR1020110143951A KR20110143951A KR20130075552A KR 20130075552 A KR20130075552 A KR 20130075552A KR 1020110143951 A KR1020110143951 A KR 1020110143951A KR 20110143951 A KR20110143951 A KR 20110143951A KR 20130075552 A KR20130075552 A KR 20130075552A
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South Korea
Prior art keywords
thin film
semiconductor package
forming
silicon
manufacturing
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KR1020110143951A
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Korean (ko)
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KR101341619B1 (en
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박종철
김준철
김동수
박세훈
유종인
육종민
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전자부품연구원
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Publication of KR20130075552A publication Critical patent/KR20130075552A/en
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Publication of KR101341619B1 publication Critical patent/KR101341619B1/en

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A semiconductor package and a manufacturing method thereof are provided to implement a thin film type semiconductor package by embedding a thin film passive device in a substrate. CONSTITUTION: At least one first hole is formed on a silicon substrate (110) integrated with a thin film passive device (120). An integrated circuit (130) is inserted into the first hole. A connection member (140) for connecting the integrated circuit to the thin film passive device is formed. An organic insulation layer is made of organic materials by a lamination process. An connection electrode is formed after the connection member is molded. [Reference numerals] (AA,CC) Thin film capacitor; (BB,DD) Spiral inductor

Description

반도체 패키지 및 그의 제조 방법{SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE}Semiconductor package and its manufacturing method {SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE}

본 발명은 반도체 패키지 및 그의 제조 방법에 관한 것으로, 더욱 자세하게 말하면 반도체 패키지의 실리콘 인터포저 및 그의 제조 방법에 관한 것이다.The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a silicon interposer and a method of manufacturing the semiconductor package.

여러 집적 회로(Integrated Circuit, IC)와 개별 부품이 패키지에 고집적되어 있는 MCM(Multi-chip Module) 기술은 주로 PCB 또는 LTCC와 같은 라미네이트(Laminate) 기판을 이용한다. 그러나 PCB와 LTCC 기술은 모두 미세 배선 공정이 어렵고, 박막 수동 소자의 집적이 불가능해 고집적 초소형 모듈을 구현하는데 있어 기술적 한계가 있다. Multi-chip Module (MCM) technology, in which several integrated circuits (ICs) and discrete components are highly integrated in a package, mainly uses laminate substrates such as PCBs or LTCCs. However, both PCB and LTCC technologies are difficult to fine-tune the wiring process and impossible to integrate thin film passive devices, so there are technical limitations in implementing highly integrated micro modules.

또한 고집적 소형화를 위해 사용되는 SoC(System on Chip)와 MMIC(Monolithic Microwave Integrated Circuit) 기술의 경우 고집적 구현은 가능하지만, 가격이 비싸고 모든 시스템 및 소자를 구현하는 데 있어 어려움이 있다. In addition, highly integrated implementations of System on Chip (SoC) and Monolithic Microwave Integrated Circuit (MMIC) technologies, which are used for high-density miniaturization, are expensive, but they are expensive and have difficulty in implementing all systems and devices.

이러한 문제를 해결하기 위해 최근 실리콘 인터포저(Silicon Interposer) 기술을 활용한 모듈에 대한 연구가 진행되고 있다. 그러나 제안된 실리콘 인터포저 또는 IPD(Integrated Passive Device) 기술을 활용한 모듈 제작 기술의 경우 단순히 IC를 실리콘 기판에 실장(mounting)하는 형태로, 모듈의 두께를 줄이기에는 한계가 있다. In order to solve this problem, researches on modules utilizing silicon interposer technology have recently been conducted. However, the module fabrication technology using the proposed silicon interposer or integrated passive device (IPD) technology has a limitation in reducing the thickness of the module by simply mounting the IC on a silicon substrate.

본 발명이 해결하고자 하는 기술적 과제는 고집적 초소형 모듈을 구현할 수 있는 반도체 패키지 및 그의 제조 방법을 제공하는 것이다. The technical problem to be solved by the present invention is to provide a semiconductor package and a method of manufacturing the same that can implement a highly integrated miniature module.

본 발명의 한 실시 예에 따르면, 반도체 패키지를 제조하는 방법이 제공된다. 반도체 패키지의 제조 방법은 박막 수동 소자가 집적된 실리콘 기판에 적어도 하나의 제1 구멍을 형성하는 단계, 상기 구멍에 집적 회로를 삽입하는 단계, 그리고 상기 집적 회로와 상기 박막 수동 소자와의 연결 부재를 형성하는 단계를 포함한다. According to an embodiment of the present invention, a method of manufacturing a semiconductor package is provided. A method of manufacturing a semiconductor package includes forming at least one first hole in a silicon substrate in which a thin film passive device is integrated, inserting an integrated circuit into the hole, and connecting the integrated circuit and the thin film passive device. Forming a step.

상기 연결 부재를 형성하는 단계는 상기 집적 회로와 상기 박막 수동 소자를 와이어 본딩하는 단계를 포함할 수 있다. The forming of the connection member may include wire bonding the integrated circuit and the thin film passive device.

상기 반도체 패키지의 제조 방법은 상기 연결 부재를 몰딩 처리한 후 연결 전극을 형성하는 단계를 더 포함할 수 있다. The method of manufacturing the semiconductor package may further include forming a connection electrode after molding the connection member.

상기 반도체 패키지의 제조 방법은 상기 실리콘 기판에 적어도 하나의 제2 구멍을 형성하는 단계, 상기 제2 구멍에 관통 실리콘 비아를 형성하는 단계, 그리고 상기 관통 실리콘 비아와 상기 박막 수동 소자 사이의 연결 전극을 형성하는 단계를 더 포함할 수 있다. The method of manufacturing the semiconductor package may include forming at least one second hole in the silicon substrate, forming a through silicon via in the second hole, and connecting a connection electrode between the through silicon via and the thin film passive element. It may further comprise the step of forming.

본 발명의 다른 실시 예에 따르면, 반도체 패키지가 제공된다. 반도체 패키지는 수동 박막 소자가 집적된 기판, 상기 기판에 형성되는 제1 구멍에 삽입되는 집적 회로, 그리고 상기 수동 박막 소자와 상기 집적 회로를 와이어 본딩을 이용하여 연결하는 연결 부재를 포함한다. According to another embodiment of the present invention, a semiconductor package is provided. The semiconductor package includes a substrate on which passive thin film elements are integrated, an integrated circuit inserted into a first hole formed in the substrate, and a connection member connecting the passive thin film element and the integrated circuit using wire bonding.

본 발명의 실시 예에 의하면, 실리콘 기판에 능동 IC와 집적 수동 소자가 결합된 초소형 초박형 모듈 구현이 가능해진다. 이때, 실리콘 기판에 구멍(cavity)를 형성하고 이 구멍에 IC를 삽입함으로써 최소한의 와이어 본딩(wire-bonding) 길이로 입출력 연결 형성이 가능하다. 또한 IC 삽입 후 유기 라미네이션 공정을 적용할 경우 미세 배선 공정 기술을 이용해 IC와 기판간 최소 길이의 연결 형성이 가능해지며, 박막 수동 소자를 기판에 함께 내장함으로 초박형의 패키지 구현이 가능해진다. According to an embodiment of the present invention, it is possible to implement a very small ultra-thin module in which an active IC and an integrated passive device are combined on a silicon substrate. At this time, by forming a cavity in the silicon substrate and inserting an IC into the hole, input / output connection can be formed with a minimum wire-bonding length. In addition, when the organic lamination process is applied after inserting the IC, it is possible to form a minimum length connection between the IC and the substrate using a micro wiring process technology, and an ultra-thin package can be realized by embedding a thin film passive element together on the substrate.

또한 미세 배선 및 박막 수동 소자의 집적을 통해 밀리미터파 대역 이상의 주파수 응용이 가능한 정밀 패키지 구현이 가능해질 수 있다. In addition, the integration of fine wiring and thin-film passive devices can enable precise package implementations for frequency applications above the millimeter wave band.

도 1은 본 발명의 제1 실시 예에 따른 실리콘 인터포저의 단면을 나타낸 도면이다.
도 2a 내지 도 2c는 각각 발명의 제1 실시 예에 따른 실리콘 인터포저의 제조 공정에 따른 단면도를 나타낸 도면이다.
도 3은 본 발명의 제2 실시 예에 따른 실리콘 인터포저의 단면을 나타낸 도면이다.
도 4는 본 발명의 실시 예에 따른 반도체 패키지의 일 예를 나타낸 도면이다.
도 5는 본 발명의 제3 실시 예에 따른 실리콘 인터포저를 나타낸 도면이다.
도 6a 내지 도 6e는 각각 제3 실시 예에 따른 실리콘 인터포저의 제조 공정에 따른 단면도를 나타낸 도면이다.
도 7은 본 발명의 제4 실시 예에 따른 실리콘 인터포저를 나타낸 도면이다.
도 8은 본 발명의 제5 실시 예에 따른 실리콘 인터포저의 단면을 나타낸 도면이다.
도 9a 내지 도 9d는 각각 본 발명의 제5 실시 예에 따른 실리콘 인터포저의 제조 공정에 따른 단면도를 나타낸 도면이다.
도 10 본 발명의 제6 실시 예에 따른 실리콘 인터포저의 단면을 나타낸 도면이다. 1 is a cross-sectional view of a silicon interposer according to a first embodiment of the present invention.
2A through 2C are cross-sectional views illustrating a process of manufacturing a silicon interposer according to a first embodiment of the present invention, respectively.
3 is a cross-sectional view of a silicon interposer according to a second embodiment of the present invention.
4 is a diagram illustrating an example of a semiconductor package according to an embodiment of the inventive concept.
5 is a diagram illustrating a silicon interposer according to a third embodiment of the present invention.
6A to 6E are cross-sectional views illustrating a process of manufacturing a silicon interposer according to a third embodiment, respectively.
7 is a diagram illustrating a silicon interposer according to a fourth embodiment of the present invention.
8 is a cross-sectional view of a silicon interposer according to a fifth embodiment of the present invention.
9A to 9D are cross-sectional views illustrating a process of manufacturing a silicon interposer according to a fifth embodiment of the present invention, respectively.
10 is a cross-sectional view of a silicon interposer according to a sixth embodiment of the present invention.

아래에서는 첨부한 도면을 참고로 하여 본 발명의 실시 예에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세히 설명한다. 그러나 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며 여기에서 설명하는 실시 예에 한정되지 않는다. 그리고 도면에서 본 발명을 명확하게 설명하기 위해서 설명과 관계없는 부분은 생략하였으며, 명세서 전체를 통하여 유사한 부분에 대해서는 유사한 도면 부호를 붙였다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

명세서 및 청구범위 전체에서, 어떤 부분이 어떤 구성 요소를 "포함"한다고 할 때, 이는 특별히 반대되는 기재가 없는 한 다른 구성요소를 제외하는 것이 아니라 다른 구성 요소를 더 포함할 수 있는 것을 의미한다. Throughout the specification and claims, when a section is referred to as "including " an element, it is understood that it does not exclude other elements, but may include other elements, unless specifically stated otherwise.

이제 본 발명의 실시 예에 따른 반도체 패키지 및 그의 제조 방법에 대하여 도면을 참고로 하여 상세하게 설명한다. A semiconductor package and a method of manufacturing the same according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

도 1은 본 발명의 제1 실시 예에 따른 실리콘 인터포저의 단면을 나타낸 도면이다. 1 is a cross-sectional view of a silicon interposer according to a first embodiment of the present invention.

도 1을 참고하면, 실리콘 인터포저(100)는 실리콘 기판(110), 집적 수동 소자(integrated passive device, IPD)(120) 및 집적 회로(Integrated Circuit, IC)(130) 및 연결 부재(140)를 포함한다. Referring to FIG. 1, the silicon interposer 100 includes a silicon substrate 110, an integrated passive device (IPD) 120, an integrated circuit (IC) 130, and a connection member 140. It includes.

IPD(120)는 실리콘 기판(110)에 집적되며, IPD(120)는 나선형 인덕터(L)와 박막 커패시터, 박막 저항 등을 포함할 수 있으며 도 1에서는 나선형 인덕터와 박막 커패시터만을 도시하였다. The IPD 120 is integrated in the silicon substrate 110, and the IPD 120 may include a spiral inductor L, a thin film capacitor, a thin film resistor, and the like. In FIG. 1, only the spiral inductor and the thin film capacitor are illustrated.

IC(130)는 실리콘 기판(110)에 형성된 구멍(cavity)에 삽입된다. The IC 130 is inserted into a cavity formed in the silicon substrate 110.

연결 부재(140)는 IC(130)와 IPD(120)의 연결(interconnection)을 제공한다. The connection member 140 provides an interconnection of the IC 130 and the IPD 120.

이러한 실리콘 인터포저(100)의 기판으로 실리콘 기판(110) 대신에 박막 공정이 가능한 다른 기판이 사용될 수 있으며, 예를 들면 박막 공정이 가능한 유리나 세라믹 등이 인터포저(10)의 기판으로 사용될 수 있다. As the substrate of the silicon interposer 100, another substrate capable of a thin film process may be used instead of the silicon substrate 110. For example, glass or ceramic capable of a thin film process may be used as the substrate of the interposer 10. .

도 1에 도시된 실리콘 인터포저(100)의 제조 방법에 대해서 도 2a 내지 도 2c를 참고로 하여 자세하게 설명한다. A method of manufacturing the silicon interposer 100 shown in FIG. 1 will be described in detail with reference to FIGS. 2A to 2C.

도 2a 내지 도 2c는 각각 발명의 제1 실시 예에 따른 실리콘 인터포저의 제조 공정에 따른 단면도를 나타낸 도면이다. 2A through 2C are cross-sectional views illustrating a process of manufacturing a silicon interposer according to a first embodiment of the present invention, respectively.

도 2a를 참고하면, 실리콘 기판(110)에 나선형 인덕터와 박막 커패시터를 집적한다. 이와 같이 실리콘 기판(110)을 사용하면, 박막 커패시터와 같은 박막 수동 소자의 집적이 가능해지고, 이를 인터포저로 활용 가능하므로, 초소형 반도체 패키지 구현이 가능해진다. 실리콘 기판(110)에 나선형 인덕터와 박막 커패시터를 집적하는 공정은 일반적인 반도체 공정을 이용한 다층 금속 배선 공정으로, 상세한 설명은 생략한다. 이러한 다층 금속 배선 공정을 통해서 나선형 인덕터와 박막 커패시터가 실리콘 기판(110)에 집적되고 IC(130)와의 전기적인 연결을 위한 연결 전극(122, 124)도 형성된다. Referring to FIG. 2A, a spiral inductor and a thin film capacitor are integrated in the silicon substrate 110. As such, when the silicon substrate 110 is used, integration of a thin film passive device such as a thin film capacitor is possible, and this may be utilized as an interposer, thereby realizing a micro semiconductor package. The process of integrating the spiral inductor and the thin film capacitor on the silicon substrate 110 is a multilayer metal wiring process using a general semiconductor process, and a detailed description thereof will be omitted. Through the multilayer metal wiring process, the spiral inductor and the thin film capacitor are integrated on the silicon substrate 110, and connection electrodes 122 and 124 for electrical connection with the IC 130 are also formed.

다음, 도 2b를 참고하면, 나선형 인덕터와 박막 커패시터가 집적된 실리콘 기판(110)에 레이저 드릴링 또는 플라즈마 식각 등을 이용하여 적어도 하나의 구멍(112)을 형성한다. Next, referring to FIG. 2B, at least one hole 112 is formed in the silicon substrate 110 in which the spiral inductor and the thin film capacitor are integrated using laser drilling or plasma etching.

그리고 도 2c를 보면, 실리콘 기판(110)에 형성된 구멍(116)에 전도성 또는 비전도성 에폭시(epoxy)를 이용하여 IC(130)를 삽입 고정시킨 뒤에 와이어 본딩(wire bonding) 기술을 이용하여 연결 부재(140)를 형성한다. 또한 와이어 본딩(wire bonding) 기술을 이용하여 실리콘 인터포저(100)의 입출력 단자에 연결되는 외부 전극 패드(도 4의 142)가 형성될 수 있다. 이와 같이, 실리콘 기판(110)에 형성된 구멍(116)에 IC(130)를 삽입함으로써, 기판 상에 IC를 형성하는 모듈에 비해 초소형 및 초박형의 구현이 가능해진다. 2C, after the IC 130 is inserted into and fixed to the hole 116 formed in the silicon substrate 110 by using conductive or non-conductive epoxy, a connection member using wire bonding technology. 140 is formed. In addition, an external electrode pad (142 of FIG. 4) may be formed to be connected to an input / output terminal of the silicon interposer 100 using a wire bonding technology. As such, by inserting the IC 130 into the hole 116 formed in the silicon substrate 110, it is possible to implement a very small and ultra-thin compared to the module for forming the IC on the substrate.

이렇게 하여, 실리콘 인터포저(100)가 완성될 수 있다. In this way, the silicon interposer 100 can be completed.

도 3은 본 발명의 제2 실시 예에 따른 실리콘 인터포저의 단면을 나타낸 도면이다. 3 is a cross-sectional view of a silicon interposer according to a second embodiment of the present invention.

도 3을 참고하면, 실리콘 인터포저(300)는 도 2c의 공정을 거쳐서 연결 부재(140)가 형성된 후에 몰딩 처리하여 몰딩층(150)을 형성한 후에 비아를 통해서 연결 전극(152)을 형성한다. 이렇게 하면, 실리콘 인터포저(300)의 연결 부재를 외부로부터 보호할 수가 있다. Referring to FIG. 3, the silicon interposer 300 forms the connection layer 152 through vias after forming the molding layer 150 by molding after forming the connection member 140 through the process of FIG. 2C. . In this way, the connecting member of the silicon interposer 300 can be protected from the outside.

즉, 실리콘 인터포저(300) 또한 나선형 인덕터와 박막 커패시터가 집적된 실리콘 기판(110) 내부에 IC(130)를 삽입 고정시킨 후에 와이어 본딩하여 나선형 인덕터와 IC(130), 박막 커패시터와 IC(130)를 연결한다. That is, the silicon interposer 300 also inserts and fixes the IC 130 inside the silicon substrate 110 in which the spiral inductor and the thin film capacitor are integrated, and then wire-bonds the spiral inductor and the IC 130, the thin film capacitor and the IC 130. ).

그리고 실리콘 인터포저(300)에서 IC(130)를 실리콘 기판(110) 내부에 삽입함으로써 몰딩 두께를 얇게 할 수 있고 이로 인해서 몰딩 이후에 비아를 통해 연결 전극(152)과 같은 외부 전극이 쉽게 형성 가능해진다. In addition, the thickness of the molding may be reduced by inserting the IC 130 into the silicon substrate 110 in the silicon interposer 300. Therefore, an external electrode such as the connection electrode 152 may be easily formed through the via after the molding. Become.

도 4는 본 발명의 실시 예에 따른 반도체 패키지의 일 예를 나타낸 도면이다. 4 is a diagram illustrating an example of a semiconductor package according to an embodiment of the inventive concept.

도 4에 도시한 바와 같이 실리콘 인터포저(100, 300)를 보드나 배선 기판(310)에 전기적으로 연결하여 반도체 패키지(400)가 형성될 수 있다. 이때, 실리콘 인터포저(100)와 배선 기판(410)은 실리콘 인터포저(100)의 외부 전극 패드(142)를 통해서 연결될 수 있다. 도 4에서는 배선 기판(310)에 실리콘 인터포저(100)를 연결한 반도체 패키지를 도시하였다. As shown in FIG. 4, the semiconductor package 400 may be formed by electrically connecting the silicon interposers 100 and 300 to the board or the wiring board 310. In this case, the silicon interposer 100 and the wiring board 410 may be connected through an external electrode pad 142 of the silicon interposer 100. 4 illustrates a semiconductor package in which the silicon interposer 100 is connected to the wiring board 310.

도 5는 본 발명의 제3 실시 예에 따른 실리콘 인터포저를 나타낸 도면이고, 도 6a 내지 도 6e는 각각 제3 실시 예에 따른 실리콘 인터포저의 제조 공정에 따른 단면도를 나타낸 도면이다.FIG. 5 is a diagram illustrating a silicon interposer according to a third embodiment of the present invention, and FIGS. 6A to 6E are cross-sectional views illustrating processes of manufacturing a silicon interposer according to a third embodiment.

도 5를 참고하면, 실리콘 인터포저(500)는 실리콘 기판(110)에 형성된 관통 실리콘 비아(through silicon via, TSV)(160) 및 범프(154)를 더 포함한다는 점을 제외하면 제2 실시 예에 따른 반도체 패키지(300)와 동일하다. Referring to FIG. 5, the silicon interposer 500 further includes a through silicon via (TSV) 160 and a bump 154 formed in the silicon substrate 110. The same as the semiconductor package 300 according to.

도 6a를 참고하면, 실리콘 기판(110)에 TSV 제조 공정을 이용하여 TSV(160)를 형성한다. TSV 제조 공정은 일반적인 TSV 공정 기술을 이용하여 제작된다. 가령 공정의 예로, 딥 리액티브 이온 에칭(Deep Reactive Ion Etching)을 이용해 실리콘 기판(110)을 식각한 뒤 이산화 규소(SiO2) 절연층을 형성하고, 티타늄 질화물(TiN) 또는 질화 탄탈늄(TaN)을 이용해 분산 배리어(Diffusion Barrier)를 형성한다. 이후 시드(Seed) 금속과 전기 도금을 통해 비아(Via)를 구리로 채우고 평탄화 공정을 진행하면 일반적인 형태의 TSV가 형성된다. Referring to FIG. 6A, the TSV 160 is formed on the silicon substrate 110 using a TSV manufacturing process. TSV manufacturing processes are manufactured using common TSV process techniques. For example, as a process, the silicon substrate 110 may be etched using deep reactive ion etching to form a silicon dioxide (SiO 2) insulating layer, and titanium nitride (TiN) or tantalum nitride (TaN) Using to form a diffusion barrier (Diffusion Barrier). Thereafter, vias are filled with copper through seed metal and electroplating, and a planarization process is performed to form TSVs in a general form.

다음, 도 6b를 참고하면, TSV(160)가 형성된 실리콘 기판(110)에 도 2a와 같이 나선형 인덕터와 박막 커패시터를 집적한다. 이때, 연결 전극(122, 124)은 TSV(160)와도 연결되도록 형성된다. Next, referring to FIG. 6B, a spiral inductor and a thin film capacitor are integrated on the silicon substrate 110 on which the TSV 160 is formed, as shown in FIG. 2A. In this case, the connection electrodes 122 and 124 are formed to be also connected to the TSV 160.

다음, 도 6c 및 도 6d를 참고하면, 도 2b 및 도 2c에서 설명한 것처럼, 실리콘 기판(110)에 적어도 하나의 구멍(112)을 형성한 후 실리콘 기판(110)에 형성된 구멍(112)에 IC(130)를 삽입 고정시킨 뒤에 와이어 본딩 기술을 이용하여 연결 부재(140)를 형성한다. Next, referring to FIGS. 6C and 6D, as described with reference to FIGS. 2B and 2C, after forming at least one hole 112 in the silicon substrate 110, the IC is formed in the hole 112 formed in the silicon substrate 110. After inserting and fixing the 130, the connection member 140 is formed using a wire bonding technique.

그리고 나서, 도 6e에 도시한 바와 같이, 연결 부재(140)를 보호하기 위해 몰딩 처리하여 몰딩층(150)을 형성한 후에 비아를 통해서 연결 전극(152)을 형성할 수 있다. 이때, TSV(160)에 전기적으로 연결되는 범프(154)를 형성할 수 있으며, 범프(154)는 단일 모듈의 실리콘 인터포저(500)를 적층할 때 실리콘 인터포저간 전기적 연결을 제공하는 역할을 한다. 6E, after forming the molding layer 150 by molding to protect the connection member 140, the connection electrode 152 may be formed through the via. In this case, a bump 154 may be formed to be electrically connected to the TSV 160. The bump 154 serves to provide electrical connection between the silicon interposers when the silicon interposers 500 of a single module are stacked. do.

또한 범프(154)를 이용하여 실리콘 인터포저(500)의 입출력 단자를 실리콘 인터포저(500)의 하부에 위치시킬 수 있으며 이 경우, 플립 칩(Filp-Chip)을 위한 BGA(ball grid array) 구조의 실리콘 인터포저(500)의 제작이 가능해진다. In addition, the bump 154 may be used to place an input / output terminal of the silicon interposer 500 under the silicon interposer 500. In this case, a ball grid array (BGA) structure for flip chip may be used. The silicon interposer 500 can be manufactured.

도 7은 본 발명의 제4 실시 예에 따른 실리콘 인터포저를 나타낸 도면이다. 7 is a diagram illustrating a silicon interposer according to a fourth embodiment of the present invention.

도 7을 참고하면, 실리콘 인터포저(700)는 적층되어 있는 복수의 실리콘 인터포저(500a, 500b, 500c)를 포함한다. 즉, 실리콘 인터포저(700)는 단일 모듈의 실리콘 인터포저(500a, 500b, 500c)들을 적층하고 실리콘 인터포저(500a, 500b, 500c)의 범프(154)를 통해서 전기적으로 연결하여 형성된다. 이때, 이들 단일 모듈의 반도체 패키지(500a, 500b, 500c)는 도 6a 내지 도 6e에 도시한 공정이 적용되어 제작될 수 있다. Referring to FIG. 7, the silicon interposer 700 includes a plurality of stacked silicon interposers 500a, 500b, and 500c. That is, the silicon interposer 700 is formed by stacking silicon interposers 500a, 500b, and 500c of a single module and electrically connecting the bumps 154 of the silicon interposers 500a, 500b, and 500c. In this case, the semiconductor packages 500a, 500b, and 500c of these single modules may be manufactured by applying the processes illustrated in FIGS. 6A to 6E.

도 8은 본 발명의 제5 실시 예에 따른 실리콘 인터포저의 단면을 나타낸 도면이고, 도 9a 내지 도 9d는 각각 본 발명의 제5 실시 예에 따른 실리콘 인터포저의 제조 공정에 따른 단면도를 나타낸 도면이다. 그리고 도 10 본 발명의 제6 실시 예에 따른 실리콘 인터포저의 단면을 나타낸 도면이다. 8 is a cross-sectional view illustrating a silicon interposer according to a fifth embodiment of the present invention, and FIGS. 9A to 9D are cross-sectional views illustrating a manufacturing process of a silicon interposer according to a fifth embodiment of the present invention. to be. 10 is a cross-sectional view of a silicon interposer according to a sixth embodiment of the present invention.

도 8을 참고하면, 실리콘 인터포저(800)는 유기 절연층(170, 180)을 이용하여 연결 전극(172) 및 다층 배선(174)을 형성한다는 점을 제외하면 본 발명의 제3 실시 예에 따른 실리콘 인터포저(500)와 동일하다. Referring to FIG. 8, except that the silicon interposer 800 forms the connection electrode 172 and the multi-layered wiring 174 using the organic insulating layers 170 and 180, the third embodiment of the present invention. Same as the silicon interposer 500 accordingly.

도 9a를 참고하면, 도 6a 내지 도 6c와 동일한 공정 단계를 통해서 실리콘 기판(110)에 적어도 하나의 구멍(112)을 형성한다. Referring to FIG. 9A, at least one hole 112 is formed in the silicon substrate 110 through the same process steps as FIGS. 6A to 6C.

다음, 도 9b를 참고하면, 실리콘 기판(110)에 형성된 구멍(112)에 IC(130)를 삽입 고정시킨 뒤에 유기 물질을 채워 넣은 후 라미네이션 공정을 수행하여 실리콘 기판(110)에 유기 절연층(170)을 형성한다. Next, referring to FIG. 9B, after the IC 130 is inserted into and fixed to the hole 112 formed in the silicon substrate 110, an organic material is filled and then a lamination process is performed on the silicon substrate 110. 170).

그리고 나서, 도 9c를 참고하면, 레이저 드릴링 또는 플라즈마 식각을 이용하여 삽입된 IC(130)와 실리콘 기판(100)의 박막 소자간 전기적 연결을 위한 비아 구멍을 형성한다. 그리고 패턴닝 공정을 이용해 IC(130)와 박막 커패시터, IC(130)와 나선형 인덕터간 전기적 연결(interconnection) 배선 공정을 수행하여 연결 전극(172)을 형성한다. 또한 다층 배선 공정을 수행하여 다층 배선(174)을 형성할 수도 있다. 이때, 연결 전극(172)이 반도체 패키지(100')에서 연결 부재(140)의 역할을 수행한다. Then, referring to FIG. 9C, a via hole for electrical connection between the inserted IC 130 and the thin film element of the silicon substrate 100 is formed by using laser drilling or plasma etching. In addition, the connection electrode 172 is formed by performing an interconnection wiring process between the IC 130, the thin film capacitor, the IC 130, and the spiral inductor using a patterning process. In addition, a multilayer wiring process may be performed to form the multilayer wiring 174. In this case, the connection electrode 172 serves as the connection member 140 in the semiconductor package 100 ′.

이와 같이 연결 전극(172)과 다층 배선(174)을 형성한 후 도 7d에 도시한 바와 After forming the connection electrode 172 and the multi-layered wiring 174 in this manner, as shown in FIG. 7D.

다음, 도 9d를 참고하면, 연결 전극(172)과 다층 배선(174)을 형성한 후 라미네이션 공정을 수행하여 실리콘 기판(110)에 유기 절연층(180)을 형성한다. 그리고 TSV(160)에 전기적으로 연결되는 범프(154)를 형성한다. Next, referring to FIG. 9D, after forming the connection electrode 172 and the multilayer wiring 174, an organic insulating layer 180 is formed on the silicon substrate 110 by performing a lamination process. And a bump 154 electrically connected to the TSV 160.

그리도 도 10에 도시한 바와 같이, 도 9a 내지 도 9d에 도시한 공정을 통해서 형성된 단일 모듈의 실리콘 인터포저(800a, 800b, 800c)를 적층하여 실리콘 인터포저(1000)를 형성할 수 있다. 10, the silicon interposer 1000 may be formed by stacking the single module silicon interposers 800a, 800b, and 800c formed through the process illustrated in FIGS. 9A to 9D.

이상에서 본 발명의 실시 예에 대하여 상세하게 설명하였지만 본 발명의 권리 범위는 이에 한정되는 것은 아니고 다음의 청구범위에서 정의하고 있는 본 발명의 기본 개념을 이용한 당업자의 여러 변형 및 개량 형태 또한 본 발명의 권리 범위에 속하는 것이다.While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Claims (8)

반도체 패키지를 제조하는 방법으로,
박막 수동 소자가 집적된 실리콘 기판에 적어도 하나의 제1 구멍을 형성하는 단계,
상기 구멍에 집적 회로를 삽입하는 단계, 그리고
상기 집적 회로와 상기 박막 수동 소자와의 연결 부재를 형성하는 단계
를 포함하는 반도체 패키지의 제조 방법. As a method of manufacturing a semiconductor package,
Forming at least one first hole in the silicon substrate in which the thin film passive element is integrated;
Inserting an integrated circuit into the hole, and
Forming a connection member between the integrated circuit and the thin film passive element
Method of manufacturing a semiconductor package comprising a. 제1항에서,
상기 연결 부재를 형성하는 단계는,
상기 집적 회로와 상기 박막 수동 소자를 와이어 본딩하는 단계를 포함하는 반도체 패키지의 제조 방법. In claim 1,
Forming the connection member,
Wire bonding the integrated circuit and the thin film passive device. 제1항에서,
상기 연결 부재를 몰딩 처리한 후 연결 전극을 형성하는 단계
를 더 포함하는 반도체 패키지의 제조 방법. In claim 1,
Forming a connection electrode after molding the connection member
Method of manufacturing a semiconductor package further comprising. 제1항에서,
상기 실리콘 기판에 적어도 하나의 제2 구멍을 형성하는 단계,
상기 제2 구멍에 관통 실리콘 비아를 형성하는 단계, 그리고
상기 관통 실리콘 비아와 상기 박막 수동 소자 사이의 연결 전극을 형성하는 단계
를 더 포함하는 반도체 패키지의 제조 방법.In claim 1,
Forming at least one second hole in the silicon substrate,
Forming through silicon vias in the second hole, and
Forming a connection electrode between the through silicon via and the thin film passive element
Method of manufacturing a semiconductor package further comprising. 제4항에서,
상기 연결 부재를 형성한 후에 라미네이션 공정을 이용하여 유기(organic) 물질로 유기 절연층을 형성하는 단계, 그리고
상기 박막 수동 소자와 상기 집적 회로의 연결을 위한 연결 전극을 형성하는 단계
를 더 포함하는 반도체 패키지의 제조 방법. 5. The method of claim 4,
Forming an organic insulating layer of an organic material by using a lamination process after forming the connecting member, and
Forming a connection electrode for connecting the thin film passive element and the integrated circuit
Method of manufacturing a semiconductor package further comprising. 제4항에서,
상기 연결 전극이 형성되는 관통 실리콘 비아의 다른 면에 범프를 형성하는 단계
를 더 포함하는 반도체 패키지의 제조 방법. 5. The method of claim 4,
Forming bumps on the other side of the through silicon via where the connection electrode is formed
Method of manufacturing a semiconductor package further comprising. 수동 박막 소자가 집적된 기판,
상기 기판에 형성되는 제1 구멍에 삽입되는 집적 회로, 그리고
상기 수동 박막 소자와 상기 집적 회로를 와이어 본딩을 이용하여 연결하는 연결 부재
를 포함하는 반도체 패키지. Substrates incorporating passive thin film elements,
An integrated circuit inserted into a first hole formed in the substrate, and
A connection member connecting the passive thin film element and the integrated circuit using wire bonding.
≪ / RTI > 제7항에서,
상기 기판에 형성되는 제2 구멍에 형성되며 상기 수동 박막 소자와의 연결을 제공하는 관통 실리콘 비아
를 더 포함하는 반도체 패키지. In claim 7,
Through silicon vias formed in the second holes formed in the substrate and providing connection with the passive thin film elements.
A semiconductor package further comprising.
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WO2015130680A1 (en) * 2014-02-28 2015-09-03 Qualcomm Incorporated Integrated interposer with embedded active devices
KR20160094502A (en) * 2015-01-30 2016-08-10 주식회사 심텍 Chip embedded type printed circuit board and method of manufacturing the same and stack package using the same
CN110838266A (en) * 2019-11-20 2020-02-25 江苏上达电子有限公司 High-resolution dot-matrix electronic driving substrate design method based on embedded transistors
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JP3421179B2 (en) * 1995-09-28 2003-06-30 株式会社日立国際電気 Element composite mounted circuit board
JP4343777B2 (en) 2004-06-16 2009-10-14 大日本印刷株式会社 Electronic component built-in wafer

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Publication number Priority date Publication date Assignee Title
WO2015130680A1 (en) * 2014-02-28 2015-09-03 Qualcomm Incorporated Integrated interposer with embedded active devices
US9510454B2 (en) 2014-02-28 2016-11-29 Qualcomm Incorporated Integrated interposer with embedded active devices
KR20160094502A (en) * 2015-01-30 2016-08-10 주식회사 심텍 Chip embedded type printed circuit board and method of manufacturing the same and stack package using the same
KR20200134596A (en) * 2019-05-22 2020-12-02 한국전자기술연구원 Semiconductor package with embedded passive device and manufacturing method thereof
US11538770B2 (en) 2019-05-22 2022-12-27 Korea Electronics Technology Institute Semiconductor package including passive device embedded therein and method of manufacturing the same
CN110838266A (en) * 2019-11-20 2020-02-25 江苏上达电子有限公司 High-resolution dot-matrix electronic driving substrate design method based on embedded transistors
CN110910768A (en) * 2019-11-29 2020-03-24 Tcl移动通信科技（宁波）有限公司 Display device

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