KR20130015048A - Display substrate, display panel and display device - Google Patents

Abstract

PURPOSE: A display substrate, a display panel, and a display device are provided to implement a high penetration ratio by forming a single domain in each pixel area through a lower electrode and an upper electrode. CONSTITUTION: A first pixel cell of a display panel(100) includes a first upper electrode and a first lower electrode. A second pixel of the display panel includes a second lower electrode and a second upper electrode. A gamma voltage generator(12) generates a first and a second gamma reference voltage group. A control unit(16) outputs first and second pixel data corresponding to a first and a second pixel cell. A data driving unit(14) converts the first and the second pixel data into a first and a second pixel voltage. [Reference numerals] (12) Gamma voltage generator; (14) Data driving unit; (16) Control unit; (18) Gate driving unit

Description

Display Board, Display Panel, and Display Device {DISPLAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display substrate, a display panel, and a display device, and more particularly, to a display substrate, a display panel, and a display device capable of improving transmittance, viewing angle, and visibility.

In general, a liquid crystal display device forms a liquid crystal layer between two insulating substrates on which a pair of field generating electrodes are formed, and applies a voltage to the field generating electrodes to rearrange the liquid crystal molecules of the liquid crystal layer to pass through the liquid crystal layer. It is a device to display a desired image by adjusting the light transmittance.

The most common structure of a liquid crystal display device is a twisted nematic (TN) mode display device in which a pair of field generating electrodes are provided on two insulating substrates facing each other. The liquid crystal display of the TN mode had a narrow viewing angle. Accordingly, liquid crystal display devices of various modes have been developed to secure a wide viewing angle. For example, a liquid crystal display device of a plane to line switching (PLS) mode may be used.

In the liquid crystal display of the PLS mode, a pair of field generating electrodes, for example, a pixel electrode and a common electrode, are insulated from each other on a substrate (for example, an array substrate) on which thin film transistors, which are switching elements, are formed. Displaying an image by adjusting the transmittance of light of the liquid crystal layer by liquid crystal particles oriented along a fringe field organically between common electrodes.

The liquid crystal display including the PLS mode forms a domain according to the direction of electric field generation. The PLS mode liquid crystal display has the advantage of high light transmittance in a 1-domain structure, Accordingly, there is a problem that a color shift occurs and a viewing angle is lowered. In order to improve this problem, a multi-domain method of forming two or more domains in one pixel has been proposed, but there is a problem in that transmittance is reduced due to the texture of the boundary region between domains.

One object of the present invention is to provide a display device capable of improving viewing angle and visibility with high transmittance.

Another object of the present invention is to provide a display substrate capable of improving viewing angle and visibility with high transmittance.

Still another object of the present invention is to provide a display panel capable of improving viewing angle and visibility with high transmittance.

A display device for achieving the above object of the present invention includes a display panel, a gamma voltage generator, a controller, and a data driver. The display panel includes a first pixel cell including a first lower electrode and a first upper electrode overlapping the first lower electrode and having a first slit pattern, and disposed in a first direction of the first pixel cell. A second pixel cell including a lower electrode and a second upper electrode overlapping the second lower electrode and having a second slit pattern extending in a direction different from an extending direction of the first slit pattern; And a first gate line extending in a second direction and disposed between the first pixel cell and the second pixel cell. The gamma voltage generator generates a first gamma reference voltage set and a second gamma reference voltage set having a voltage level different from that of the first gamma reference voltage set. The controller outputs first and second pixel data corresponding to the first and second pixel cells, respectively. The data driver converts the first pixel data into a first pixel voltage having a corresponding analog type based on the first gamma reference voltage set, and outputs the second pixel data based on the second gamma reference voltage set. Converts to a second pixel voltage in analog form and outputs the same.

In one embodiment, the controller is configured to process an externally provided image signal to output the first and second pixel data, and to share a gamma selection signal for controlling selection of the first and second gamma reference voltage sets. The data driver includes a gamma voltage selector configured to select the first gamma reference voltage set or the second gamma reference voltage set according to the gamma selection signal.

In one embodiment, the controller is configured to process an externally provided image signal to output the first and second pixel data, and to share a gamma selection signal for controlling selection of the first and second gamma reference voltage sets. The gamma voltage generator selectively outputs the first gamma reference voltage set or the second gamma reference voltage set according to the gamma selection signal.

In this case, the gamma voltage generator may include a first gamma part, a second gamma part, and a gamma voltage selector. The first gamma unit includes a first resistor string and generates the first gamma reference voltage set using an externally provided power supply voltage. The second gamma part includes a second resistor row different from the first resistor row, and generates the second gamma reference voltage set using the power supply voltage. The gamma voltage selector selectively outputs the first gamma reference voltage set or the second gamma reference voltage set among the first and second gamma reference voltage sets according to the gamma selection signal.

In one embodiment, the first and second gamma reference voltage sets have different gamma values.

In an embodiment, the extending direction of the first slit pattern and the extending direction of the second slit pattern may have a symmetrical structure with respect to the first gate line.

The display panel may further include a first data line extending in the first direction to cross the first gate line and connected to at least one of the first and second pixel cells. .

In an embodiment, the first and second pixel cells operate sequentially, and the selection period of the first and second gamma reference voltage sets may be the same as the operation period of the first and second pixel cells.

According to another aspect of the present invention, a display substrate includes an insulating substrate having a first pixel region and a second pixel region disposed in a first direction of the first pixel region, and a first direction on the insulating substrate. First and second gate lines extending in an intersecting second direction and arranged parallel to each other with the first and second pixel regions interposed therebetween, a first lower electrode formed in each of the first and second pixel regions; A second lower electrode, a first upper electrode having a first slit pattern overlapping the first lower electrode in the first pixel region and extending in a third direction different from the first and second directions, and the second A second upper electrode overlapping the second lower electrode in the pixel area, the second upper electrode having a second slit pattern extending in a fourth direction different from the first to third directions, connected to the first gate line, and the first pixel; A first switching element disposed in the region, And a second switching element connected to the second gate line and disposed in the second pixel area.

The display device may further include a first data line intersecting the first and second gate lines and disposed on one side of the first and second pixel areas, wherein the first and second switching elements are configured to be connected to the first and second gate lines. It can be connected to a data line.

The first switching device may further include first and second data lines that cross the first and second gate lines and are disposed to be parallel to each other with the first and second pixel regions interposed therebetween. May be connected to the first data line, and the second switching element may be connected to the second data line.

In example embodiments, the first switching device may be electrically connected to the first upper electrode, and the second switching device may be electrically connected to the second upper electrode.

In example embodiments, the first switching element may be electrically connected to the first lower electrode, and the second switching element may be electrically connected to the second lower electrode.

In an embodiment, the first upper electrode and the second upper electrode may have an integrated structure connected to each other, and the first and second slit patterns may be connected to each other.

In example embodiments, the first and second upper electrodes may be formed on an insulating substrate, and the first and second pixel regions may further include an alignment layer having the same alignment direction in each of the first and second pixel regions, wherein the alignment direction of the alignment layer is It may be in the first direction or the second direction.

In example embodiments, the second direction may be perpendicular to the first direction, and the third and fourth directions may be symmetrical with respect to the first gate line.

The insulating substrate may further include a third pixel region disposed in the first direction of the second pixel region, extending in the second direction on the insulating substrate, and the second gate line and the second pixel region. A third gate line disposed between the third pixel regions, a third lower electrode formed in the third pixel region, and a third overlapping with the third lower electrode in the third pixel region and extending in the third direction The display device may further include a third upper electrode having a slit pattern, and a third switching element connected to the third gate line and adjacent to the third gate line and disposed in the third pixel region.

A display panel for achieving another object of the present invention described above includes a display substrate, an opposing substrate and a liquid crystal layer. The display substrate may include an insulating substrate having a first pixel region and a second pixel region disposed in a first direction of the first pixel region, and extending in a second direction crossing the first direction on the insulating substrate. First and second gate lines disposed to be parallel to each other with the first and second pixel regions interposed therebetween, a first lower electrode and a second lower electrode formed in each of the first and second pixel regions, and the first pixel A first upper electrode overlapping the first lower electrode in an area and having a first slit pattern extending in a third direction different from the first and second directions, and overlapping the second lower electrode in the second pixel area A second upper electrode having a second slit pattern extending in a fourth direction different from the first to third directions, a first switching element connected to the first gate line and disposed in the first pixel region; Is connected to the second gate line and It includes a second switching element disposed in the second pixel region. The opposing substrate faces the display substrate and includes a light blocking pattern overlapping the first and second gate lines, the first and second data lines, and the first and second switching elements. The liquid crystal layer is interposed between the display substrate and the counter substrate.

In example embodiments, the insulating substrate may further include a third pixel region disposed in the first direction of the second pixel region. The display substrate may further include a third gate line extending in the second direction and disposed between the second gate line and the third pixel region, and a third lower portion disposed in the third pixel region on the insulating substrate. A third upper electrode having an electrode, a third upper electrode overlapping the third lower electrode and extending in the third direction, and a third switching electrically connected to the third gate line and formed in the third pixel region The device may further include.

In example embodiments, the width of the light blocking pattern overlapping between the second pixel area and the third pixel area based on the first direction may extend the second and third gate lines at one end of the second switching device. It may be a structure narrower than the width to the other end of the third switching device on the opposite side.

According to the display substrate, the display panel, and the display device of the present invention, each pixel region is formed of a single domain by the lower electrode and the upper electrode formed in each of the pixel regions, thereby achieving high transmittance. At the same time, different domains are formed between adjacent pixel regions, and particularly, domains that are symmetrical to each other can be improved, thereby improving viewing angle and visibility, which are advantages of the multi-domain. Therefore, in the small size display device in which the multi-domain formation is difficult due to deterioration of the transmittance characteristic, the effect of the multi-domain can be derived to improve the viewing angle and visibility and the transmittance.

In addition, the gate lines may be arranged in units of two pixel regions having different domains, thereby concentrating light blocking regions by the gate lines, thereby improving horizontal line visibility problems caused by luminance differences between different domains. Can be.

In addition, in the driving of the first and second pixel cells having different single domains, different levels of gamma reference voltages are used to use pixel voltages of different levels, so that horizontal lines generated due to different domains between adjacent pixels are used. Visibility problems can be improved.

1 is a schematic structural diagram of a display device according to Embodiment 1 of the present invention.
FIG. 2 is a schematic configuration diagram of the data driver shown in FIG. 1.
3A is a plan view illustrating the display panel illustrated in FIG. 1.
3B is a cross-sectional view taken along the line II ′ of FIG. 3A.
4 is a schematic structural diagram of a display device according to a second exemplary embodiment of the present invention.
FIG. 5 is a schematic diagram of a gamma voltage generator illustrated in FIG. 4.
FIG. 6 is a schematic configuration diagram of the data driver shown in FIG. 4.
7 is a plan view illustrating a display panel of a display device according to a third exemplary embodiment of the present invention.
8 is a plan view illustrating a display panel of a display device according to a fourth exemplary embodiment of the present invention.
9 is a plan view illustrating a display panel of a display device according to a fifth exemplary embodiment of the present invention.
10 is a plan view illustrating a display panel of a display device according to a sixth exemplary embodiment of the present invention.
11A is a plan view illustrating a display panel according to a seventh exemplary embodiment of the present invention.
FIG. 11B is a cross-sectional view taken along the line II-II of FIG. 11A.
12 is a plan view illustrating a display panel of a display device according to an eighth embodiment of the present invention.
13 is a plan view illustrating a display panel of a display device according to a ninth embodiment of the present invention.
14 is a plan view illustrating a display panel of a display device according to a tenth exemplary embodiment of the present invention.
15 is a plan view illustrating a display panel of a display device according to an eleventh embodiment of the present invention.
16A and 16B are equivalent circuit diagrams and plan views illustrating a display panel of a display device according to a twelfth embodiment of the present invention.
17 is a plan view illustrating a light shielding pattern included in an opposing substrate in a display panel of a twelfth embodiment of the present invention.
18 is a plan view illustrating a display panel of a display device according to a thirteenth embodiment.
19A and 19B are equivalent circuit diagrams and plan views illustrating a display panel of a display device according to a twelfth embodiment of the present invention.
20 is a plan view illustrating a display panel of a display device according to a fifteenth embodiment of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

As the inventive concept allows for various changes and numerous modifications, particular embodiments will be illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions describing relationships between components, such as "between" and "immediately between" or "adjacent to" and "directly adjacent to", should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprise", "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is practiced, and that one or the same. It is to be understood that the present invention does not exclude in advance the possibility of the presence or addition of other features or numbers, steps, operations, components, parts or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant description of the same components is omitted.

Example 1

1 is a schematic configuration diagram of a display device according to a first exemplary embodiment of the present invention, and FIG. 2 is a schematic configuration diagram of a data driver shown in FIG. 1.

1 and 2, the display device 10 includes a display panel 100, a gamma voltage generator 12, and a data driver 14. The gamma voltage generator 12 and the data driver 14 are drivers for driving the display panel 100. The display device 10 further includes a controller 16 and a gate driver 18 as a driver for driving the display panel 100. The driving unit drives the display panel 100 to display an image signal provided from an image source such as an external graphic device.

In addition, although not shown, the display device 10 further includes a backlight assembly that radiates light to the display panel 100. The backlight assembly is typically disposed on the back of the display panel 100. A traveling direction of light emitted from the backlight assembly to the display panel 100 may be defined as a display direction of an image.

The display panel 100 includes a display substrate (or lower substrate), an opposing substrate (or upper substrate), and a liquid crystal layer. The opposing substrate opposes the display substrate. The liquid crystal layer is interposed between the display substrate and the counter substrate. In the equivalent circuit, the display panel 100 includes a plurality of pixel cells PX and a plurality of signal lines GL and DL connected to the pixel cells PX. For example, the plurality of pixel cells PX may include a first pixel cell PX1, a second pixel cell PX2, a third pixel cell PX3, and a fourth pixel cell PX4. In the plan view, the second pixel cell PX2 may be defined as a pixel cell disposed in the first direction D1 of the first pixel cell PX1. Here, the first direction D1 may be a vertical direction (or a column direction). In addition, the third and fourth pixel cells PX3 and PX4 may be defined as pixel cells disposed in the second direction D2 of the first and second pixel cells PX1 and PX2, respectively. Here, the second direction D2 may be a direction crossing the first direction D1, for example, a direction perpendicular to the first direction D1, and may be a horizontal direction (or a row direction). That is, the pixel cells PX may have a structure arranged in a matrix form.

The signal lines GL and DL include gate lines GL and data lines DL that intersect the gate lines GL. For example, the signal lines may include first and second gate lines GL1 and GL2 and first and second data lines DL1 and DL2. The first and second gate lines GL1 and GL2 may extend in the second direction D2 and may be parallel to each other. The first and second data lines DL1 and DL2 extend each other while extending in a direction crossing the first and second gate lines GL1 and GL2, for example, a first direction D1 crossing the second direction D2. Can be side by side. The signal lines are connected to the pixel cells PX. For example, each of the pixel cells PX may be connected to one gate line GL and one data line DL.

Although not shown in detail, each of the pixel cells PX includes a pair of field forming electrodes and a liquid crystal layer. The pair of field forming electrodes includes a lower electrode and an upper electrode overlapping the lower electrode, and the upper electrode has a slit pattern for domain formation. The pixel cells PX form a domain through an electric field according to a slit pattern formed at each upper electrode. In detail, the first and second pixel cells PX1 and PX2 have different domains. For example, domains of the first pixel cell PX1 and the second pixel cell PX2 may be symmetrical with respect to the gate line GL. In other words, the domains of the first and second pixel cells PX1 and PX2 may be symmetrical with respect to each other with respect to the second direction D2, which is an extension direction of the gate line GL. In addition, the third and fourth pixel cells PX3 and PX4 have different domains. For example, the structures may be symmetrical with respect to the gate line GL or the second direction D2. In this case, the domains of the third and fourth pixel cells PX3 and PX4 may be the same as the domains of the first and second pixel cells PX1 and PX2, respectively. That is, the pixel cells PX in the pixel cells PX disposed along the second direction D2, which is the extending direction of the gate line GL, have the same domain and have a first extension direction of the data line DL. Adjacent pixel cells PX arranged along the direction D1 may have a structure having different domains.

The structure of the display panel 100 will be described in more detail with reference to the accompanying drawings.

The gamma voltage generator 12 generates gamma reference voltage sets VREF1 and VREF2 that are based on a substantially driving voltage (for example, a gray voltage) applied to the pixel cells PX of the display panel 100. In particular, the gamma voltage generator 200 generates a first gamma reference voltage set VREF1 and a second gamma reference voltage set VREF2. The first and second gamma reference voltage sets VREF1 and VREF2 have different voltage levels. For example, the first gamma reference voltage set VREF1 is a set of voltages according to a first gamma curve having a first gamma value, and the second gamma reference voltage set VREF2 has a second gamma value different from the first gamma value. It may be a set of voltages according to the second gamma curve. The first and second gamma values may be values for compensating for deviations according to domains of the first and second pixel cells PX1 and PX2, respectively. The first gamma reference voltage set VREF1 has a voltage level for compensation driving of the first pixel cell PX1, and the second gamma reference voltage set VREF2 has a voltage for compensation driving of the second pixel cell PX2. May have a level. Also, since the pixel cells PX have the same domain in the second direction D2 and have different domains in the first direction D1, the first and second gamma reference voltage sets ( VREF1 and VREF2 may be a voltage set for different application of pixel cells PX along the first direction D1.

Although not shown in detail, the gamma voltage generator 12 may include a first gamma part for generating the first gamma reference voltage set VREF1 and a second gamma part for generating the second gamma reference voltage set VREF2. Can be. The first gamma part includes a first resistor row for voltage distribution, the second gamma part includes a second resistor row for voltage distribution, and the first and second resistor rows include different resistors. The first and second gamma units are each supplied with a power supply voltage for generating a gamma reference voltage from a power generator (not shown), and divide the voltages to generate the first and second gamma reference voltage sets VREF1 and VREF2. The gamma voltage generator 12 outputs the generated first gamma reference voltage set VREF1 and the second gamma reference voltage set VREF2 to the data driver 300.

The data driver 14 receives the pixel data DATA ′ of the pixel cells PX and the control signals CONT1 and GSEL from the controller 16. The data driver 14 converts the pixel data DATA 'into corresponding analog pixel voltages based on the first and second gamma reference voltage sets VREF1 and VREF2 and converts the pixel data DATA ′ into corresponding pixel voltages through the data line DL. Output to cells PX. In this case, the first pixel data corresponding to the first pixel cell PX1 is converted into a corresponding first pixel voltage based on the first gamma reference voltage set VREF1 and output. In contrast, the second pixel data corresponding to the second pixel cell PX2 is converted into a corresponding second pixel voltage based on the second gamma reference voltage set VREF2 and output. The pixel data DATA ′ of the pixel cells PX provided by the controller 400 are in digital form. Therefore, the data driver 14 converts the pixel data DATA ′ in the digital form into a corresponding pixel voltage in the analog form and outputs the same.

The control signals CONT1 and GSEL include a data control signal CONT1 and a gamma selection signal GSEL. The data control signal CONT1 applies a corresponding pixel voltage to the horizontal synchronization signal STH and data line DL informing transmission of data to the pixel cells PX in a row unit arranged along the second direction D2. The data signal includes a load signal LOAD and a data clock signal DCLK for timing synchronization. In addition, the data control signal CONT1 may include a polarity inversion signal for inverting the polarity of the pixel voltage. The gamma selection signal GSEL is a signal for controlling selection of the first and second gamma reference voltage sets VREF1 and VREF2. The gamma selection signal GSEL is a control signal for instructing selection of the first gamma reference voltage set VREF1 or the second gamma reference voltage set VREF2. Since the first and second gamma reference voltage sets VREF1 and VREF2 are used to convert the pixel data corresponding to the first and second pixel cells PX1, the gamma selection signal GSEL may be the pixel cells PX in row units. It may have the same period as the horizontal synchronization signal (STH) that informs the data transmission. That is, the first and second pixel cells PX1 and PX2 disposed along the first direction are sequentially operated, and the selection period of the first and second gamma reference voltage sets is selected from the first and second pixel cells ( Same as the operation cycle of PX1, PX2).

The data driver 14 includes a shift register 14a, a latch 14b, a digital-to-analog converter 14c, a buffer 14d, and a gamma voltage selector 14e. The shift register 14a receives the horizontal simultaneous signal STH and the data clock signal DCLK. When the horizontal simultaneous signal STH is applied, the shift register 14a sequentially receives the input pixel data DATA 'according to the data clock signal DCLK. Shift to provide the latch 14b. The latch 14b stores the pixel data DATA ′ provided from the shift register 14a and simultaneously converts the pixel data DATA ′ in row units stored in response to the load signal LOAD (digital analog converter). 14c). The digital-to-analog converter 14c corresponds to an analog form corresponding to the pixel data DATA 'based on the first gamma reference voltage set VREF1 or the second gamma reference voltage set VREF2 provided by the gamma voltage selector 14e. It converts into pixel voltage of and outputs it to the buffer 14d. Although not shown, the digital-to-analog converter 14c may receive a polarity inversion signal and output a pixel voltage whose polarity is inverted according to the polarity inversion signal. The buffer 14d outputs the pixel voltages provided from the digital-to-analog converter 14c to the data lines DL and provides them to the corresponding pixel cells PX. The gamma voltage selector 14e receives the first and second gamma reference voltage sets VREF1 and VREF2 together from the gamma voltage generator 12, and according to the gamma selection signal GSEL, the first and second gamma references Any one of the voltage sets VREF1 and VREF2 is selected and output to the digital-to-analog converter 14c. As a result, the gamma voltage selector 14e selects and outputs the first gamma reference voltage set VREF1 in the driving period of the first pixel cell PX1 and outputs the second gamma voltage in the driving period of the second pixel cell PX2. The gamma reference voltage set VREF2 is selected and output. The gamma voltage selector 14e may include a multiplexer that outputs one of a plurality of inputs.

The controller 16 receives the image signal DATA and the synchronization signals CONT from an external image source such as a graphic device. The synchronization signals CONT include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock signal MCLK. The controller 16 generates and outputs a gamma selection signal GSEL, a data control signal CONT1, and a gate control signal CONT2 for driving the display panel 100 based on the input synchronization signals CONT. . The data control signal CONT1 and the gate control signal CONT2 are output to the data driver 14 and the gate driver 18, respectively. The pixel data of the pixel cells PX output to the data driver 14 may include pixel data of three colors corresponding to the red pixel, the green pixel, and the blue pixel.

The gate driver 18 sequentially outputs gate signals for activating the gate lines GL in response to the gate control signal CONT2 provided from the controller 16. That is, by sequentially outputting the gate signals, the pixel cells PX connected thereto are sequentially activated to prepare the pixel voltages to be ready for application. The gate control signal CONT2 includes a watch start signal STV for notifying the start of scanning and a clock signal CLK for controlling the output time of the gate-on voltage Von. The gate driver 18 receives a gate on voltage VON and a gate off voltage VOFF for generating a gate signal from a power generator (not shown).

Hereinafter, the display panel 100 will be described in more detail.

3A is a plan view illustrating the display panel illustrated in FIG. 1, and FIG. 3B is a cross-sectional view taken along the line II ′ of FIG. 3A.

3A and 3B, the display panel 100 includes a display substrate 110, an opposite substrate 120, and a liquid crystal layer 130. The opposing substrate 120 faces the display substrate 110, and the liquid crystal layer 130 is interposed between the display substrate 110 and the opposing substrate 120. The liquid crystal layer 130 may include liquid crystals LC. The display panel 100 may further include a first polarizer 102 and a second polarizer 104.

The display substrate 110 includes a first insulating substrate 111, a plurality of signal lines formed on the first insulating substrate 111, and a plurality of field forming electrodes for forming an electric field. The display substrate 110 may further include switching elements SW1, SW2, SW3, and SW4 for operation control of the field forming electrodes and a first alignment layer 112 for initial alignment of the liquid crystal.

The first insulating substrate 111 is made of a transparent insulating material such as glass or plastic, and has a plurality of pixel areas PA1, PA2, PA3, and PA4 corresponding to the pixel cells PX. For example, the plurality of pixel areas PA1, PA2, PA3, and PA4 may include the first pixel area PA1, the second pixel area PA2, the third pixel area PA3, and the fourth pixel area PA4. It may include. The first to fourth pixel areas PA1, PA2, PA3, and PA4 are defined as regions for forming the first to fourth pixel cells PX1, PX2, PX3, and PX4 described with reference to FIGS. 1 and 2, respectively. The second pixel area PA2 may be defined as a pixel area disposed in the first direction D1 of the first pixel area PA1. Here, the first direction D1 may be a vertical direction (or a column direction). In addition, the third pixel area PA3 may be defined as a pixel area disposed in the second direction D2 of the first pixel area PA1, and the fourth pixel area PA4 is the second pixel area PA2. It may be defined as a pixel area disposed in the second direction D2 of. That is, the first to fourth pixel areas PA1, PA2, PA3, and PA4 are arranged in a matrix form. Here, the second direction D2 may be a horizontal direction (or a row direction) in a direction perpendicular to the first direction D1.

The signal lines may include a first gate line GL1 and a second gate line GL2, and a first data line DL1 and a second data line DL2. The first and second gate lines GL1 and GL2 may extend in the second direction D1. The first gate line GL1 may be disposed between the first pixel area PA1 and the second pixel area PA2 and between the third pixel area PA3 and the fourth pixel area PA3 and PA4. The second gate line GL2 is disposed in the first direction D1 of the first gate line GL1. For example, the second gate line GL2 may be disposed in parallel with the first gate line GL1 with the second and fourth pixel regions PA2 and PA4 interposed therebetween. The first and second data lines DL1 and DL2 may extend in the first direction D1. The first and second data lines DL1 and DL may extend in the first direction D1 in a zigzag form, and the zigzag form may be formed along the shapes of the field forming electrodes.

Although not illustrated in the drawing, the display substrate 100 may further include pad portions (not shown) formed at one end of the first and second gate lines GL1 and GL2. The pad portions are electrically connected to the gate driver 18.

The field forming electrodes include first to fourth lower electrodes 113_1, 113_2, 113_3 and 113_4 and first to fourth upper electrodes 114_1, 114_2, 114_3 and 114_4. The first to fourth lower electrodes 113_1, 113_2, 113_3 and 113_4 and the first to fourth upper electrodes 114_1, 114_2, 114_3 and 114_4 may be transparent electrodes formed of a transparent conductive material. Alternatively, the first to fourth lower electrodes 113_1, 113_2, 113_3, and 113_4 may be opaque electrodes.

The first lower electrode 113_1 is formed in the first pixel area PA1. The first lower electrode 113_1 may have a plate shape. The outer periphery of the first lower electrode 113_1 may partially overlap the first gate line GL1, the first and second data lines DL1 and DL2.

The second lower electrode 113_2 is formed in the second pixel area PA2. The second lower electrode 113_2 may have a plate shape. The outer periphery of the second lower electrode 113_2 may partially overlap the first and second gate lines GL1 and GL2 and the first and second data lines DL1 and DL2.

The first lower electrode 113_1 and the second lower electrode 113_2 may be integrally formed. Ends of the first and second lower electrodes 113_1 and 113_2 may be connected to each other in a region where the first lower electrode 113_1 and the second lower electrode 113_2 are adjacent to each other. For example, the first lower electrode 113_1 and the second lower electrode 113_2 may be connected to each other on the first gate line GL1. The first lower electrode 113_1 and the second lower electrode 113_2 may be common electrodes to which a common voltage is applied. On the contrary, the first lower electrode 113_1 and the second lower electrode 113_2 are spaced apart from each other and physically separated from each other, and are separated (eg, island tongue) structures receiving a common voltage through a separate common electrode line (not shown). It may be.

The third lower electrode 113_3 is formed in the third pixel area PA3, and the fourth lower electrode 113_4 is formed in the fourth pixel area PA4. As in the case of the first and second lower electrodes 113_1 and 113_2, the third and fourth lower electrodes 113_3 and 113_4 may have an integrated structure in which ends thereof are connected to each other. In contrast, the third and fourth lower electrodes 113_3 and 113_4 may have independent structures, and may have a structure in which a common voltage is applied through a separate common electrode line (not shown). Each of the third and fourth lower electrodes 113_3 and 113_4 may have substantially the same structure as the first and second lower electrodes 113_1 and 113_2.

As described above, the first and second lower electrodes 113_1 and 113_2 have an integrated structure, and the third and fourth lower electrodes 113_3 and 113_4 have an integrated structure, for example, a stripe structure. Alternatively, the first to fourth lower electrodes 113_1, 113_2, 113_3, and 113_4 may have an integral structure as a whole. When the first to fourth lower electrodes 113_1, 113_2, 113_3, and 113_4 have an integral structure, the electrode of the integral structure may include a region other than the switching elements SW1, SW2, SW3, and SW4 and the contact region, or at least It is formed in an area excluding the contact area of the switching elements SW1, SW2, SW3, and SW4.

The first upper electrode 114_1 is formed in the first pixel area PA1 and is insulated from and overlapped with the first lower electrode 113_1. The first upper electrode 114_1 has a first slit pattern 115_1 for forming a domain of the liquid crystal layer. The first slit pattern 115_1 extends in a third direction different from the first and second directions D1 and D2. The third direction may be a direction inclined at a predetermined angle with respect to the first and second directions D1 and D2. The slits of the first slit pattern 115_1 may be arranged in parallel at equal intervals. The first upper electrode 114_1 may be electrically connected to the first switching element SW1.

The first switching element SW1 is electrically connected to the first gate line GL1 and the first data line DL1. The first switching element SW1 is disposed in the first pixel area PA1. The first switching element SW1 is disposed on the gate electrode GE connected to the first gate line GL1, the source electrode SE connected to the first data line DL1, and on the semiconductor layer 116a and the semiconductor layer 116a. It may include an active pattern AP including an ohmic contact layer 116b formed in the drain electrode and a drain electrode DE spaced apart from the source electrode SE. The drain electrode DE may be in contact with the first upper electrode 114_1 so that the first upper electrode 114_1 may be electrically connected to the first switching element SW1. The first upper electrode 114_1 may be a pixel electrode to which the pixel voltage is applied from the first data line DL1 according to the switching operation of the first switching element SW1.

Each of the second to fourth upper electrodes 114_2, 114_3, and 114_4 is substantially the same as the first upper electrode 114_1 except for the formation position and the extension direction of the slit pattern, and the second to fourth switching elements SW2. , SW3 and SW4 are substantially the same as the first switching element SW1 except for an electrical connection. Therefore, the following description will be briefly focused on differences.

The second upper electrode 114_2 is formed in the second pixel area PA2 and is insulated from and overlapped with the second lower electrode 113_2. The second upper electrode 114_2 has a second slit pattern 115_2 for forming a domain of the liquid crystal layer. The second slit pattern 115_2 extends in the fourth direction, and the fourth direction is different from the first and second directions D1 and D2, and is also different from the third direction. For example, the fourth direction may be a direction symmetrical to the third direction with respect to the first gate line GL1. That is, the fourth direction may be a direction symmetrical with the third direction with respect to the second direction. The slits of the second slit pattern 115_2 are arranged in parallel at equal intervals. The second upper electrode 114_2 is electrically connected to the second switching element SW2 electrically connected to the second gate line GL2 and the first data line DL1. The second upper electrode 114_2 is connected to the first data line DL1 and receives a pixel voltage for displaying an image from the first data line DL1 according to the switching operation of the second switching element SW2. Can be. The second upper electrode 114_2 is connected to the second switching element SW2.

The second switching element SW2 is electrically connected to the second gate line GL2 and the first data line DL1. The second switching element SW2 is disposed in the second pixel area PA2. The second upper electrode 114_2 may be a pixel electrode electrically connected to the second switching element SW2 to receive a pixel voltage from the first data line DL1 according to a switching operation of the second switching element SW2. have.

The sides of each of the first and second upper electrodes 114_1 and 114_2 adjacent to the first and second data lines DL1 and DL2 extend in the extension direction of the first and second slit patterns 115_1 and 115_2. Sides of the first upper electrode 114_1 may be parallel to the first slit pattern 115_1, and sides of the second upper electrode 114_2 may be formed parallel to the second slit pattern 115_2.

The second data line DL2 may have a bent structure. In the overall display substrate 110, the second data line DL2 may have a zigzag pattern in which a bending structure is repeated along the first direction D1. In this case, the second data line DL2 may include a portion extending in parallel with the first slit pattern 115_1 and the second slit pattern 115_2. In detail, the second data line DL1 includes a portion extending between the first and third pixel areas PA1 and PA3 in the same third direction as that of the first slit pattern 115_1. And a portion extending between the fourth pixel areas PA2 and PA4 in the same fourth direction as that of the second slit pattern 115_2.

In addition, the first data line DL1 may have the same bending structure as the second data line DL2. The first data line DL1 may have a zigzag pattern in which a bending structure is repeated along the first direction D1. The first and second data lines DL1 and DL2 are disposed with the first and second pixel areas PA1 and PA2 interposed therebetween. Since the first data line DL1 has the same shape as the second data line DL2, the first and second data lines DL1 and DL2 may be parallel to each other.

Sides of the first and second upper electrodes 114_1 and 114_2 adjacent to the first and second data lines DL1 and DL2 may be parallel to the first and second data lines DL1 and DL2.

The third upper electrode 114_3 is formed in the third pixel area PA3 and overlaps the third lower electrode 113_3. The third upper electrode 114_3 includes a third slit pattern 115_3 extending in the same direction as the first slit pattern 115_1. That is, the third upper electrode 114_3 includes a third slit pattern 115_3 extending in the third direction. The third upper electrode 114_3 is connected to the third switching element SW3.

The third switching device SW3 is electrically connected to the first gate line GL1 and the second data line DL2. The third switching element SW3 is disposed in the third pixel area PA3. The third upper electrode 114_3 may be a pixel electrode electrically connected to the third switching element SW3 to receive the pixel voltage from the second data line DL2 according to the switching operation of the third switching element SW3. have.

The fourth upper electrode 114_4 is formed in the fourth pixel area PA4 and overlaps the fourth lower electrode 113_4. The fourth upper electrode 114_4 includes a fourth slit pattern 115_4 extending in the same direction as the second slit pattern 115_2. That is, the fourth upper electrode 114_4 includes a fourth slit pattern 115_4 extending in the fourth direction. The fourth upper electrode 114_4 is connected to the fourth switching device SW4.

The fourth switching device SW4 is electrically connected to the second gate line GL2 and the second data line DL2. The fourth switching element SW4 is disposed in the fourth pixel area PA4. The fourth upper electrode 114_4 may be a pixel electrode electrically connected to the fourth switching element SW4 to receive the pixel voltage from the second data line DL2 according to the switching operation of the fourth switching element SW4. have.

Accordingly, the third upper electrode 114_3 forms a domain of the liquid crystal layer in the same direction as the first upper electrode 114_1, and the fourth upper electrode 114_4 is in the same direction as the second upper electrode 114_2. To form a domain. In other words, the first to fourth upper electrodes 114_1, 114_2, 114_3, and 114_4 have the same domain on a row basis, and have different domains between adjacent rows in the column direction.

The first alignment layer 112 is formed on the first insulating substrate 111 on which the first to fourth upper electrodes 114_1, 114_2, 114_3, and 114_4 are formed. The first alignment layer 112 is processed so that the alignment directions in the first to fourth pixel regions PA1, PA2, PA3, and PA4 are the same, so that the surface orientations of the first alignment layer 112 are different from each other in plan view. May be the same. That is, the first alignment layer 112 is processed in a single alignment direction with respect to the first to fourth pixel areas PA1, PA2, PA3, and PA4. This means that the first alignment layer 112 is formed on the entire surface of the first insulating substrate 111 and has a single alignment direction with respect to the entire surface of the first insulating substrate 111. Here, the alignment direction of the first alignment layer 112 may be defined as a direction in which the first alignment layer 112 aligns the liquid crystal. The alignment direction of the first alignment layer 112 may be formed through a rubbing process or a photo alignment process. The alignment direction of the first alignment layer 112 may be formed in various ways.

The alignment direction of the first alignment layer 112 may have a first direction D1 or a second direction D2. Since the first alignment layer 112 has an alignment direction of the first direction D1 or the second direction D2 with respect to the first to fourth pixel regions PA1, PA2, PA3, and PA4, the first and the first alignment layers 112 may be formed. The two slit patterns 115_1 and 115_2 may be balanced in the directions. Therefore, the first pixel area PA1 and the second pixel area PA2 may be driven in a direction in which they are symmetrical with each other, and the third pixel area PA3 and the fourth pixel area PA4 are in a symmetrical direction with each other. It is possible to drive the liquid crystal. Therefore, when the display substrate 110 is used, the viewing angles in both the left and right directions as a whole may be balanced.

This manufacturing method of the display substrate 110 will be briefly described.

A gate metal layer is formed on the first insulating substrate 111, and the gate metal layer is patterned to form a gate pattern including the first and second gate lines GL1 and GL2 and the gate electrodes GE. The gate metal layer may include aluminum (Al), silver (Ag), molybdenum (Mo), chromium (Cr), or the like as the conductive metal. A gate insulating layer 117 is formed on the first insulating substrate 111 on which the gate pattern is formed. For example, the gate insulating layer 117 may be formed of silicon nitride (SiNx), silicon oxide (SiOx), or the like.

The active pattern AP is formed to overlap the gate electrode GE on the gate insulating layer 117. The active pattern AP may include a semiconductor layer 116a and an ohmic contact layer 116b formed on the semiconductor layer 116a. Subsequently, a data metal layer is formed on the insulating substrate 111 on which the active pattern AP is formed, and the data metal layer is patterned to form the first and second data lines DL1 and DL2, the source electrodes SE, and the drain electrodes. A source pattern containing (DE) is formed. The first passivation layer 118 is formed on the first insulating substrate 111 on which the source pattern is formed.

A first transparent electrode layer is formed on the first passivation layer 118 and patterned to form first and fourth lower electrodes 113_1 and 113_2 in each of the first to fourth pixel regions PA1, PA2, PA3, and PA4. , 113_3, 113_4).

Next, a second passivation layer 119 is formed on the first insulating substrate 111 on which the first to fourth lower electrodes 113_1, 113_2, 113_3, and 113_4 are formed. The second passivation layer 119 may cover the first to fourth lower electrodes 113_1, 113_2, 113_3, and 113_4.

The first and second passivation layers 118 and 119 are etched to form contact holes. A portion of the drain electrode DE is exposed through the contact hole. A second transparent electrode layer is formed and patterned on the first and second passivation layers 118 and 119 on which the contact holes are formed to form the first to fourth upper electrodes 114_1, 114_2, 114_3, and 114_4. Each of the first to fourth upper electrodes 114_1, 114_2, 114_3, and 114_4 has first to fourth slit patterns 115_1, 115_2, 115_3, and 115_4 to form a domain of the liquid crystal. The first and third slit patterns 115_1 and 115_3 formed in the first and third upper electrodes 114_1 and 114_3 respectively extend in the same third direction. In addition, the second and fourth slit patterns 115_2 and 115_4 formed in the second and fourth upper electrodes 114_2 and 114_4 respectively extend in the same fourth direction. Here, the third direction and the fourth direction may be different directions, and preferably, the third direction and the fourth direction may be symmetrical with respect to the first gate line GL1 with respect to the first gate line GL1.

A preliminary layer is formed on the first insulating substrate 111 on which the first to fourth upper electrodes 114_1, 114_2, 114_3, and 114_4 are formed, and the surface of the preliminary layer is rubbed or photoaligned in the first direction D1. As a result, the first alignment layer 112 may be formed. The surface of the preliminary membrane may be rubbed in the second direction D2. The first alignment layer 112 may have the same alignment direction in all of the first to fourth pixel areas PA1, PA2, PA3, and PA4. An orientation direction can be defined as the direction which orientates a liquid crystal. The manufacturing method of the display substrate 110 may be formed by a process sequence different from that described above, and is not necessarily limited to the method described above.

The opposing substrate 120 includes a second insulating substrate 121, a light blocking pattern BM, and color filters CF formed on the insulating substrate 121. The opposing substrate 120 may further include a second alignment layer 122 for initial alignment of the liquid crystal.

The light blocking pattern BM is formed to overlap the switching elements SW1, SW2, SW3, and SW4 and the signal lines GL1, GL2, DL1, and DL2 formed on the display substrate 110.

The color filters CF are formed to overlap each of the pixel areas PA1, PA2, PA3, and PA4 of the display substrate 110. The color filters CF may include a red filter R, a green filter G, and a blue filter B. Alternatively, the color filters CF may include other colors. Color combinations of the color filters CF may be variously applied, and the range is not limited by the color combinations of the color filters CF.

The second alignment layer 122 is formed on the second insulating substrate 120 on which the light blocking pattern BM and the color filters CF are formed. The second alignment layer 122 is formed on one surface of the second alignment layer 122 that faces the display substrate 110 and contacts the liquid crystal layer 130. The second alignment layer 122 is formed in substantially the same manner as the first alignment layer 112. In detail, the second alignment layer 122 is processed so that the alignment directions in the regions corresponding to the first to fourth pixel regions PA1, PA2, PA3, and PA4 are the same, so that the first to fourth views may be viewed in plan view. Surface orientations in areas corresponding to the four pixel areas PA1, PA2, PA3, and PA4 may be the same. That is, the second alignment layer 122 is formed to have a single alignment direction with respect to the entire surface of the second insulating substrate 121. The alignment direction of the second alignment layer 122 may be formed through a rubbing process or a photo alignment process. Here, the alignment direction may be defined as a direction in which the second alignment layer 122 aligns the liquid crystal.

The alignment direction of the second alignment layer 121 may be the same as the alignment direction of the first alignment layer 112. That is, the alignment direction of the second alignment layer 121 may be the first direction D1 or the second direction D2. For example, when the alignment direction of the first alignment layer 112 is the first direction D1, the alignment direction of the second alignment layer 121 is also the first direction D1, and the alignment direction of the first alignment layer 112 is the first direction D1. In the second direction D2, the alignment direction of the second alignment layer 122 also becomes the second direction D2.

Each of the first polarizing plate 102 and the second polarizing plate 104 is disposed on an outer surface of the display substrate 110 and the opposing substrate 120.

The first polarizing plate 102 is disposed on a lower surface of the display substrate 110, that is, on an opposite surface of the first insulating substrate 111 to be in contact with the liquid crystal layer 130. The first polarizing plate 102 has a polarization axis in the same direction as the alignment direction of the first alignment layer 112 included in the display substrate 110. For example, when the alignment direction of the first alignment layer 112 is the first direction D1, the first polarizing plate 102 has a polarization axis in the first direction D1, and the alignment direction of the first alignment layer 112 is the second direction ( D2), the first polarizing plate 102 has a polarization axis in the second direction D2.

The second polarizing plate 104 is disposed on an upper surface of the opposing substrate 120, that is, on an opposite surface of the second insulating substrate 121 that is in contact with the liquid crystal layer 130. The polarization axis of the second polarizing plate 104 is disposed perpendicular to the polarization axis of the first polarizing plate 102. Therefore, the second polarizing plate 104 has a polarization axis in a direction perpendicular to the alignment direction of the second alignment layer 122 provided on the opposing substrate 120.

In the display panel 100, the first to fourth pixel cells PX1, PX2, PX3, and PX4 are defined by field forming electrodes and liquid crystal layers formed in the first to fourth pixel areas PA1, PA2, PA3, and PA4. Can be. That is, the first pixel cell PX1 may be defined as the liquid crystal layer 130 overlapping the first lower electrode 113_1, the first upper electrode 114_1, and the first pixel area PA1. The second pixel cell PX2 may be defined as the liquid crystal layer 130 overlapping the second lower electrode 113_2, the second upper electrode 114_2, and the second pixel region PA2. The third pixel cell PX3 may be defined as the liquid crystal layer 130 overlapping the third lower electrode 113_3, the third upper electrode 114_3, and the third pixel region PA3. The fourth pixel cell PX4 may be defined as the liquid crystal layer 130 overlapping the fourth lower electrode 113_4, the fourth upper electrode 114_4, and the fourth pixel area PA4.

According to the above description, each of the first to second pixel cells PX1, PX2, PX3, and PX4 is connected to the first to fourth upper electrodes 114_1, 114_2, 114_3, and 114_4, which are one of the field forming electrodes, to form a domain. The first to fourth slit patterns 115_1, 115_2, 115_3, and 115_4 are applied, respectively. In detail, each of the first to fourth pixel cells PX1, PX2, PX3, and PX4 has a single domain, and the domain directions of the first and second pixel cells PX1 and PX2 are different from each other. And different domain directions of the fourth pixel cells PX3 and PX4. Domains of the first and second pixel cells PX1 and PX2 are symmetrical with respect to the first gate line GL1, and domains of the third and fourth pixel cells PX3 and PX4 are opposed to each other. At the same time, the alignment direction of the first alignment layer 112 is formed in a single direction as a whole with respect to the display substrate 110. As a result, the transmittance can be improved through the single domain and the viewing angle and visibility can be improved through the multi-domain.

In addition, by using different sets of gamma reference voltage sets that are the basis of driving voltages of the first pixel cell PX1 and the second pixel cell PX2 having different domains, luminance differences that may occur due to domain formation are determined. Compensate to improve the horizontal visibility problem.

Example 2

4 is a schematic configuration diagram of a display device according to a second exemplary embodiment of the present invention, FIG. 5 is a schematic configuration diagram of a gamma voltage generator illustrated in FIG. 4, and FIG. 6 is a schematic configuration diagram of a data driver illustrated in FIG. 4. Phosphorus composition diagram.

4, 5, and 6, the display device 20 includes a display panel 200, a gamma voltage generator 22, and a data driver 24. The gamma voltage generator 22 and the data driver 24 are drivers for driving the display panel 200. The display device 20 further includes a controller 26 and a gate driver 28 as a driver for driving the display panel 200. The driving unit drives the display panel 200 to display an image signal provided from an image source such as an external graphic device.

Here, the display device 20 according to the second embodiment of the present invention is substantially the same as the display device 10 described with reference to FIGS. 1 and 2 except for the gamma voltage generator 22 and the data driver 24. . Therefore, hereinafter, redundant descriptions will be omitted and briefly described based on differences.

The gamma voltage generator 22 generates gamma reference voltage sets VREF1 and VREF2 that are based on a substantially driving voltage applied to the pixel cells PX of the display panel 200, for example, a gray voltage. In particular, the gamma voltage generator 22 generates the first gamma reference voltage set VREF1 and the second gamma reference voltage set VREF2, and the first gamma reference voltage set VREF1 or the second gamma reference voltage set ( Optionally output VREF2). The first and second gamma reference voltage sets VREF1 and VREF2 have different voltage levels. For example, the first gamma reference voltage set VREF1 is a set of voltages according to a first gamma curve having a first gamma value, and the second gamma reference voltage set VREF2 has a second gamma value different from the first gamma value. It may be a set of voltages according to the second gamma curve. The first and second gamma values may be values for compensating for deviations according to domains of the first and second pixel cells PX1 and PX2, respectively. The first gamma reference voltage set VREF1 has a voltage level for compensation driving of the first pixel cell PX1, and the second gamma reference voltage set VREF2 has a voltage for compensation driving of the second pixel cell PX2. May have a level.

The gamma voltage generator 22 receives a gamma selection signal GSEL from the controller 26. The gamma selection signal GSEL is a signal for controlling selection of the first and second gamma reference voltage sets VREF1 and VREF2. The gamma selection signal GSEL is a control signal for instructing selection of the first gamma reference voltage set VREF1 or the second gamma reference voltage set VREF2. Since the first and second gamma reference voltage sets VREF1 and VREF2 are used to convert the pixel data corresponding to the first and second pixel cells PX1, the gamma selection signal GSEL may be the pixel cells PX in row units. It may have the same period as the horizontal synchronization signal (STH) that informs the data transmission. That is, the first and second pixel cells PX1 and PX2 disposed along the first direction are sequentially operated, and the selection period of the first and second gamma reference voltage sets is selected from the first and second pixel cells ( Same as the operation cycle of PX1, PX2).

The gamma voltage generator 22 includes a first gamma part 22a, a second gamma part 22b, and a gamma voltage selector 22c.

The first gamma part 22a receives a power supply voltage for generating a gamma reference voltage from a power generator (not shown), and divides the voltage to generate a first gamma reference voltage set VREF1. The first gamma part 22a includes a first resistor column made up of a plurality of resistors for voltage distribution.

The second gamma unit 22b receives the power supply voltage from a power generation unit (not shown) and divides the voltage to generate a second gamma reference voltage set VREF2. The second gamma part 22b includes a second resistor row made up of a plurality of resistors for voltage distribution. The second row of resistors is different in configuration from the first row of resistors.

The gamma voltage selector 22c receives the first and second gamma reference voltage sets VREF1 and VREF2 from the first and second gamma units 22a and 22b, respectively, and the gamma selection signal GSEL from the controller 28. ) Is provided. The gamma voltage selector 22c selects and outputs one voltage set from the first and second gamma reference voltage sets VREF1 and VREF2 according to the gamma selection signal GSEL. The voltage set selected and output by the gamma voltage selector 22c is provided to the data driver 24. The gamma voltage selector 22c selects and outputs the first gamma reference voltage set VREF1 in the operation period of the first pixel cell PX1 based on the gamma selection signal GSEL, and outputs the second pixel cell PX2. The second gamma reference voltage set VREF2 is selected and output in an operation period of. The gamma voltage selector 22c may include a multiplexer.

As described above, the gamma voltage generator 22 outputs only the first gamma reference voltage set VREF1 or the second gamma reference voltage set VREF2 at the same time.

The data driver 24 receives the pixel data DATA ′ of the pixel cells PX and the data control signal CONT1 from the controller 26. The data driver 24 converts the pixel data DATA 'into a corresponding analog pixel voltage and outputs the pixel data DATA ′ to the corresponding pixel cells PX through the data line DL. In this case, the first pixel data corresponding to the first pixel cell PX1 is converted into a corresponding first pixel voltage based on the first gamma reference voltage set VREF1 and output. In contrast, the second pixel data corresponding to the second pixel cell PX2 is converted into a corresponding second pixel voltage based on the second gamma reference voltage set VREF2 and output. The pixel data DATA ′ of the pixel cells PX provided by the timing controller 400 are in a digital form. Therefore, the data driver 14 converts the digital pixel data DATA 'into an analog pixel voltage and outputs the converted pixel voltages.

The data control signal CONT1 applies a corresponding pixel voltage to the horizontal synchronization signal STH and data line DL informing transmission of data to the pixel cells PX in a row unit arranged along the second direction D2. The data signal includes a load signal LOAD and a data clock signal DCLK for timing synchronization. In addition, the data control signal CONT1 may include a polarity inversion signal for inverting the polarity of the pixel voltage.

The data driver 24 includes a shift register 24a, a latch 24b, a digital analog converter 24c, and a buffer 24d. Here, the shift register 24a, latch 24b, digital analog converter 24c, and buffer 24d include the shift register 14a, latch 14b, digital analog converter 14c, and buffer 124d described in FIG. Are substantially the same, so detailed description is omitted. However, the digital-to-analog converter 24c selectively receives the first gamma reference voltage set VREF1 or the second gamma reference voltage set VREF2 from the gamma voltage generator 22.

Example 3

7 is a plan view illustrating a display panel of a display device according to a third exemplary embodiment of the present invention.

The display device according to the third exemplary embodiment of the present invention is substantially the same as the display device 10 of the first exemplary embodiment described with reference to FIGS. 1 and 2 except for the display panel 300. Alternatively, the display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second exemplary embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 300. That is, the display device according to the third exemplary embodiment of the present invention is a driver of the display panel 300, and the gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

The display panel 300 is substantially the same as the display panel 100 described with reference to FIGS. 3A and 3B except for the display substrate 310. In addition, the display substrate 310 illustrated in FIG. 8 may have the display substrate described with reference to FIGS. 3A and 3B except for the structure of the slit pattern of each of the first to fourth upper electrodes 314_1, 314_2, 314_3, and 314_4. Practically the same as 110). Therefore, the detailed description will be briefly described based on the differences.

Referring to FIG. 7, the display substrate 310 includes an insulating substrate (not shown), a plurality of signal lines, and a plurality of field forming electrodes, and switching elements SW1, SW2, for controlling the operation of the field forming electrodes. SW1 and SW4 and a first alignment layer (not shown) for initial alignment of the liquid crystal.

The insulating substrate has first to fourth pixel regions PA1, PA2, PA3, and PA4. The second pixel area PA2 is disposed in the first direction D1 of the first pixel area PA1, and each of the third and fourth pixel areas PA3 PA4 is the first and second pixel areas PA1 and PA2. It is arranged in the second direction D2 of).

The signal lines include first and second gate lines GL1 and GL2 and first and second data lines DL2 and DL2 and are formed to cross each other. The first and second gate lines GL1 and GL2 may extend in the second direction D2, and the first and second data lines DL2 and DL2 may extend in a zigzag form in the first direction D1. .

First to fourth lower electrodes 313_1, 313_2, 313_3, and 313_4 are formed in the first to fourth pixel regions PA1, PA2, PA3, and PA4, respectively, and the first to fourth lower electrodes 313_1. , 313_2, 313_3, and 313_4, respectively, overlap the first to fourth upper electrodes 314_1, 314_2, 314_3, and 314_4.

The first to fourth upper electrodes 314_1, 314_2, 314_3, and 314_4 include first to fourth slit patterns 315_1, 315_2, 315_3, and 315_4, respectively. The first and third slit patterns 315_1 and 315_3 extend in a third direction different from the first and second directions D1 and D2. The second and fourth slit patterns 315_2 and 315_4 extend in a fourth direction different from the first and second directions D1 and D2 and different from the third direction.

The first slit pattern 315_1 formed on the first upper electrode 314_1 has a first bent part 315_1a at one end so that the inclination angle with respect to the second direction D2 is small. That is, the first curved portion 315_1a is a structure in which one end of the first slit pattern 315_1a is refracted in the direction close to the second direction D2. In the case where the end portion of the first slit pattern 315_1a has an angled structure, electric field distortion occurs in the end region, which causes a decrease in the aperture ratio. Therefore, by providing the first bent portion 315_1a, the aperture ratio can be improved by alleviating electric field distortion in the end region of the first slit pattern 315_1.

The second slit pattern 315_2a formed on the second upper electrode 314_2 has a second curved portion 315_2a at one end so that the inclination angle with respect to the second direction D2 is small. The second curved portion 315_2a has a structure in which one end of the second slit pattern 315_2 is refracted in a direction close to the second direction D2. The second curved portion 315_2a has the same effect as that of the first curved portion 315_1a.

In addition, the third slit pattern 315_3 formed on the third upper electrode 314_3 has a third bent portion 315_3a at one end thereof, and the third slit pattern 315_3 extends in the same direction as the first slit pattern 315_1. Accordingly, the third curved portion 315_3a has the same structure as the first curved portion 315_1a.

The fourth slit pattern 315_4 formed on the fourth upper electrode 314_4 has a fourth bent portion 315_4 at one end thereof, and as the fourth slit pattern 315_4 extends in the same direction as the second slit pattern 315_2. The fourth bent portion 315_4a has the same structure as the second bent portion 315_2a.

Here, the first and second curved portions 315_1a and 315_2a may have a pattern that is symmetrical with respect to the first gate line GL1. That is, the first curved portion 315_1a is configured at one end of the first slit pattern 315_1 far from the first gate line GL1, and the second curved portion 315_2a is the second slit far from the first gate line GL1. One end of the pattern 315_2 may be configured. The third and fourth curved portions 315_3a and 315_4a are the same as those of the first and second curved portions 315_1a and 315_2a.

In the above description, the first to fourth bent portions 315_1a, 315_2a, 315_3a, and 315_4a are respectively provided at one ends of the first to fourth slit patterns 315_1, 315_2, 315_3, and 315_4. Alternatively, the first to fourth bends 315_1a, 315_2a, 315_3a, and 315_4a may be provided at one end and the other end (eg, both ends) of the first to fourth slit patterns 315_1, 315_2, 315_3, and 315_4, respectively. It may be.

Example 4

8 is a plan view illustrating a display panel of a display device according to a fourth exemplary embodiment of the present invention.

The display device according to the fourth exemplary embodiment of the present invention is substantially the same as the display device 10 of the first exemplary embodiment described with reference to FIGS. 1 and 2 except for the display panel 400. The display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second exemplary embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 400. That is, the display device according to the fourth exemplary embodiment of the present invention is a driver of the display panel 400. The gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

In addition, the display panel 400 is substantially the same as the display panel 100 described with reference to FIGS. 3A and 3B except for the display substrate 410. In addition, the display substrate 410 illustrated in FIG. 8 has a structure of a slit pattern of each of the first to fourth upper electrodes 414_1, 414_2, 414_3, and 414_4 and the first to fourth switching elements SW1, SW2, Except for the arrangement of SW3 and SW4, the display substrate 110 is similar to the display substrate 110 described with reference to FIGS. 3A and 3B. Therefore, the detailed description will be briefly described based on the differences.

Referring to FIG. 8, the display substrate 410 includes an insulating substrate (not shown), a plurality of signal lines, and a plurality of field forming electrodes, and switching elements SW1, SW2, for controlling the operation of the field forming electrodes. SW1 and SW4 and a first alignment layer (not shown) for initial alignment of the liquid crystal.

The insulating substrate has first to fourth pixel regions PA1, PA2, PA3, and PA4. The second pixel area PA2 is disposed in the first direction D1 of the first pixel area PA1, and the third and fourth pixel areas PA3 PA4 are respectively disposed in the first and second pixel areas PA1 and PA2. It is arranged in the second direction D2 of).

The signal lines include first and second gate lines GL1 and GL2 and first and second data lines DL2 and DL2 and are formed to cross each other. The first and second gate lines GL1 and GL2 may extend in the second direction D2, and the first and second data lines DL2 and DL2 may extend in a zigzag form in the first direction D1. .

First to fourth lower electrodes 413_1, 413_2, 413_3, and 413_4 are formed in the first to fourth pixel regions PA1, PA2, PA3, and PA4, respectively, and the first to fourth lower electrodes 413_1. , 413_2, 413_3, and 413_4 overlap with the first to fourth upper electrodes 414_1, 414_2, 414_3, and 414_4, respectively.

The first to fourth upper electrodes 414_1, 414_2, 414_3, and 414_4 respectively include the first to fourth slit patterns 415_1, 415_2, 415_3, and 415_4. Each of the first and third slit patterns 415_1 and 415_3 extends in the third direction. Each of the second and fourth slit patterns 415_2 and 415_4 extends in the fourth direction.

The first slit pattern 415_1 formed on the first upper electrode 414_1 has a first bent part 415_1a at one end and the other end thereof such that the inclination angle with respect to the second direction D2 is reduced. The first curved portion 415_1a is a portion refracted at one end and the other end of the first slit pattern 415_1 in a direction close to the second direction D2. The function of the first curved portion 415_1a is substantially the same as that of the first curved portion 315_1a (refer to FIG. 7) described in the third embodiment.

The second slit pattern 415_2 formed in the second upper electrode 414_2 has a second bent portion 415_2a at one end and the other end such that the inclination angle with respect to the second direction D2 is reduced. The second curved portion 415_2a is a portion refracted at one end and the other end of the second slit pattern 415_2 in a direction close to the second direction D2. The function of the second curved portion 415_2a is substantially the same as that of the second curved portion 315_2a (refer to FIG. 7) described in the third embodiment.

In addition, the third slit pattern 415_3 formed on the third upper electrode 414_3 has a third bent portion 415_3a at one end and the other end thereof, and the third slit pattern 415_3 is the same as the first slit pattern 415_1. As extending in the direction, the third curved portion 415_3a has the same structure as the first curved portion 415_1a.

The fourth slit pattern 415_4 formed on the fourth upper electrode 414_4 has a fourth bent portion 415_4a at one end and the other end thereof, and the fourth slit pattern 415_4 extends in the same direction as the second slit pattern 415_2. Accordingly, the fourth curved portion 415_4a has the same structure as the second curved portion 415_2a.

Here, the first and second bends 415_1a and 415_2a may have patterns that are symmetrical with respect to the first gate line GL1, and the third and fourth bends 415_3a and 415_4a may also have a first gate line ( GL1) may have a pattern that is symmetrical to each other.

In addition, the first upper electrode 414_1 may be electrically connected to the first switching element SW1. The first switching element SW1 is connected to the first gate line GL1 and the second data line DL2. The first and second data lines DL1 and DL2 may be disposed in parallel with each other with the first and second pixel areas PA1 and PA2 interposed therebetween.

The second upper electrode 414_2 may be electrically connected to the second switching element SW2. The second switching element SW2 is connected to the second gate line GL2 and the first data line DL1.

As such, the first and second switching elements SW1 and SW2 are connected to different data lines. In addition, the first switching element SW1 is disposed adjacent to the second data line DL2, and the second switching element SW2 is disposed adjacent to the first data line DL1. Therefore, the arrangement of the first and second switching elements SW1 and SW2 has a symmetrical structure. For example, the first switching device SW1 is disposed at a right portion adjacent to the second data line DL2 in the first pixel area PA1, and the second switching device SW2 is formed in the second pixel area PA2. 1 is disposed at the left side adjacent to the data line DL1.

Meanwhile, the third and fourth upper electrodes 414_3 and 414_4 are electrically connected to the third and fourth switching elements SW3 and SW4, respectively, and the structures of the third and fourth switching elements SW3 and SW4 are formed in the first and fourth switching electrodes SW3 and SW4, respectively. The structure is the same as that of the first and second switching elements SW1 and SW2.

As such, the arrangement of the switching elements SW1, SW2, SW3, and SW4 has a different structure along the first direction D1, so that the light blocking regions are alternately arranged so that visibility in the left and right directions is balanced. Can be.

Example 5

9 is a plan view illustrating a display panel of a display device according to a fifth exemplary embodiment of the present invention.

The display device according to the fifth exemplary embodiment of the present invention is substantially the same as the display device 10 of the first exemplary embodiment described with reference to FIGS. 1 and 2 except for the display panel 500. Alternatively, the display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 500. That is, the display device according to the fifth exemplary embodiment of the present invention is a driver of the display panel 500, and the gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

The display panel 500 is substantially the same as the display panel 100 described with reference to FIGS. 3A and 3B except for a part of the display substrate 510. Therefore, the detailed description will be briefly described based on the differences.

Referring to FIG. 9, the display substrate 510 includes an insulating substrate (not shown), a plurality of signal lines, and a plurality of field forming electrodes, and switching elements SW1, SW2, for controlling the operation of the field forming electrodes. SW3, SW4) and an alignment layer (not shown) for initial alignment of the liquid crystal.

The insulating substrate has first to fourth pixel regions PA1, PA2, PA3, and PA4. The second pixel area PA2 is disposed in the first direction D1 of the first pixel area PA1, and each of the third and fourth pixel areas PA3 PA4 is the first and second pixel areas PA1 and PA2. It is arranged in the second direction D2 of). Here, the first to fourth pixel areas PA1, PA2, PA3, and PA4 may have a rectangular shape, respectively. For example, each of the first to fourth pixel areas PA1, PA2, PA3, and PA4 may have a rectangular shape.

The signal lines include first and second gate lines GL1 and GL2 and first and second data lines DL1 and DL2 and are formed to cross each other. The first and second gate lines GL1 and GL2 may extend in the second direction D2, and the first and second data lines DL2 and DL2 may extend in the first direction D1.

Each of the first and second data lines DL1 and DL2 may extend in a straight line along the first direction D1, and the first and second data lines DL1 and DL2 may be parallel to each other. The first and second data lines DL1 and DL2 are disposed such that the first and second pixel areas PA1 and PA2 are positioned therebetween.

First to fourth lower electrodes 513_1, 513_2, 513_3, and 513_4 are formed in the first to fourth pixel regions PA1, PA2, PA3, and PA4, respectively, and the first to fourth lower electrodes 513_1. , 513_2, 513_3, and 513_4 overlap with the first to fourth upper electrodes 514_1, 514_2, 514_3, and 514_4, respectively.

The first to fourth upper electrodes 514_1, 514_2, 514_3, and 514_4 respectively include the first to fourth slit patterns 515_1, 515_2, 515_3, and 515_4. The first and third slit patterns 515_1 and 515_3 extend in a third direction different from the first and second directions D1 and D2. The second and fourth slit patterns 515_2 and 515_4 extend in a fourth direction different from the first and second directions D1 and D2 and different from the third direction. The third and fourth directions may be directions that are symmetrical with respect to the first gate line GL1.

The first slit pattern 515_1 formed on the first upper electrode 514_1 has a first bent part 515_1a at one end and the other end so that the inclination angle with respect to the second direction D2 is small. That is, the first curved portion 515_1a is a portion refracted at one end and the other end of the first slit pattern 515_1 in a direction close to the second direction D2. The function of the first curved portion 515_1a is the same as that of the first curved portion 315_1a (see FIG. 7) of the third embodiment described above.

The second slit pattern 515_2 formed on the second upper electrode 514_2 has a second bent portion 515_2a at one end and the other end such that the inclination angle with respect to the second direction D2 is small. The second curved portion 515_2a is a portion refracted at one end and the other end of the second slit pattern 515_2 in a direction close to the second direction D2. The function of the second curved portion 515_2a is the same as that of the second curved portion 315_2a (see FIG. 7) of the third embodiment described above.

In addition, the third slit pattern 515_3 formed on the third upper electrode 514_3 has a third bent portion 515_3a at one end and the other end thereof, and the third slit pattern 515_3 is the same as the first slit pattern 515_1. As extending in the direction, the third curved portion 515_3a has the same structure as the first curved portion 515_1a.

The fourth slit pattern 515_4 formed on the fourth upper electrode 514_4 has a fourth bent portion 515_4a at one end and the other end thereof, and the fourth slit pattern 515_4 extends in the same direction as the second slit pattern 515_2. Accordingly, the fourth curved portion 515_4a has the same structure as the second curved portion 515_2a.

Here, the first and second bends 515_1a and 515_2a may have a pattern that is symmetrical with respect to the first gate line GL1, and the third and fourth bends 515_3a and 515_4a may also have a first gate line GL1. ) May have a symmetric pattern.

The first upper electrode 514_1 may be electrically connected to the first switching element SW1. The first switching element SW1 is connected to the first gate line GL1 and the second data line DL2.

The second upper electrode 514_2 may be electrically connected to the second switching element SW2. The second switching element SW2 is connected to the second gate line GL2 and the first data line DL1.

As such, the first and second switching elements SW1 and SW2 are connected to different data lines. Therefore, the arrangement of the first and second switching elements SW1 and SW2 is the same as that of the fourth embodiment described above with reference to FIG. 8.

Each of the third and fourth upper electrodes 514_3 and 514_4 is electrically connected to the third and fourth switching elements SW3 and SW4, and the structures of the third and fourth switching elements SW3 and SW4 are formed in the first and fourth switching electrodes SW3 and SW4. The structure is the same as that of the second switching elements SW1 and SW2.

Sides of the first and second upper electrodes 514_1 and 514_2 adjacent to the first and second data lines DL1 and DL2 are formed parallel to the first and second data lines DL1 and DL2. Accordingly, the first and second upper electrodes 514_1 and 514_2 may have rectangular structures, respectively. Similarly, the third and fourth upper electrodes 514_3 and 514_4 may each have a rectangular structure.

As described above, the first to fourth pixel areas PA1, PA2, PA3, and PA4 have a rectangular shape, and the field forming electrodes have a shape corresponding thereto. Therefore, the division of each pixel part becomes easy. On the other hand, by forming an electric field in an inclined direction through the first to fourth slit patterns 515_1, 515_2, 515_3, and 515_4, the first and second pixel areas PA1 and PA2 are domains in different directions. Can be formed to improve the viewing angle and visibility and improve the aperture ratio.

Example 6

10 is a plan view illustrating a display panel of a display device according to a sixth exemplary embodiment of the present invention.

The display device according to the sixth exemplary embodiment of the present invention is substantially the same as the display device 10 of the first exemplary embodiment described with reference to FIGS. 1 and 2 except for the display panel 600. Alternatively, the display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 600. That is, the display device according to the third exemplary embodiment of the present invention is a driver of the display panel 600, and the gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

The display panel 600 is substantially the same as the display panel 100 described with reference to FIGS. 3A and 3B except for a part of the display substrate 610. Therefore, the detailed description will be briefly described based on the differences.

Referring to FIG. 11, the display substrate 600 includes an insulating substrate (not shown), a plurality of signal lines, and a plurality of field forming electrodes, and switching elements SW1, SW2, for controlling the operation of the field forming electrodes. SW1 and SW4 and a first alignment layer (not shown) for initial alignment of the liquid crystal.

The insulating substrate has first to fourth pixel regions PA1, PA2, PA3, and PA4. The second pixel area PA2 is disposed in the first direction D1 of the first pixel area PA1, and each of the third and fourth pixel areas PA3 PA4 is the first and second pixel areas PA1 and PA2. It is arranged in the second direction D2 of).

The signal lines include first and second gate lines GL1 and GL2 and first and second data lines DL2 and DL2 and are formed to cross each other. The first and second gate lines GL1 and GL2 extend in the second direction D2, and the first gate line GL1 is disposed between the first pixel area PA1 and the second pixel area PA2. . The first and second data lines DL2 and DL2 extend in a zigzag form in the first direction D1, and the zigzag form has at least one bend in each pixel region section.

First to fourth lower electrodes 613_1, 613_2, 613_3, and 613_4 are formed in the first to fourth pixel regions PA1, PA2, PA3, and PA4, respectively, and the first to fourth lower electrodes 613_1. , 613_2, 613_3, and 613_4 overlap with the first to fourth upper electrodes 614_1, 614_2, 614_3, and 614_4, respectively.

The first to fourth upper electrodes 614_1, 614_2, 614_3, and 614_4 include first to fourth slit patterns 615_1, 615_2, 615_3, and 615_4 to form domains of the liquid crystal, respectively.

The first slit pattern 615_1 includes portions extending in a third direction and a fourth direction which are different from the first and second directions D1 and D2 and are different from each other. For example, the first slit pattern 615_1 has a structure sequentially extending in the third direction and the fourth direction toward the first direction D1. That is, the first slit pattern 615_1 has a structure extending in the third direction and then refracted to extend in the fourth direction. Here, the third direction and the fourth direction may be directions that are symmetrical to each other based on the imaginary line extending in the second direction D2.

The second slit pattern 615_2 includes portions extending in the fourth and third directions. For example, the second slit pattern 615_2 has a structure sequentially extending in the fourth direction and the third direction toward the first direction D1. That is, the second slit pattern 615_2 has a refractive structure and has a structure opposite to that of the first slit pattern 615_1.

The third slit pattern 615_3 has a structure parallel to the first slit pattern 615_1, and the fourth slit pattern 615_4 has a structure parallel to the second slit pattern 615_2. In other words, the third and fourth slit patterns 615_3 and 615_4 have the same shape as the first and second slit patterns 615_1 and 615_2, respectively.

The first slit pattern 615_1 has a first bent portion 615_1a at one end so that the inclination angle with respect to the second direction D2 is small. The first curved portion 615_1a is disposed at an end portion of the third direction extension portion, and has a structure having a smaller inclination angle than the third direction with respect to the second direction D2. In addition, the first slit pattern 615_1 has a second bent part 615_1b so that the inclination angle becomes smaller with respect to the second direction D2 at the other end opposite to one end where the first bent part 615_1a is formed. The second bent part 615_1b is disposed at an end portion of the fourth direction extension part and has a structure having a smaller inclination angle than the fourth direction with respect to the second direction D2.

The second slit pattern 615_2 has a third bent portion 615_2a at one end so that the inclination angle with respect to the second direction D2 is small. The third bent part 615_1a is disposed at an end portion of the third direction extension part and has a structure having a smaller inclination angle than the third direction with respect to the second direction D2. In addition, the second slit pattern 615_2 has a fourth bent part 615_2b at the other end opposite to one end where the third bent part 615_2a is formed so that the inclination angle is small with respect to the second direction D2. The second bent part 615_2b is disposed at an end portion of the fourth direction extension part and has a structure having a smaller inclination angle than the fourth direction with respect to the second direction D2.

Here, one end of the first slit pattern 615_1 having the first bent part 615_1a and one end of the second slit pattern 615_2 having the third bent part 615_2a are end portions positioned in opposite directions.

The third slit pattern 615_3 has a fifth bent part 615_3a at one end and a sixth bent part 615_3b at the other end. The fifth and sixth curved portions 615_3a and 615_3b are substantially the same as the first and second curved portions 615_1a and 615_1b formed in the first slit pattern 615_1.

The fourth slit pattern 615_4 has a seventh bend 615_4a at one end and an eighth bend 615_4b at the other end. The seventh and eighth curved portions 615_4a and 615_4b are substantially the same as the third and fourth curved portions 615_2a and 615_2b formed in the second slit pattern 615_2.

In addition, the first upper electrode 614_1 is electrically connected to the first switching element SW1. The first switching element SW1 is connected to the first gate line GL1 and the second data line DL2.

The second upper electrode 614_2 is electrically connected to the second switching element SW2. The second switching element SW2 is connected to the second gate line GL2 and the first data line DL1.

As such, the first and second switching elements SW1 and SW2 are connected to different data lines. Therefore, the arrangement of the first and second switching elements SW1 and SW2 is substantially the same as that of the fourth embodiment described with reference to FIG. 9. For example, the first switching element SW1 is disposed on the right side in the first pixel area PA1 adjacent to the second data line DL2, and the second switching element SW2 is disposed in the first data line DL1. It is disposed on the left side in the second pixel area PA2 adjacent to.

Each of the third and fourth upper electrodes 615_3. 615_4 is electrically connected to the third and fourth switching elements SW3 and SW4, and the structures of the third and fourth switching elements SW3 and SW4 are respectively represented by the first and fourth switching electrodes SW3 and SW4. The structure is the same as that of the second switching elements SW1 and SW2.

Meanwhile, the first and second data lines DL1 and DL2 are disposed with the first and second pixel regions PA1 and PA2 interposed therebetween, and portions extending in parallel with the first slit pattern 615_1 and the second. And a portion extending in parallel with the slit pattern 615_2. That is, the first and second data lines DL1 and DL2 have a zigzag structure.

Accordingly, each of the first and second pixel areas PA1 and PA2 forms two domains, and has domain symmetry with respect to the first gate line GL1. Therefore, aperture ratio, viewing angle, and visibility can be improved.

Example 7

11A is a plan view illustrating a display panel according to a seventh exemplary embodiment of the present invention, and FIG. 11B is a cross-sectional view taken along the line II-II of FIG. 11A.

The display device according to the third exemplary embodiment of the present invention is substantially the same as the display device 10 of the first exemplary embodiment described with reference to FIGS. 1 and 2 except for the display panel 700. Alternatively, the display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second exemplary embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 700. That is, the display device according to the third exemplary embodiment of the present invention is a driver of the display panel 700, and the gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

11A and 11B, the display panel 700 includes a display substrate 710, an opposing substrate 720, and a liquid crystal layer 730. The opposing substrate 720 faces the display substrate 710, and the liquid crystal layer 720 is interposed between the display substrate 710 and the opposing substrate 720. The liquid crystal layer 730 may include liquid crystals LC. The display panel 700 further includes a first polarizer 702 and a second polarizer 704.

Here, the display panel 700 is substantially the same as the display panel 100 described with reference to FIGS. 3A and 3B except for a part of the display substrate 710. The display substrate 710 illustrated in FIG. 11A has a difference in that lower electrodes are electrically connected to switching elements. Therefore, the detailed description will be briefly described based on the differences.

The display substrate 710 includes an insulating substrate 711, a plurality of signal lines formed on the insulating substrate 711, and a plurality of field forming electrodes for forming an electric field. The display substrate 710 further includes switching elements SW1, SW2, SW3 and SW4 for operation control of the field forming electrodes and a first alignment layer 712 for initial alignment of the liquid crystal.

The insulating substrate 711 has first to fourth pixel regions PA1, PA2, PA3, and PA4. The second pixel area PA2 is disposed in the first direction D1 based on the first pixel area PA1, and each of the third and fourth pixel areas PA3 and PA4 corresponds to the first and second pixel areas ( It is arrange | positioned in the 2nd direction D2 of PA1 and PA2. Here, the first direction D1 and the second direction D2 may be directions perpendicular to each other.

The signal lines include first and second gate lines GL1 and GL2 and first and second data lines DL1 and DL2 and cross each other. The first and second gate lines GL1 and GL2 may extend in the second direction D2, and the first gate line GL1 may be disposed between the first and second pixel regions PA1 and PA2. The second gate line GL2 is disposed in parallel with the first gate line GL1 with the second pixel area PA2 interposed therebetween.

The field forming electrodes include first to fourth lower electrodes 713_1, 713_2, 713_3, and 713_4 and first to fourth upper electrodes 714_1, 714_2, 714_3, and 714_4.

The first to fourth lower electrodes 713_1, 713_2, 713_3, and 713_4 are formed in the first to fourth pixel regions PA1, PA2, PA3, and PA4, respectively. A gate insulating layer 717 is formed between the first to fourth lower electrodes 713_1, 713_2, 713_3, and 713_4 and the first and second gate lines GL1 and GL2 to insulate each other. It is preferable that the first to fourth lower electrodes 713_1, 713_2, 713_3, and 713_4 do not overlap adjacent signal lines, respectively. Accordingly, edges of the first to fourth lower electrodes 713_1, 713_2, 713_3, and 713_4 are respectively spaced apart from the signal lines by a predetermined distance. In this case, in some cases, the first to fourth lower electrodes 713_1, 713_2, 713_3, and 713_4 may be formed to partially overlap the adjacent gate line to form storage. Alternatively, a storage electrode (not shown) may be provided to overlap the first to fourth lower electrodes 713_1, 713_2, 713_3, and 713_4 to form storage. The storage electrode may be electrically connected to a storage line formed in parallel with the gate line, and may be formed of the same metal layer as the gate line.

The first lower electrode 713_1 may be electrically connected to the first switching element SW1. The first switching element SW1 is electrically connected to the first gate line GL1 and the first data line DL1. The first lower electrode 713_1 may be a pixel electrode receiving a pixel voltage for displaying an image from the first data line DL1 according to the switching operation of the first switching element SW1.

The second lower electrode 713_2 may be electrically connected to the second switching element SW2. The second switching element SW2 is electrically connected to the second gate line GL2 and the first data line DL1. The second lower electrode 713_2 may be a pixel electrode receiving a pixel voltage for displaying an image from the first data line DL1 according to the switching operation of the second switching element SW2.

The third and fourth lower electrodes 713_3 and 713_4 are electrically connected to the second data line DL2 through the third and fourth switching elements SW3 and SW4, respectively.

The first to fourth lower electrodes 713_1, 713_2, 713_3, and 713_4 may be plate-shaped electrodes.

The first to fourth upper electrodes 714_1, 714_2, 714_3, and 714_4 are formed in the first to fourth pixel areas PA1, PA2, PA3, and PA4, respectively. The first to fourth upper electrodes 714_1, 714_2, 714_3, and 714_4 overlap the first to fourth lower electrodes 713_1, 713_2, 713_3, and 713_4, respectively. The first passivation layer 718 is disposed between the first to fourth upper electrodes 714_1, 714_2, 714_3, and 714_4 and the first to fourth lower electrodes 713_1, 713_2, 713_3, and 713_4 to insulate each other. do.

The first to fourth upper electrodes 714_1, 714_2, 714_3, and 714_4 have first to fourth slit patterns 715_1, 715_2, 715_3, and 715_4 to form domains of the liquid crystal, respectively. The first to fourth slit patterns 715_1, 715_2, 715_3, and 715_4 are the first to fourth slit patterns 115_1, 115_2, and 115_3 of the display substrate 110 of the first embodiment described with reference to FIGS. 3A and 3B, respectively. , 115_4).

The first to fourth upper electrodes 714_1, 714_2, 714_3, and 714_4 may be common electrodes to which a common voltage is applied. In the first to fourth upper electrodes 714_1, 714_2, 714_3, and 714_4, the first and second upper electrodes 714_1 and 714_2 have an integrated structure, and the third and fourth upper electrodes 714_3 and 714_4 are integrated. It may be a stripe structure having a structure. Alternatively, the first to fourth upper electrodes 714_1, 714_2, 714_3, and 714_4 may have one unitary structure except for some regions. That is, the upper electrodes may have an integrated structure with respect to the entire surface of the display substrate 710. Alternatively, the first to fourth upper electrodes 714_1, 714_2, 714_3, and 714_4 may have a separate structure (for example, island type), and in this case, a common voltage line may be separately provided to provide the first to fourth upper electrodes. It may be electrically connected to the electrodes 714_1, 714_2, 714_3, 714_4.

The display panel 700 forms a domain of the liquid crystal through the first to fourth slit patterns 715_1, 715_2, 715_3, and 715_4 formed on the first to fourth upper electrodes 714_1, 714_2, 714_3, and 714_4. Form. In detail, a single domain is formed for each pixel area, and domains of different directions, for example, symmetrical directions, are formed between adjacent pixel areas in the first direction D1 to obtain a multi-domain effect. Therefore, viewing angle and visibility can be improved with opening ratio improvement.

The first alignment layer 712 is formed on the insulating substrate 711 on which the first to fourth upper electrodes 714_1, 714_2, 714_3, and 714_4 are formed. In the first alignment layer 712, the alignment directions in each of the first to fourth pixel areas PA1, PA2, PA3, and PA4 are processed to be the same, so that the surface directivity forms a single direction when viewed in plan view. The alignment direction of the first alignment layer 712 may be defined as a direction in which the liquid crystal is aligned. The alignment direction of the first alignment layer 712 may be a first direction D1 or a second direction D2. The first alignment layer 712 is formed on one surface of the insulating substrate 712 in contact with the liquid crystal layer.

The opposing substrate 720 may include an insulating substrate 721, a light blocking pattern BM, and color filters CF formed on the insulating substrate 721. The opposing substrate 720 may further include a second alignment layer 722 for initial alignment of the liquid crystal.

The light blocking pattern BM is formed to overlap the signal lines and the switching elements. The light blocking pattern BM blocks light transmission.

The color filters CF are formed to overlap the pixel areas PA1, PA2, PA3, and PA4, respectively. The color filters CF may have a three color configuration, and in some cases, may further include a white (or transparent) color filter CF.

The second alignment layer 722 is formed on one surface of the second alignment layer 722 facing the display substrate 7100 and in contact with the liquid crystal layer 730. The second alignment layer 722 is processed so that the alignment directions in the regions corresponding to the first to fourth pixel regions PA1, PA2, PA3, and PA4 are the same, so that the first to fourth pixel regions are viewed in plan view. The surface orientations in the areas corresponding to the fields PA1, PA2, PA3, and PA4 may be the same. That is, the second alignment layer 722 is formed in a single alignment direction with respect to the entire surface of the insulating substrate 721. The alignment of the second alignment layer 722 may be formed through a rubbing process or a photo alignment process. The alignment direction of the second alignment layer 722 is the same direction as the alignment direction of the first alignment layer 712.

Each of the first polarizer 702 and the second polarizer 704 is disposed on an outer surface of the display substrate 710 and the opposing substrate 720. The first polarizing plate 702 has a polarization axis in the same direction as the alignment direction of the first alignment layer 712 included in the display substrate 710.

The second polarizing plate 704 is disposed on the upper surface of the opposing substrate 720, that is, the surface opposite to the surface in contact with the liquid crystal layer 730. The second polarizer 704 has a polarization axis perpendicular to the polarization axis of the first polarizer 702.

Example 8

12 is a plan view illustrating a display panel of a display device according to an eighth embodiment of the present invention.

The display device according to the eighth embodiment of the present invention is substantially the same as the display device 10 according to the first embodiment described with reference to FIGS. 1 and 2 except for the display panel 800. Alternatively, the display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second exemplary embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 800. That is, the display device according to the third exemplary embodiment of the present invention is a driver of the display panel 800, and the gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

The display panel 800 is substantially the same as the display panel 700 described with reference to FIGS. 11A and 11B except for the display substrate 810. Also, the display substrate 810 illustrated in FIG. 12 may have the display substrate described with reference to FIGS. 11A and 11B except for the structure of the slit pattern of each of the first to fourth upper electrodes 314_1, 314_2, 314_3, and 314_4. 710 is substantially the same. Therefore, the detailed description will be briefly described based on the differences.

Referring to FIG. 12, the display substrate 810 may include an insulating substrate 811, a plurality of signal lines, a plurality of field forming electrodes, a plurality of switching elements SW1, SW2, SW3, and SW4 and a first alignment layer. Not shown).

The insulating substrate 811 has first to fourth pixel regions PA1, PA2, PA3, and PA4. The second pixel area PA2 is disposed in the first direction D1 of the first pixel area PA1, and each of the third and fourth pixel areas PA3 PA4 is the first and second pixel areas PA1 and PA2. It is arranged in the second direction D2 of).

The signal lines include first and second gate lines GL1 and GL2 and first and second data lines DL2 and DL2 and are formed to cross each other. The first and second gate lines GL1 and GL2 may extend in the second direction D2, and the first and second data lines DL2 and DL2 may extend in a zigzag form in the first direction D1. have.

First to fourth lower electrodes 813_1, 813_2, 813_3, and 813_4 are formed in the first to fourth pixel regions PA1, PA2, PA3, and PA4, respectively, and the first to fourth lower electrodes 813_1. , 813_2, 813_3, and 813_4 overlap with the first to fourth upper electrodes 814_1, 814_2, 814_3, and 814_4.

The first lower electrode 813_1 is electrically connected to the first switching element SW1. The first switching element SW1 is electrically connected to the first gate line GL1 and the first data line DL1. The first lower electrode 813_1 may be a pixel electrode to which a pixel voltage for displaying an image is applied.

The second lower electrode 813_2 is electrically connected to the second switching element SW2. The second switching element SW2 is electrically connected to the second gate line GL2 and the first data line DL1. The second lower electrode 813_2 may be a pixel electrode to which a pixel voltage for displaying an image is applied.

Each of the third and fourth lower electrodes 813_3 and 813_4 is electrically connected to the second data line DL2 through the third and fourth switching elements SW3 and SW4, and is connected to the image from the second data line DL2. It may be a pixel electrode receiving a pixel voltage for displaying.

The first to fourth upper electrodes 814_1, 814_2, 814_3, and 814_4 respectively include first to fourth slit patterns 815_1, 815_2, 815_3, and 815_4 for domain formation of liquid crystals. The first to fourth slit patterns 815_1, 815_2, 815_3, and 815_4 may be formed of the first to fourth slit patterns 315_1, 315_2, 315_3, and 315_4 of the display substrate 310 of the third embodiment described with reference to FIG. 7. same.

The first to fourth upper electrodes 814_1, 814_2, 814_3, and 814_4 may be common electrodes to which a common voltage is applied. The first to fourth upper electrodes 814_1, 814_2, 814_3, and 814_4 may have a stripe structure, an integrated structure, or a separate structure as described in the seventh embodiment.

Example 9

13 is a plan view illustrating a display panel of a display device according to a ninth embodiment of the present invention.

The display device according to the ninth embodiment of the present invention is substantially the same as the display device 10 according to the first embodiment described with reference to FIGS. 1 and 2 except for the display panel 900. Alternatively, the display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second exemplary embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 900. That is, the display device according to the third exemplary embodiment of the present invention is a driver of the display panel 900, and the gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

The display panel 900 is substantially the same as the display panel 700 described with reference to FIGS. 11A and 11B except for the display substrate 910. In addition, the display substrate 910 illustrated in FIG. 13 has a structure of a slit pattern of each of the first to fourth upper electrodes 414_1, 414_2, 414_3, and 414_4 and the first to fourth switching elements SW1, SW2, Except for the arrangement of the SW3 and SW4, the display substrate 710 is substantially the same as the display substrate 710 described with reference to FIGS. 11A and 11B. Therefore, the detailed description will be briefly described based on the differences.

Referring to FIG. 13, the display substrate 900 may include an insulating substrate (not shown), a plurality of signal lines, a plurality of field forming electrodes, a plurality of switching elements SW1, SW2, SW3, and SW4, and a first alignment layer. (Not shown).

The insulating substrate has first to fourth pixel areas PA1, PA2, PA3, and PA4. The second pixel area PA2 is disposed in the first direction D1 of the first pixel area PA1, and each of the third and fourth pixel areas PA3 PA4 is the first and second pixel areas PA1 and PA2. It is arranged in the second direction D2 of).

The signal lines include first and second gate lines GL1 and GL2 and first and second data lines DL2 and DL2. The first and second gate lines GL1 and GL2 may extend in the second direction D2, and the first and second data lines DL1 and DL2 may extend in a zigzag form in the first direction D1. . The first and second data lines DL1 and DL2 may be arranged in parallel with the first and second pixel areas PA1 and PA2 interposed therebetween.

First to fourth lower electrodes 913_1, 913_2, 913_3, and 913_4 are formed in the first to fourth pixel regions PA1, PA2, PA3, and PA4, respectively, and the first to fourth lower electrodes 913_1. , 913_2, 913_3, and 913_4 overlap with the first to fourth upper electrodes 914_1, 914_2, 914_3, and 914_4.

The first lower electrode 913_1 is electrically connected to the first switching element SW1. The first switching element SW1 is connected to the first gate line GL1 and the second data line DL2. The first lower electrode 913_1 is a pixel electrode to which a pixel voltage is applied.

The second lower electrode 913_2 is electrically connected to the second switching element SW2. The second switching element SW2 is connected to the second gate line GL2 and the first data line DL1. The second lower electrode 913_2 is a pixel electrode to which a pixel voltage is applied.

As such, the first and second switching elements SW1 and SW2 are connected to different data lines. In addition, the first switching element SW1 is disposed adjacent to the second data line DL2, and the second switching element SW2 is disposed adjacent to the first data line DL1. Therefore, the arrangement of the first and second switching elements SW1 and SW2 has a symmetrical structure for each pixel area.

Meanwhile, each of the third and fourth lower electrodes 913_3 and 913_4 is electrically connected to the third and fourth switching elements SW3 and SW4, and the structures of the third and fourth switching elements SW3 and SW4 are The structure is the same as that of the first and second switching elements SW1 and SW2.

The first to fourth upper electrodes 914_1, 914_2, 914_3, and 914_4 include first to fourth slit patterns 915_1, 915_2, 915_3, and 915_4, respectively. The first to fourth slit patterns 915_1, 915_2, 915_3, and 915_4 may be different from the first to fourth slit patterns 415_1, 415_2, 415_3, and 415_4 of the display substrate 410 of the fourth embodiment described with reference to FIG. 8. same.

The first to fourth upper electrodes 914_1, 914_2, 914_3, and 914_4 may be common electrodes to which a common voltage is applied. The first to fourth upper electrodes 914_1, 914_2, 914_3, and 914_4 may have a stripe structure, an integrated structure, or a separate structure as described in the seventh embodiment.

Example 10

14 is a plan view illustrating a display panel of a display device according to a tenth exemplary embodiment of the present invention.

The display device according to the tenth embodiment of the present invention is substantially the same as the display device 10 according to the first embodiment described with reference to FIGS. 1 and 2 except for the display panel 1000. Alternatively, the display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second exemplary embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 1000. That is, the display device according to the third exemplary embodiment of the present invention is a driver of the display panel 1000. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

The display panel 1000 is substantially the same as the display panel 700 described with reference to FIGS. 11A and 11B except for a part of the display substrate 1010. Therefore, the detailed description will be briefly described based on the differences.

Referring to FIG. 11, the display substrate 900 includes an insulating substrate (not shown), a plurality of signal lines, a plurality of field forming electrodes, a plurality of switching elements SW1, SW2, SW3, and SW4, and a first alignment layer. (Not shown).

The insulating substrate has first to fourth pixel areas PA1, PA2, PA3, and PA4. The second pixel area PA2 is disposed in the first direction D1 of the first pixel area PA1, and each of the third and fourth pixel areas PA3 PA4 is the first and second pixel areas PA1 and PA2. It is arranged in the second direction D2 of). Here, each of the first to fourth pixel areas PA1, PA2, PA3, and PA4 may have a rectangular shape.

The signal lines include first and second gate lines GL1 and GL2 and first and second data lines DL2 and DL2 and cross each other. The first and second gate lines GL1 and GL2 may extend in the second direction D2, and the first and second data lines DL2 and DL2 may extend in the first direction D1.

Each of the first and second data lines DL1 and DL2 may extend in a straight line along the first direction D1, and the first and second data lines DL1 and DL2 may be parallel to each other. The first and second pixel areas PA1 and PA2 are disposed between the first and second data lines DL1 and DL2.

First to fourth lower electrodes 1013_1, 1013_2, 1013_3, and 1013_4 are formed in the first to fourth pixel regions PA1, PA2, PA3, and PA4, respectively, and the first to fourth lower electrodes 1013_1. The first to fourth upper electrodes 1014_1, 1014_2, 1014_3, and 1014_4 overlap with the first and second upper electrodes 1013_2, 1013_3, and 1013_4.

The first to fourth upper electrodes 1014_1, 1014_2, 1014_3, and 1014_4 include the first to fourth slit patterns 1015_1, 1015_2, 1015_3, and 1015_4, respectively. The first to fourth slit patterns 1015_1, 1015_2, 1015_3, and 1015_4 may be different from the first to fourth slit patterns 514_1, 514_2, 514_3, and 514_4 of the display substrate 510 of the fifth embodiment described with reference to FIG. 9. same.

The first lower electrode 1013_1 is electrically connected to the first switching element SW1. The first switching element SW1 is connected to the first gate line GL1 and the second data line DL2. The first lower electrode 1013_1 is a pixel electrode.

The second lower electrode 1013_2 is electrically connected to the second switching element SW2. The second switching element SW2 is connected to the second gate line GL2 and the first data line DL1. The second lower electrode 1013_2 is a pixel electrode.

The first switching element SW1 is disposed adjacent to the second data line DL2, and the second switching element SW2 is disposed adjacent to the first data line DL1. Therefore, the arrangement of the first and second switching elements SW1 and SW2 has a symmetrical structure for each pixel area.

The third and fourth lower electrodes 1013_3 and 1013_4 are electrically connected to the third and fourth switching elements SW3 and SW4, respectively, and the structures of the third and fourth switching elements SW3 and SW4 may be the first and the fourth lower electrodes 1013_3 and 1013_4, respectively. The structure is the same as that of the second switching elements SW1 and SW2.

In the first to fourth upper electrodes 1014_1, 1014_2, 1014_3, and 1014_4, sides adjacent to the data line are formed parallel to the data line. Accordingly, the first to fourth upper electrodes 1014_1, 1014_2, 1014_3, and 1014_4 may each have a rectangular structure.

Example 11

15 is a plan view illustrating a display panel of a display device according to an eleventh embodiment of the present invention.

The display device according to the eleventh embodiment of the present invention is substantially the same as the display device 10 according to the first embodiment described with reference to FIGS. 1 and 2 except for the display panel 1100. The display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second exemplary embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 1100. That is, the display device according to the third exemplary embodiment of the present invention is a driver of the display panel 1100, and the gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

The display panel 1100 is substantially the same as the display panel 700 described with reference to FIGS. 11A and 11B except for a part of the display substrate 1110. Therefore, the detailed description will be briefly described based on the differences.

Referring to FIG. 12, the display substrate 1100 includes an insulating substrate (not shown), a plurality of signal lines, a plurality of field forming electrodes, switching elements SW1, SW2, SW3, and SW4, and a first alignment layer (not shown). May include).

The insulating substrate has first to fourth pixel areas PA1, PA2, PA3, and PA4. The second pixel area PA2 is disposed in the first direction D1 of the first pixel area PA1, and each of the third and fourth pixel areas PA3 PA4 is the first and second pixel areas PA1 and PA2. It is arranged in the second direction D2 of).

The signal lines include first and second gate lines GL1 and GL2 and first and second data lines DL2 and DL2 and are formed to cross each other. The first and second gate lines GL1 and GL2 extend in the second direction D2, and the first gate line GL1 is disposed between the first and second pixel regions PA1 and PA2. The first and second data lines DL2 and DL2 extend in a zigzag form in the first direction D1, and the zigzag form has at least one bend in each pixel region section.

First to fourth lower electrodes 1113_1, 1113_2, 1113_3, and 1113_4 are formed in the first to fourth pixel regions PA1, PA2, PA3, and PA4, respectively, and the first to fourth lower electrodes 1113_1. The first to fourth upper electrodes 1114_1, 1114_2, 1114_3, and 1114_4 overlap with the first and second top electrodes 1113_2, 1113_3, and 1113_4.

The first to fourth upper electrodes 1114_1, 1114_2, 1114_3, and 1114_4 include first to fourth slit patterns 1115_1, 1115_2, 1115_3, and 1115_4 to form domains of the liquid crystal, respectively. The first to fourth slit patterns 1115_1, 1115_2, 1115_3, and 1115_4 may be different from the first to fourth slit patterns 615_1, 615_2, 615_3, and 615_4 of the display substrate 610 of the sixth embodiment described with reference to FIG. 10. same.

The first lower electrode 1113_1 is electrically connected to the first switching element SW1. The first switching element SW1 is connected to the first gate line GL1 and the second data line DL2. The first lower electrode 1113_1 is a pixel electrode.

The second lower electrode 1113_2 is electrically connected to the second switching element SW2. The second switching element SW2 is connected to the second gate line GL2 and the first data line DL1. The second lower electrode 1113_2 is a pixel electrode.

The first and second switching elements SW1 and SW2 are connected to different data lines. In addition, the first switching element SW1 is disposed adjacent to the second data line DL2, and the second switching element SW2 is disposed adjacent to the first data line DL1. Therefore, the arrangement of the first and second switching elements SW1 and SW2 has a symmetrical structure for each pixel area.

Each of the third and fourth lower electrodes 924 and 928 is electrically connected to the third and fourth switching elements SW3 and SW4. It is substantially the same as the structure of the second switching elements SW1 and SW2.

The first and second data lines DL1 and DL2 have the same shape as the first and second data lines DL1 and DL2 of the display substrate 610 of the sixth embodiment described with reference to FIG. 10.

Example 12

16A and 16B are equivalent circuit diagrams and plan views illustrating a display panel of a display device according to a twelfth embodiment of the present invention.

The display device according to the twelfth embodiment of the present invention is substantially the same as the display device 10 according to the first embodiment described with reference to FIGS. 1 and 2 except for the display panel 1200. Alternatively, the display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second exemplary embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 1200. That is, the display device according to the third exemplary embodiment of the present invention is a driver of the display panel 1200, and the gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

The display panel 1200 is substantially the same as the display panel 100 described with reference to FIGS. 3A and 3B except for a part of the display substrate 1210. Therefore, the detailed description will be briefly described based on the differences.

16A and 16B, the display panel 1200 includes a display substrate 1210 or a lower substrate, an opposing substrate (or an upper substrate), and a liquid crystal layer. The opposing substrate faces the display substrate 1210, and the liquid crystal layer is interposed between the display substrate 1210 and the opposing substrate.

In an equivalent circuit, the display panel 1200 includes a plurality of pixel cells PX and a plurality of signal lines GL and DL connected to the pixel cells PX. The plurality of pixel cells PX is arranged in a matrix form. For example, the plurality of pixel cells PX may include first to eighth pixel cells PX1 to PX8. The pixel cells sequentially arranged in the first direction D1 based on the first pixel cell PX1 on the plane may be defined as second to third pixel cells PX2, PX3, and PX4, respectively. The first direction D1 may be a longitudinal direction (or a column direction). The fifth to eighth pixel cells PX5, PX6, PX7, and PX8 may be defined as pixel cells disposed in the second direction D2 in the first to fourth pixel cells PX1, PX2, PX3, and PX4, respectively. . That is, the pixel cells arranged in the second direction D2 of the first pixel cell PX1 may be defined as the fifth pixel cell PX5. Pixel cells sequentially arranged in the first direction D1 based on the fifth pixel cell PX5 may be defined as sixth to eighth pixel cells PX6, PX7, and PX8, respectively. The second direction D2 may be a direction crossing the first direction D1, for example, a direction perpendicular to the first direction D1, and may be a horizontal direction (or a row direction). The pixel cells PX are arranged in a matrix form.

The pixel cells PX each include a pair of field forming electrodes and a liquid crystal layer formed on the display substrate 1210. For example, in the case of the first pixel cell PX1, a pair of field forming electrodes includes a first lower electrode 1213_1 and a first upper electrode 1214_1 overlapping the first lower electrode 1213_1. The first upper electrode 1214_1 has a first slit pattern 1215_1 for forming a domain. The pixel cells PX form a domain through an electric field according to a slit pattern formed at each upper electrode.

The first and second pixel cells PX1 and PX2 have different domains. The domains of the first pixel cell PX1 and the second pixel cell PX2 may be symmetrical with respect to the gate line GL. That is, the domains of the first and second pixel cells PX1 and PX2 may have a structure that is symmetrical with respect to the second direction D2 which is an extension direction of the gate line GL. The third and fourth pixel cells PX3 and PX4 have different domains. The third and fourth pixel cells PX3 and PX4 may have a symmetrical structure with respect to the gate line GL or the second direction D2. The third and fourth pixel cells PX3 and PX4 have different domains. The fifth and sixth pixel cells PX5 and PX6 may have a symmetrical structure with respect to the gate line GL or the second direction D2. The seventh and eighth pixel cells PX7 and PX8 have different domains. The seventh and eighth pixel cells PX7 and PX8 may have a symmetrical structure with respect to the gate line GL or the second direction D2. In this case, the first, third, fifth, and seventh pixel cells PX1, PX3, PX5, and PX7 have the same domain, and the second, fourth, sixth, and eighth pixel cells PX2, PX4, PX6, PX8) may be the same domain. That is, the pixel cells PX in the pixel cells PX disposed along the second direction D2, which is the extending direction of the gate line GL, have the same domain and have a first extension direction of the data line DL. Adjacent pixel cells PX arranged along the direction D1 may have a structure having different domains.

The signal lines GL and DL include gate lines GL and data lines DL that intersect the gate lines GL. The signal lines are connected to the pixel cells PX. For example, each of the pixel cells PX may be connected to one gate line GL and one data line DL. For example, the signal lines may include first to fourth gate lines GL1, GL2, GL3, and GL4 and first to third data lines DL1, DL2, and DL3.

The display substrate 1210 includes an insulating substrate (not shown), a plurality of signal lines, a plurality of field forming electrodes, a plurality of switching elements, and a first alignment layer (not shown).

The insulating substrate has first to eighth pixel areas PA1 to PA8. The first to eighth pixel cells PA1 to PA8 have the same arrangement as the first to eighth pixel cells PX1 to PX8 described above in the equivalent circuit diagram. That is, the first to fourth pixel areas PA1, PA2, PA3, and PA4 may be defined as pixel areas sequentially disposed along the first direction D1. The fifth to eighth pixel areas PA5, PA6, PA7, and PA8 may be defined as pixel areas disposed in the second direction D1 of the first to fourth pixel areas PA1, PA2, PA3, and PA4, respectively. have.

The signal lines include first to fourth gate lines GL1, GL2, GL3, and GL4 and first to third data lines DL1, DL2, and DL3, and are formed to cross each other.

The first to fourth gate lines GL1, GL2, GL3, and GL4 extend in the second direction D2 and are disposed parallel to each other. In particular, the first and second gate lines GL1 and GL2 are disposed parallel to each other with the first and second pixel regions PA1 and PA2 interposed therebetween and the fifth and sixth pixel regions PA5 and PA6 interposed therebetween. The first gate line GL1 is disposed on one side (eg, above) of the first and fifth pixel areas PA1 and PA5, and the second gate line GL2 is opposite to the second and sixth pixel areas PA2, It is disposed on the other side of PA6) (for example, below). The second gate line GL2 is disposed between the second pixel area PA2 and the third pixel area PA3 and between the sixth pixel area PA6 and the seventh pixel area PA7. The third and fourth gate lines GL3 and GL4 are disposed parallel to each other with the third and fourth pixel regions PA3 and PA4 interposed therebetween and the seventh and eighth pixel regions PA7 and PA8 interposed therebetween. The third gate line GL3 is disposed on one side (eg, above) of the third and seventh pixel areas PA3, and the fourth gate line GL4 is in the opposite direction of the fourth and eighth pixel areas PA4 and PA8. It is disposed on the other side of (eg the bottom). The third gate line GL3 is disposed between the second pixel area PA2 and the third pixel area PA3 and between the sixth pixel area PA6 and the seventh pixel area PA7. The third gate line GL3 is disposed between the second gate line GL2 and the third pixel area PA3 and between the second gate line GL2 and the seventh pixel area PA7. Therefore, the gate line GL is not disposed between the first pixel area PA1 and the second pixel area PA2 and between the fifth pixel area PA5 and the sixth pixel area PA6. On the other hand, two gate lines GL are disposed between the second pixel area PA2 and the third pixel area PA3 and between the sixth pixel area PA6 and the seventh pixel area PA7. As a result, the gate lines GL have a structure in which two wires are arranged in units of two pixel areas PA in the first direction D1.

The first to third data lines DL, DL2, and DL3 may cross the first to second gate lines GL1, GL2, GL3, and GL4, for example, the first direction to cross the second direction D2. Extending parallel to D1). For example, the first and second data lines DL1 and DL2 are disposed on one side (eg, the left side) of the first and fifth pixel areas PA1 and PA5, respectively, and the third data line DL3 is the second. The second pixel area PA5 is disposed on the other side (for example, the right side) in the opposite direction of the data line DL2.

The field forming electrodes include first to eighth lower electrodes 1213_1 to 1213_8 and first to eighth upper electrodes 1214_1 to 1214_8.

First to eighth lower electrodes 1213_1 to 1213_8 are formed in the first to eighth pixel areas PA1 to PA8, respectively, and overlap the first to eighth lower electrodes 1213_1 to 1213_8. To eighth upper electrodes 1214_1 to 1214_8.

The first to eighth upper electrodes 1214_1 to 1214_8 include first to eighth slit patterns 1215_1 to 1215_8, respectively. The first, third, fifth and seventh slit patterns 1215_1, 1215_3, 1215_5, and 1215_7 extend in a third direction different from the first and second directions D1 and D2. The second, fourth, sixth, and seventh slit patterns 1215_2, 1215_4, 1215_6, and 1215_8 extend in a fourth direction different from the third and second directions D1 and D2. The third and fourth directions may be symmetrical with respect to the second direction D2, which is an extension direction of the gate line GL.

The first to eighth upper electrodes 1214_1 to 1214_8 are electrically connected to the first to eighth switching elements SW1 to SW8, respectively, to be electrically connected to the signal lines. The first to eighth upper electrodes 1214_1 to 1214_8 may be pixel electrodes provided with a pixel voltage.

The first to eighth switching elements SW1 to SW8 are disposed in the first to eighth pixel areas PA1 to PA8, respectively.

The first to fourth switching elements SW1, SW2, SW3, and SW4 are electrically connected to the first to fourth gate lines GL1, GL2, GL3, and GL4, respectively, and are all connected to the first data line DL1. Electrically connected. The fourth to eighth switching elements SW5, SW6, SW7, and SW8 are electrically connected to the first to fourth gate lines GL1, GL2, GL3, and GL4, respectively, and are all connected to the second data line DL2. Electrically connected. The first to eighth switching elements SW1 to SW8 may be disposed adjacent to the signal lines electrically connected to each other.

In the display substrate 1210 described above, structural features of the data lines DL, the lower electrodes, the upper electrodes, and the slit patterns may include the display substrates according to the embodiments 3 to 6 described with reference to FIGS. 8 to 11. 310, 410, 510, 610 may be the same.

Although not shown, the opposite substrate includes a light blocking pattern, color filters, and a second alignment layer formed on the insulating substrate.

17 is a plan view illustrating a light shielding pattern included in an opposing substrate in a display panel of a twelfth embodiment of the present invention.

Referring to FIG. 17, the light blocking pattern BM is formed to overlap the signal lines GL1 to GL4 and DL1 to DL3 and the switching elements SW1 to SW8 formed on the display substrate 1210.

The light blocking pattern BM has a width d1 in the first direction D1 that is relatively narrower than that of the light blocking target. In detail, when the gate pattern includes the gate line GL and the switching element SW connected to the gate line GL, the light blocking pattern BM overlaps the gate pattern with respect to the first direction D1. The width d1 is smaller than the width d2 of the gate pattern. For example, the width d1 of the light blocking pattern BM disposed between the second pixel area PA2 and the third pixel area PA3 based on the first direction D1 may correspond to the second and third gate lines. GL2 and GL3 are formed to be narrower than the overall width d2 of the second and third switching elements SW2 and SW3 connected thereto. In this case, the width d2 of the gate pattern may be defined as the distance from one end of the second switching element SW2 to the other end of the third switching element SW3 in the opposite direction.

As described above, the light shielding pattern BM is formed to be narrower than the width of the gate pattern, so that an alignment margin can be secured when the display substrate 1210 and the counter substrate (not shown) are bonded to each other. Therefore, it is possible to improve the reduction of the aperture ratio due to the alignment error.

The light blocking pattern BM may have a width in the second direction D2 equal to or relatively narrow with respect to the data line DL.

Example 13

18 is a plan view illustrating a display panel of a display device according to a thirteenth embodiment.

The display device according to the thirteenth embodiment of the present invention is substantially the same as the display device 10 according to the first embodiment described with reference to FIGS. 1 and 2 except for the display panel 1300. Alternatively, the display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second exemplary embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 1300. That is, the display device according to the third exemplary embodiment of the present invention is a driver of the display panel 1300, and the gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

The display panel 1300 is substantially the same as the display panel 1200 described with reference to FIGS. 16A and 16B except for a part of the display substrate 1310. Therefore, the detailed description will be briefly described based on the differences.

Referring to FIG. 18, the display substrate 1210 includes an insulating substrate (not shown), a plurality of signal lines, a plurality of field forming electrodes, a plurality of switching elements, and a first alignment layer (not shown).

The insulating substrate has first to eighth pixel areas PA1 to PA8. The first to fourth pixel areas PA1, PA2, PA3, and PA4 may be defined as pixel areas sequentially disposed along the first direction D1. The fifth to eighth pixel areas PA5, PA6, PA7, and PA8 may be defined as pixel areas disposed in the second direction D1 of the first to fourth pixel areas PA1, PA2, PA3, and PA4, respectively. have.

The signal lines include first to fourth gate lines GL1, GL2, GL3, and GL4 and first to third data lines DL1, DL2, and DL3, and are formed to cross each other.

The field forming electrodes include first to eighth lower electrodes 1213_1 to 1213_8 and first to eighth upper electrodes 1214_1 to 1214_8.

First to eighth lower electrodes 1213_1 to 1213_8 are formed in the first to eighth pixel areas PA1 to PA8, respectively, and overlap the first to eighth lower electrodes 1213_1 to 1213_8. To eighth upper electrodes 1214_1 to 1214_8. The first to eighth upper electrodes 1214_1 to 1214_8 include first to eighth slit patterns 1215_1 to 1215_8, respectively.

The first to eighth upper electrodes 1214_1 to 1214_8 are electrically connected to the first to eighth switching elements SW1 to SW8, respectively, to be electrically connected to the signal lines. The first to eighth upper electrodes 1214_1 to 1214_8 may be pixel electrodes provided with a pixel voltage.

The first to eighth switching elements SW1 to SW8 are disposed in the first to eighth pixel areas PA1 to PA8, respectively.

The first to fourth switching elements SW1, SW2, SW3, and SW4 are electrically connected to the first to fourth gate lines GL1, GL2, GL3, and GL4, respectively, and the second and fourth switching elements SW2. , SW4 is connected to the first data line DL1, and the first and third switching elements SW1 and SW3 are connected to the second data line DL2.

The fourth to eighth switching elements SW5, SW6, SW7, and SW8 are electrically connected to the first to fourth gate lines GL1, GL2, GL3, and GL4, respectively, and the sixth and eighth switching elements SW6. , SW8 is connected to the second data line DL2, and the fifth and seventh switching elements SW5 and SW7 are connected to the third data line DL2.

As such, since the arrangement of the switching elements SW1 to SW8 has a different structure along the first direction D1, the visibility of the light blocking in the left and right directions may be balanced since the regions where light is blocked are alternately arranged. In addition, since the switching elements SW1 to SW8 are alternately connected to different data lines DL along the first direction D1, the dot driving effect may be obtained by applying a pixel voltage in a line inversion scheme.

 In the display substrate 1310 described above, structural features of the data lines DL, the lower electrodes, the upper electrodes, and the slit patterns may include the display substrates according to the embodiments 3 to 6 described with reference to FIGS. 8 to 11. 310, 410, 510, 610 may be the same.

Although not illustrated, the display panel 1300 may include an opposing substrate facing the display substrate 1310. The opposing substrate includes a light blocking pattern, and the light blocking pattern is substantially the same as that of the twelfth embodiment described with reference to FIG. 18.

Example 14

19A and 19B are equivalent circuit diagrams and plan views illustrating a display panel of a display device according to a twelfth embodiment of the present invention.

The display device according to the fourteenth exemplary embodiment of the present invention is substantially the same as the display device 10 of the first exemplary embodiment described with reference to FIGS. 1 and 2 except for the display panel 1400. The display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second exemplary embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 1400. That is, the display device according to the third exemplary embodiment of the present invention is a driver of the display panel 1400, and the gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

The display panel 1400 is substantially the same as the display panel 700 described with reference to FIGS. 12 and 13 except for a part of the display substrate 1210. Therefore, the detailed description will be briefly described based on the differences.

19A and 19B, the display panel 1400 includes a display substrate 1410 or a lower substrate, an opposing substrate (or an upper substrate), and a liquid crystal layer.

In an equivalent circuit, the display panel 1400 includes a plurality of pixel cells PX and a plurality of signal lines GL and DL connected to the pixel cells PX. The plurality of pixel cells PX is arranged in a matrix form. For example, the plurality of pixel cells PX may include first to eighth pixel cells PX1 to PX8.

The pixel cells PX each include a pair of field forming electrodes and a liquid crystal layer formed on the display substrate 1410. The pixel cells PX form a domain through an electric field according to a slit pattern formed at each upper electrode.

The pixel cells PX are arranged along the second direction D2, which is the extending direction of the gate line GL, and the pixel cells PX have the same domain, and the first direction (the extending direction of the data line DL). Adjacent pixel cells PX disposed along D1) may have a structure having different domains.

The signal lines GL and DL include gate lines GL and data lines DL that intersect the gate lines GL. The signal lines are connected to the pixel cells PX. For example, the signal lines may include first to fourth gate lines GL1, GL2, GL3, and GL4 and first to third data lines DL1, DL2, and DL3.

The display substrate 1410 includes an insulating substrate (not shown), a plurality of signal lines, a plurality of field forming electrodes, a plurality of switching elements, and a first alignment layer (not shown).

The insulating substrate has first to eighth pixel areas PA1 to PA8. The first to fourth pixel areas PA1, PA2, PA3, and PA4 may be defined as pixel areas sequentially disposed along the first direction D1. The fifth to eighth pixel areas PA5, PA6, PA7, and PA8 may be defined as pixel areas disposed in the second direction D1 of the first to fourth pixel areas PA1, PA2, PA3, and PA4, respectively. have.

The signal lines include first to fourth gate lines GL1, GL2, GL3, and GL4 and first to third data lines DL1, DL2, and DL3, and are formed to cross each other. The signal lines are substantially the same as the display panel 1200 described with reference to FIGS. 16A and 16B.

The field forming electrodes include first to eighth lower electrodes 1413_1 to 1413_8 and first to eighth upper electrodes 1414_1 to 1414_8.

First to eighth lower electrodes 1413_1 to 1413_8 are formed in the first to eighth pixel regions PA1 to PA8, respectively, and overlap the first to eighth lower electrodes 1413_1 to 1413_8. To eighth upper electrodes 1414_1 to 1414_8 are formed.

The first to eighth lower electrodes 1413_1 to 1413_8 are electrically connected to the first to eighth switching elements SW1 to SW8, respectively, to be electrically connected to the signal lines. The first to eighth lower electrodes 1414_1 to 1414_8 may be pixel electrodes provided with a pixel voltage.

The first to eighth upper electrodes 1414_1 to 1414_8 include first to eighth slit patterns 1415_1 to 1415_8, respectively. The first, third, fifth, and seventh slit patterns 1415_1, 1415_3, 1415_5, and 1415_7 extend in a third direction different from the first and second directions D1 and D2. The second, fourth, sixth, and seventh slit patterns 1415_2, 1415_4, 1415_6, and 1415_8 extend in a fourth direction different from the third and second directions D1 and D2. The third and fourth directions may be symmetrical with respect to the second direction D2, which is an extension direction of the gate line GL.

In particular, the first and second upper electrodes 1414_1 and 1414_2 may have an integrated structure. In addition, the first and second slit patterns 1415_1 and 1415_2 formed on the first and second upper electrodes 1414_1 and 1414_2 may have a structure connected to each other. That is, one end (eg, top) of the second slit pattern 1415_2 and the other end (eg, bottom) of the first slit pattern 1415_1 facing each other may have a structure connected to each other. As such, since the first and second slit patterns 1415_1 and 1415_2 are connected to each other, the electric field distortion is reduced at the boundary between the first upper electrode 1414_1 and the second upper electrode 1414_2. This improves the horizontal line visibility.

The first to eighth switching elements SW1 to SW8 are disposed in the first to eighth pixel areas PA1 to PA8, respectively.

The first to fourth switching elements SW1, SW2, SW3, and SW4 are electrically connected to the first to fourth gate lines GL1, GL2, GL3, and GL4, respectively, and are all connected to the first data line DL1. Electrically connected. The fourth to eighth switching elements SW5, SW6, SW7, and SW8 are electrically connected to the first to fourth gate lines GL1, GL2, GL3, and GL4, respectively, and are all connected to the second data line DL2. Electrically connected. The first to eighth switching elements SW1 to SW8 may be disposed adjacent to the signal lines electrically connected to each other.

In the display substrate 1210 described above, structural features of the shape of the data lines DL, the lower electrodes, the upper electrodes, and the slit patterns may include the display substrates according to the embodiments 8 to 11 described with reference to FIGS. 14 to 17. 810, 910, 1010, 1110.

Although not illustrated, the display panel 1400 may include an opposing substrate facing the display substrate 1410. The opposing substrate includes a light blocking pattern, and the light blocking pattern is substantially the same as that of the twelfth embodiment described with reference to FIG. 18.

Example 15

20 is a plan view illustrating a display panel of a display device according to a fifteenth embodiment of the present invention.

The display device according to the fifteenth embodiment of the present invention is substantially the same as the display device 10 according to the first embodiment described with reference to FIGS. 1 and 2 except for the display panel 1500. In addition, the display device according to the third exemplary embodiment of the present invention is substantially the same as the other display device 20 of the second exemplary embodiment described with reference to FIGS. 4, 5, and 6 except for the display panel 1500. That is, the display device according to the third exemplary embodiment of the present invention is a driver of the display panel 1500, and the gamma voltage generator 12, the data driver 14, the controller 16, and the gate driver 18 described in the first embodiment are described. Or a gamma voltage generator 22, a data driver 24, a controller 26, and a gate driver 28 described in the second embodiment.

The display panel 1500 is substantially the same as the display panel 1400 described with reference to FIGS. 19A and 19B except for a part of the display substrate 1510. Therefore, the detailed description will be briefly described based on the differences.

Referring to FIG. 20, the display substrate 1510 may include an insulating substrate (not shown), a plurality of signal lines, a plurality of field forming electrodes, a plurality of switching elements, and a first alignment layer (not shown).

The insulating substrate has first to eighth pixel areas PA1 to PA8. The first to fourth pixel areas PA1, PA2, PA3, and PA4 may be defined as pixel areas sequentially disposed along the first direction D1. The fifth to eighth pixel areas PA5, PA6, PA7, and PA8 may be defined as pixel areas disposed in the second direction D1 of the first to fourth pixel areas PA1, PA2, PA3, and PA4, respectively. have.

The signal lines include first to fourth gate lines GL1, GL2, GL3, and GL4 and first to third data lines DL1, DL2, and DL3, and are formed to cross each other. It is formed to cross each other. The signal lines are substantially the same as the display substrate 1210 described with reference to FIGS. 16A and 16B.

The field forming electrodes include first to eighth lower electrodes 1513_1 to 1513_8 and first to eighth upper electrodes 1514_1 to 1514_8.

First to eighth lower electrodes 1513_1 to 1513_8 are formed in the first to eighth pixel areas PA1 to PA8, respectively, and overlap the first to eighth lower electrodes 1513_1 to 1513_8. To eighth upper electrodes 1514_1 to 1514_8. The first to eighth upper electrodes 1514_1 to 1514_8 respectively include the first to eighth slit patterns 1515_1 to 1515_8.

The first to eighth lower electrodes 1513_1 to 1513_8 are electrically connected to the first to eighth switching elements SW1 to SW8, respectively, to be electrically connected to the signal lines. The first to eighth lower electrodes 1514_1 to 1514_8 may be pixel electrodes provided with a pixel voltage.

The first to eighth upper electrodes 1514_1 to 1514_8 respectively include the first to eighth slit patterns 1515_1 to 1515_8. The first to eighth slit patterns 1515_1 to 1515_8 are the same as the first to eighth slit patterns 1415_1 to 1415_8 of the display substrate 1410 described with reference to FIGS. 19A and 19B.

The first to eighth switching elements SW1 to SW8 are disposed in the first to eighth pixel areas PA1 to PA8, respectively. The first to eighth switching elements SW1 to SW8 and the signal lines GL and DL are connected to the first to eighth switching elements SW1 to SW8 of the display substrate 1410 described with reference to FIGS. 19A and 19B. Is substantially the same as

In the display substrate 1310 described above, structural features of the data lines DL, the lower electrodes, the upper electrodes, and the slit patterns may include the display substrates according to the embodiments 3 to 6 described with reference to FIGS. 8 to 11. 300, 400, 500, 600).

Although not illustrated, the display panel 1300 may include an opposing substrate facing the display substrate 1310. The opposing substrate includes a light blocking pattern, and the light blocking pattern is substantially the same as that of the twelfth embodiment described with reference to FIG. 18.

As described above, the exemplary embodiments of the present invention have been described, but the present invention is not limited thereto, and a person skilled in the art does not depart from the spirit and scope of the following claims. It will be appreciated that various changes and modifications are possible in the following.

According to the display substrate and the display device including the same according to the exemplary embodiments of the present invention, the transmittance, which is an advantage of the single domain, and the viewing angle and visibility, which are the advantages of the multi-domain, are improved. Therefore, the present invention can be used in a display device for improving display quality.

In addition, in a small display device that is difficult to form a multi-domain in the related art,

Formation improves viewing angle and visibility. Therefore, it can be used to improve the display quality of the small display device, and can be applied to improve the viewing angle and visibility without lowering the transmittance in the display device.

10, 20: display device 12, 22: gamma voltage generator
14, 24: data driver 16, 26: control unit
18 and 28: gate driver 100: display panel
102: first polarizing plate 104: second polarizing plate
110: display substrate 111: insulating substrate
112: first alignment layer 113_1: first lower electrode
113_2: second lower electrode 113_3: third lower electrode
113_4: fourth lower electrode 114_1: first upper electrode
114_2: second upper electrode 114_3: third upper electrode
114_4: fourth upper electrode 115_1: first slit pattern
115_2: second slit pattern 115_3: third slit pattern
115_4: Fourth slit pattern 120: Opposing substrate
121: insulating substrate 122: second alignment layer
130: liquid crystal layer GL1, GL2: first and second gate wirings
DL1, DL2: First and second data lines LC: Liquid crystal
AP: active pattern GE: gate electrode
DE: drain electrode SE: source electrode
BM: Shading Pattern CF: Color Filter
PA1, PA2, PA3, PA4: first, second, third, and fourth pixel areas
SW1, SW2, SW3, SW4: first, second, third and fourth switching elements

Claims (20)

A first pixel cell including a first lower electrode and a first upper electrode overlapping the first lower electrode and having a first slit pattern, disposed in a first direction of the first pixel cell, and a second lower electrode and the A second pixel cell including a second upper electrode overlapping a second lower electrode and having a second slit pattern extending in a direction different from an extending direction of the first slit pattern; and in a second direction different from the first direction A display panel extending and including a first gate line disposed between the first pixel cell and the second pixel cell;
A gamma voltage generator configured to generate a first gamma reference voltage set and a second gamma reference voltage set having a voltage level different from that of the first gamma reference voltage set;
A controller configured to output first and second pixel data corresponding to the first and second pixel cells, respectively; And
The first pixel data is converted into a first pixel voltage having a corresponding analog form based on the first gamma reference voltage set and output, and the second pixel data is corresponding analog based on the second gamma reference voltage set. And a data driver for converting the second pixel voltage into a second pixel voltage. The gamma selection signal of claim 1, wherein the controller is configured to process an externally provided image signal to output the first and second pixel data, and to control a selection of the first and second gamma reference voltage sets. Output together,
And the data driver comprises a gamma voltage selector configured to select the first gamma reference voltage set or the second gamma reference voltage set according to the gamma selection signal. The gamma selection signal of claim 1, wherein the controller is configured to process an externally provided image signal to output the first and second pixel data, and to control a selection of the first and second gamma reference voltage sets. Output together,
And the gamma voltage generator selectively outputs the first gamma reference voltage set or the second gamma reference voltage set according to the gamma selection signal. The method of claim 3, wherein the gamma voltage generator
A first gamma part including a first resistance column and generating the first gamma reference voltage set using an externally provided power supply voltage;
A second gamma part including a second resistance row different from the first resistance row and generating the second gamma reference voltage set using the power supply voltage; And
And a gamma voltage selector configured to selectively output the first gamma reference voltage set or the second gamma reference voltage set according to the gamma selection signal among the first and second gamma reference voltage sets. The display device of claim 1, wherein the first and second gamma reference voltage sets have different gamma values. The display device of claim 1, wherein the extending direction of the first slit pattern and the extending direction of the second slit pattern have symmetrical structures with respect to the first gate line. The display panel of claim 1, wherein the display panel
And a first data line extending in the first direction and crossing the first gate line and connected to at least one of the first and second pixel cells. The method of claim 1, wherein the first and second pixel cells operate sequentially.
And a selection period of the first and second gamma reference voltage sets is the same as an operation period of the first and second pixel cells. An insulating substrate having a first pixel region and a second pixel region disposed in a first direction of the first pixel region;
First and second gate lines extending in a second direction crossing the first direction on the insulating substrate and disposed parallel to each other with the first and second pixel regions interposed therebetween;
First and second lower electrodes formed on the first and second pixel regions, respectively;
A first upper electrode overlapping the first lower electrode in the first pixel area and having a first slit pattern extending in a third direction different from the first and second directions;
A second upper electrode overlapping the second lower electrode in the second pixel area and having a second slit pattern extending in a fourth direction different from the first to third directions;
A first switching element connected to the first gate line and disposed in the first pixel area; And
And a second switching element connected to the second gate line and disposed in the second pixel area. The display device of claim 9, further comprising: a first data line intersecting the first and second gate lines and disposed on one side of the first and second pixel regions,
And the first and second switching elements are connected to the first data line. 10. The method of claim 9, further comprising first and second data lines intersecting the first and second gate lines and disposed parallel to each other with the first and second pixel regions interposed therebetween.
The first switching element is connected to the first data line,
And the second switching element is connected to the second data line. The method according to any one of claims 10 and 11,
The first switching device is electrically connected to the first upper electrode,
And the second switching element is electrically connected to the second upper electrode. The method according to any one of claims 10 and 11,
The first switching element is electrically connected to the first lower electrode,
And the second switching element is electrically connected to the second lower electrode. The display substrate of claim 13, wherein the first upper electrode and the second upper electrode have an integral structure connected to each other, and the first and second slit patterns are connected to each other. 10. The semiconductor device of claim 9, further comprising an alignment layer formed on an insulating substrate on which the first and second upper electrodes are formed, and having the same alignment direction in each of the first and second pixel regions.
The alignment direction of the alignment layer is the first direction or the second direction. The method of claim 9, wherein the second direction is a direction perpendicular to the first direction,
And the third and fourth directions are symmetrical with respect to the first gate line. The semiconductor device of claim 9, wherein the insulating substrate further comprises a third pixel area disposed in the first direction of the second pixel area.
A third gate line extending in the second direction on the insulating substrate and disposed between the second gate line and the third pixel region;
A third lower electrode formed in the third pixel region;
A third upper electrode overlapping the third lower electrode in the third pixel area and having a third slit pattern extending in the third direction; And
And a third switching element connected to the third gate line and disposed in the third pixel area adjacent to the third gate line. An insulating substrate having a first pixel region and a second pixel region disposed in a first direction of the first pixel region and extending in a second direction crossing the first direction on the insulating substrate; First and second gate lines disposed to be parallel to each other with the pixel region interposed therebetween, first and second lower electrodes formed on the first and second pixel regions, and the first and second gate electrodes respectively disposed in the first pixel region. A first upper electrode overlapping the first lower electrode and having a first slit pattern extending in a third direction different from the first and second directions, and overlapping the second lower electrode in the second pixel area; A second upper electrode having a second slit pattern extending in a fourth direction different from the third to third directions, a first switching element connected to the first gate line and disposed in the first pixel area, and the second gate Connected to a line and arranged in the second pixel area A display substrate comprising a second switching element mounted.
An opposing substrate facing the display substrate and including a light blocking pattern overlapping the first and second gate lines, the first and second data lines, and the first and second switching elements; And
And a liquid crystal layer interposed between the display substrate and the opposing substrate. The semiconductor device of claim 18, wherein the insulation substrate further comprises a third pixel region disposed in the first direction of the second pixel region.
The display substrate
A third gate line extending in the second direction and disposed between the second gate line and the third pixel region;
A third lower electrode disposed in the third pixel area on the insulating substrate;
A third upper electrode overlapping the third lower electrode and having a third slit pattern extending in the third direction; And
And a third switching element electrically connected to the third gate line and formed in the third pixel area. 20. The second and third gate lines of claim 19, wherein a width of the light blocking pattern overlapping the second pixel area and the third pixel area with respect to the first direction is set at one end of the second switching element. And a width narrower than a width to the other end of the third switching device on the opposite side of the display panel.

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