KR20130000656A - Method of fabricating display panel - Google Patents

Abstract

PURPOSE: A method for manufacturing a display panel is provided to surround an upper and a lower motherboard with a dummy sealant, thereby preventing damage to the substrate due to etchant. CONSTITUTION: A sealant pattern including first sealants(210a), second sealants(210b) and at least one dummy sealant(210c) are formed on one of an upper motherboard and a lower motherboard(101). Liquid crystal is dropped in a space obtained by the first sealant. Multiple display panels are formed by combining the upper motherboard with the lower motherboard. The first and the second sealant, and the dummy sealant are hardened. The rear side of the motherboard is etched. Unit display panels are separated by scribing.

Description

Manufacturing method of display panel {METHOD OF FABRICATING DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a display panel, and more particularly, to a method of manufacturing a display panel which can not be bonded.

In general, a liquid crystal display (LCD) displays an image by allowing each of the liquid crystal cells arranged in a matrix form on a liquid crystal display panel to adjust light transmittance according to a video signal.

The liquid crystal display panel includes a thin film transistor substrate and a color filter substrate that are bonded by a binder with a liquid crystal interposed therebetween.

The color filter substrate includes a color filter array including a black matrix for preventing light leakage, a color filter for color implementation, a common electrode forming a vertical electric field with the pixel electrode, and an upper alignment layer coated thereon for liquid crystal alignment thereon. Is formed.

The thin film transistor substrate includes a gate line and a data line intersecting each other on a lower substrate, a thin film transistor (TFT) formed at an intersection thereof, a pixel electrode connected to the thin film transistor, and a liquid crystal alignment thereon. A thin film transistor array including the applied lower alignment layer is formed on the lower substrate.

Conventionally, a manufacturing process for manufacturing a liquid crystal display panel is divided into an array forming process, a substrate bonding / liquid crystal implantation process, a substrate scribing process, and the like.

The array forming process is divided into an upper array forming process and a lower array forming process.

In the upper array forming process, a plurality of color filter arrays are formed on an upper substrate. Each of the plurality of color filter arrays constitutes an independent display element. In the lower array forming process, a plurality of thin film transistor arrays are formed on a lower substrate. Each of the plurality of thin film transistor arrays constitutes an independent display device.

A sealant is formed on one of the upper and lower mother substrates, the liquid crystal is dropped in the liquid crystal space provided by the sealant, and then the upper and lower mother substrates are bonded. The backside of the bonded upper and lower mother substrates are etched to form the substrates to the desired thickness. At this time, the etching liquid penetrates between the upper and lower mother substrates, thereby causing the inside of the liquid crystal display panel to be etched. In order to prevent the etching solution from penetrating between the upper and lower mother substrates, the upper and lower mother substrates are coated with a bonding agent. As described above, the bonding agent is formed of a UV curable resin-based bonding agent, and the upper and lower mother substrates are coated and then cured by irradiating UV. In order to perform the bonding operation, a moving operation is performed such as up loading or shifting the upper and lower mother substrates. Scratches are generated in the upper and lower mother substrates while performing such a moving operation. As described above, the bonding operation requires much UV curing process, and a separate bonding agent is required, thereby increasing the processing time and cost. In the case of the bonding operation, since the material is made of UV rays or a bonding agent, it is harmful to the human body. When the bonding agent is applied to the outer edges of the upper and lower mother substrates, there is a possibility that it is applied unevenly. At this time, surface etching stains are generated during the etching process by the bonding agent having a non-uniform thickness. In this way, the bonding operation is a problem that the non-uniform surface etching process according to the process time and cost, the difference in the coating thickness of the bonding agent is made.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a method of manufacturing a display panel which can not be bonded.

To this end, a method of manufacturing a display panel according to the present invention includes forming a plurality of color filter arrays on an upper mother substrate, and forming a plurality of thin film transistor arrays on a lower mother substrate corresponding to the upper mother substrate. And first sealants formed in a closed loop shape to surround a plurality of array regions on either one of the upper and lower mother substrates, and a closed loop so as to surround an outside of the region where the unit display panel is to be formed. Forming a sealant pattern including second sealants formed in a shape, and at least one dummy sealant formed in a closed loop shape to surround an outer side of one of the upper and lower mother substrates; Forming a plurality of display panels by dropping liquid crystals into a space provided by the upper and lower mother substrates; Hardening the first and second sealants and the at least one dummy sealant, etching back surfaces of the bonded upper and lower mother substrates, and scribing to separate the unit display panels. It is characterized by the above-mentioned.

Here, the at least one dummy sealant is formed to surround an end of the outer edge of the lower mother substrate.

In addition, the at least one dummy sealant may be formed to surround the second sealants at a predetermined interval from the end of the outer edge of the lower mother substrate.

Here, the distance between the end of the outer edge of the lower mother substrate and the end of the dummy sealant is greater than 0 and less than 10mm.

The at least one dummy sealant may include a first dummy sealant formed to surround an end of the outer edge of the lower mother substrate, and a second dummy sealant formed at a predetermined distance from the end of the outer edge of the lower mother substrate. .

Here, the distance between the end of the outer edge of the lower mother substrate and the end of the second dummy sealant is greater than 0 and less than 10mm.

In addition, the at least one dummy sealant may be formed in plural within a range of 10 mm from an end of the outer edge of the lower mother substrate.

As described above, the method of manufacturing the display panel according to the present invention may include at least one of the upper and lower mother substrates in the form of a closed loop so as to surround one of the upper and lower mother substrates in a closed loop instead of applying the bonding agent to the upper and lower mother substrates. Form a dummy sealant. Accordingly, at least one dummy sealant without a bonding agent is used to prevent substrate damage caused by the etchant and to prevent the etchant from penetrating into the cell.

In addition, since the dummy sealant according to the present invention is formed at the same time when forming the first and second sealants without any additional process, the process time or the cost may be reduced accordingly.

1 is a flowchart sequentially illustrating a method of manufacturing a display panel according to a first embodiment of the present invention.
2A and 2B are views illustrating a sealant pattern forming process according to a first embodiment of the present invention, FIG. 2A is a perspective view illustrating a sealant pattern forming process, and FIG. 2B is a view illustrating the lower mother substrate shown in FIG. It is sectional drawing cut along the line I '.
3A and 3B are views illustrating a sealant pattern forming process in a different pattern from FIGS. 2A and 2B, FIG. 3A is a perspective view illustrating a sealant pattern forming process, and FIG. 3B is a view illustrating the lower mother substrate shown in FIG. It is sectional drawing cut along the line I '.
4A and 4B illustrate a bonding process of upper and lower mother substrates according to the sealant pattern forming process illustrated in FIGS. 2A and 2B.
5A and 5B illustrate a bonding process of upper and lower mother substrates according to the sealant pattern forming process illustrated in FIGS. 3A and 3B.
6A and 6B illustrate a process of forming a sealant pattern in a method of manufacturing a display panel according to a second exemplary embodiment of the present invention, FIG. 6A is a perspective view illustrating a process of forming a sealant pattern, and FIG. 6B is illustrated in FIG. 6A. The lower mother substrate is a cross-sectional view taken along the line II ′.
7A and 7B illustrate a bonding process according to the sealant pattern forming process illustrated in FIGS. 6A and 6B.
8 is a perspective view showing a display panel formed by the manufacturing method according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The configuration of the present invention and the operation and effect thereof will be clearly understood through the following detailed description. Before describing the present invention in detail, the same components are denoted by the same reference symbols as possible even if they are displayed on different drawings. In the case where it is judged that the gist of the present invention may be blurred to a known configuration, do.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 1 to 8. FIG.

1 is a flowchart sequentially illustrating a method of manufacturing a display panel according to a first embodiment of the present invention.

Referring to FIG. 1, a manufacturing process for manufacturing the display panel according to the first exemplary embodiment of the present invention includes an array forming process (step S1), a sealant pattern forming process (S2 step), a liquid crystal dropping process (S3 step), Bonding process (step S4), sealant pattern curing process (step S5), substrate etching process (step S6), scribing process (step S7), liquid crystal cell inspection process (step S8), module inspection process (step S9) Include.

The array forming process (step S1) is divided into a color filter array forming process and a thin film transistor array forming process.

In the color filter array forming process, a plurality of color filter arrays are formed on the upper mother substrate 141. Here, each of the plurality of color filter arrays includes a black matrix 142 for preventing light leakage, a color filter 144 for color implementation, a common electrode 148 forming a vertical electric field with the pixel electrode 122, and a liquid crystal on them. An upper alignment film (not shown) applied for orientation.

In the thin film transistor array forming process, a plurality of thin film transistor arrays are formed on the lower mother substrate 101. Here, each of the plurality of thin film transistor arrays includes a gate line and a data line formed to cross each other, a thin film transistor (TFT) formed at an intersection thereof, a pixel electrode 122 connected to the thin film transistor, and thereon A lower alignment layer (not shown) coated for liquid crystal alignment.

In this case, the plurality of TFTs formed on the lower mother substrate 101 are positioned to face the gate electrode 102 connected to the gate line, the source electrode 108 connected to the data line, and the source electrode 108. And overlap the gate electrode 102 with the drain electrode 110 and the gate insulating layer 112 connected therebetween to form a channel between the source electrode 108 and the drain electrode 110. A thin film transistor TFT and a thin film transistor TFT including an ohmic contact layer 116 formed on the active layer except for a channel region for ohmic contact with the active layer 114, the source electrode 108, and the drain electrode 110. A pixel electrode 122 connected to the drain electrode 110 of the pixel electrode.

The sealant pattern forming process (step S2) surrounds the plurality of array regions on one of the upper mother substrate 141 on which the plurality of color filter arrays are formed and the lower mother substrate 101 on which the plurality of thin film transistor arrays are formed. The first sealants 210a formed to cover the first sealant 210a, the second sealants 210b formed to surround the area where the unit display panel is to be formed, and an outer portion of one of the upper and lower mother substrates in a closed loop shape. Dummy sealants 210c and 210d are formed. As shown in FIGS. 2A and 3A, the sealant pattern 210 may be formed by a dispensing method or a screen printing method in which the adhesive is discharged by applying a constant pressure to the syringes 200. . Although the sealant pattern 210 may be formed by a screen printing method, the forming by the dispensing method will be described by way of example.

In detail, as illustrated in FIGS. 2A and 3A, the first sealant 210a is formed on the lower mother substrate 101 in a closed loop form to surround the image display unit AA in which the plurality of thin film transistor arrays are formed. The second sealants 210b are formed in a closed loop form to surround the area where the unit display panel is to be formed after the end point 212 of the first sealant 210a. As described above, the second sealant 210b may include the scribing line 141a of the upper mother substrate 141 formed for each unit display panel and the scribing line 101a of the lower mother substrate 101 formed for each unit display panel. It is formed to surround. Since the second sealant 210b is formed to surround the outer portion of the unit display panel, each unit display panel is maintained at a constant gap. That is, the back surface of each of the upper mother substrate 101 and the lower mother substrate 141 is etched to form a flexible thin film substrate. In this case, the second sealant is formed to surround each unit display panel so that each unit display panel is not bent and maintains a constant gap.

The dummy sealants 210c and 210d may be formed to surround the ends of the outer edge of the lower mother substrate 101 as shown in FIGS. 2A and 2B, or the outer edge of the lower mother substrate 101 as shown in FIGS. 3A and 3B. It may be formed to surround the second sealants 210b spaced apart from the end by a predetermined distance D. The distance D between the outer edge of the lower mother substrate 101 and the end of the dummy sealant 210d is greater than 0 and less than or equal to 10 mm. The dummy sealants 210c and 201d may be formed at any position within this range, but the dummy sealants 210c and 210d must be within the above ranges to omit the conventional bonding operation. That is, when the dummy sealants 210c and 210d are positioned inside the upper and lower mother substrates 101 and 141 so that the dummy sealants 210c and 210d are too close to the second sealant 210b, the etching liquid is the mother substrate during the back etching process of the upper and lower mother substrates 101 and 141. 101,141) can be sharpened. When the ends of the mother substrates 101 and 141 are sharp, the mother substrates 101 and 141 may be broken, so that dummy sealants 210c and 210d should be formed within the range to prevent the ends of the mother substrates 101 and 141 from being sharpened. The etchant may not penetrate between the upper and lower mother substrates 101 and 141.

As such, the dummy sealants 210c and 210d are formed to surround the outer side of the lower mother substrate 101, thereby preventing damage to the substrate due to the etchant during the back etching process of the upper and lower mother substrates 101 and 141. To prevent penetration.

In the conventional bonding operation, a bonding agent is applied to surround the outer edges of the upper and lower mother substrates 101 and 141. Such a bonding agent is formed to surround the outer edges of the upper and lower mother substrates 101 and 141 to prevent the etching liquid from penetrating between the upper and lower mother substrates 101 and 141 when etching the rear surfaces of the upper and lower mother substrates 101 and 141. To do this. Instead of using such a bonding agent, the present invention uses dummy sealants 210c and 210d. First, since the dummy sealants 210c and 210d are formed at the same time when the first and second sealants 210a and 210b are formed, the upper and lower mother substrates 101 and 141 may not be moved for the bonding operation. In addition, when the bonding agent is applied to the outer edges of the upper and lower mother substrates 101 and 141, the coating thickness of the bonding agent or the type of the bonding agent should be applied according to the panel size of the upper and lower mother substrates 101 and 141. Since the dummy sealants 210c and 210d are applied at the same time when the first and second sealants 210a and 210b are applied, there is no need to change the coating thickness and type like the bonding agent.

In the liquid crystal dropping process (step S3), a liquid crystal layer is formed by dropping a liquid crystal into the liquid crystal space provided by the first sealant 201a on the lower mother substrate 101, and then shown in FIGS. 4A and 4B, 5A, and 5B. As described above, the upper mother substrate 141 and the lower mother substrate 101 are bonded to each other (step S4) to provide a plurality of unit display panels. As described above, the liquid crystal layer may be formed by a liquid crystal dropping method, or may be formed by a liquid crystal injection method. 4A and 4B illustrate a bonding process of upper and lower mother substrates according to the sealant pattern forming process illustrated in FIGS. 2A and 2B, and FIGS. 5A and 5B illustrate the sealant pattern formation illustrated in FIGS. 3A and 3B. Figures showing the bonding process of the upper and lower mother substrate according to the process.

The sealant pattern curing process (step S5) cures the first and second sealants 210a and 210b and the dummy sealants 210c and 210d formed on the lower mother substrate 101 through light (UV) curing or thermal curing. .

Substrate etching process (step S6) is an etching process to form a thin back as the desired thickness while the back side of the upper mother substrate 141, the upper array is not formed and the lower mother substrate 101, the lower array is not formed. do. The etching process may be performed by spraying an etching solution on the rear surfaces of the upper and lower mother substrates 101 and 141 by spraying, or by immersing the bonded upper and lower mother substrates 101 and 141 in an etching solution by dipping. do. At this time, the present invention can prevent the substrate damage by the etching solution during the back etching process of the upper and lower mother substrate (101,141) by the dummy sealant (210c, 201d) formed to surround the outer edge of the upper and lower mother substrate (101,141). have.

This will be described in conjunction with [Table 1]. Table 1 shows the results according to the process time and the defective rate according to the conventional bonding operation and the dummy sealant operation of the present invention when 200 mother substrates capable of forming six 9.7-inch display panels are formed. .

division Bonding operation (conventional) Dummy sealant application (invention) fair Process time 90min 0min Fair staff 6 people 0 people quality Ledger damage rate 6.7% (15 sheets / 200 sheets) 0% (0/200 sheets) Appearance
(scrach, stamp, etc.) 6.61% 5.03%

As shown in Table 1, the process time of the bonding operation surrounding the outer edges of the bonded upper and lower mother substrates 101 and 141 with the bonding agent takes 90 minutes for six workers, and the dummy sealant operation of the present invention includes the first and the first 2 Sealant is formed at the same time, so no operator or separate process time is required. As such, since a separate process is not required, the process time is reduced, and the yield is improved. In other words, it is possible to reduce the amount of time or the number of people required by the conventional bonding operation time.

In addition, when the display panel surrounding the outer periphery is etched, the ledger breakage rate is 6.7%, and the first and second sealants 210a and 210b and the dummy sealants 210c and 210d are bonded together. The ledger breakage rate generated when the display panel is etched is 0%. As shown in Table 1, the failure rate of the ledger which may be caused by forming the dummy sealants 210c and 210d of the present invention does not affect the failure rate increase. In addition, defects in appearance such as scratches or imprints that may occur during the process may be reduced as the bonding process is deleted.

The scribing process (step S7) separates each of the plurality of unit display panels using a diamond wheel along the scribing lines. The non-uniform side surface of the cut portion of the display panel separated by the scribing process may be uniformized by a polishing process using a grinding apparatus.

The liquid crystal cell inspection process (step S6) is attached to each of the separated display panels to determine whether the panel is defective or not, and the module inspection process (step S7) is a test driver for the display panel determined as good in the liquid crystal cell process After installing, determine whether there is a defect.

6A and 6B illustrate a process of forming a sealant pattern in a method of manufacturing a display panel according to a second exemplary embodiment of the present invention, and FIGS. 7A and 7B illustrate a process of forming a sealant pattern shown in FIGS. 6A and 6B. Figures showing the bonding process.

The manufacturing process for manufacturing the display panel according to the second embodiment of the present invention is an array forming process (step S1), a sealant pattern forming process (S2 step), a liquid crystal dropping process (S3 step), a bonding process (S4 step), It includes a sealant pattern curing process (step S5), a substrate etching process (step S6), a scribing process (step S7), a liquid crystal cell inspection process (step S8), and a module inspection process (step S9).

Since the manufacturing process of the display panel according to the second exemplary embodiment of the present invention is the same process except for the sealant pattern forming process (step S2) and the bonding process (step S4), the remaining processes will be omitted.

As shown in FIGS. 6A and 6B, the sealant pattern forming process (step S2) may include at least one of an upper mother substrate 141 having a plurality of color filter arrays and a lower mother substrate 101 having a plurality of thin film transistor arrays. Of the first sealants 210a formed to surround the array area on the mother substrate, the second sealants 210b formed to surround the area where the unit display panel is to be formed, and the upper and lower mother substrates 101 and 141. At least one dummy sealant (210c, 210d) is formed to surround the outer side of any one of the mother substrate in the form of a closed loop.

In detail, as illustrated in FIGS. 6A and 6B, the first sealant 210a is formed in a closed loop on the lower mother substrate 101 so as to surround the image display unit on which the plurality of thin film transistor arrays are formed. The second sealants 210b are formed in a closed loop shape so as to surround the area where the unit display panel is to be formed after the end point 212 of the 210a.

The at least one dummy sealant 210c and 210d may be spaced apart from the end of the first dummy sealant 210c and the outer edge of the lower mother substrate 101 by being spaced apart from the end of the lower mother substrate 101 by the second sealant. And a second dummy sealant 210d formed to surround the fields 210b. The distance between the outer edge of the lower mother substrate 101 and the end of the second dummy sealant 210d is greater than 0 and less than or equal to 10 mm. The upper and lower mother substrates 101 and 141 are formed using the first and second sealants 210a and 210b and the first and second dummy sealants 210c and 210d formed as shown in FIGS. 7A and 7B. To be attached.

At least one dummy sealant may be formed as two first and second dummy sealants 210c and 210d as shown in FIGS. 6A and 6B, and a plurality of dummy sealants are formed in a plurality of 10 mm from the end of the outer edge of the lower mother substrate 101. can do.

8 is a perspective view showing a display panel formed by the manufacturing method according to the present invention.

The display panel 130 illustrated in FIG. 8 includes a thin film transistor substrate 170 and a color filter substrate 180 that are bonded to each other with the liquid crystal layer 176 therebetween.

The color filter substrate 180 includes a black matrix 68, a color filter 162, a common electrode 164, and a column spacer (not shown) sequentially formed on the upper substrate 160.

The black matrix 68 divides the upper substrate 160 into a plurality of cell regions in which the color filter 162 is to be formed, and prevents light interference and external light reflection between adjacent cells. To this end, the black matrix 68 is formed on the upper substrate 160 to overlap at least one of the data line 174, the gate line 182, and the thin film transistor 158 formed on the lower substrate 1. .

The color filter 162 is formed to be divided into red (R), green (G), and blue (B) in the cell region divided by the black matrix 68 to transmit red, green, and blue light, respectively.

The common electrode 164 supplies a common voltage Vcom which is a reference when driving the liquid crystal to the transparent conductive layer.

The column spacer serves to maintain a constant cell gap between the thin film transistor substrate 170 and the color filter substrate 180.

The thin film transistor substrate 170 may include a gate line 182 and a data line 174 intersecting with each other on the lower substrate 1, a thin film transistor 158 adjacent to the intersection portion, and a pixel region having a cross structure. The formed pixel electrode 172 is provided.

The thin film transistor 158 keeps the pixel signal supplied to the data line 174 charged and held in the pixel electrode 172 in response to the scan signal supplied to the gate line 182. To this end, the thin film transistor 158 may include a gate electrode connected to the gate line 182, a source electrode connected to the data line 174, a drain electrode positioned to face the source electrode, and connected to the pixel electrode 172. An ohmic contact layer for ohmic contact with an active layer, a source electrode, and a drain electrode, which forms a channel between the electrode and the drain electrode, is provided.

The pixel electrode 172 charges the pixel signal supplied from the thin film transistor 158 to generate a potential difference from the common electrode 164 formed on the color filter substrate 180. Due to the potential difference, the liquid crystal positioned on the thin film transistor substrate 170 and the color filter substrate 180 is rotated by dielectric anisotropy, and the amount of light incident from the backlight unit via the pixel electrode 172 is adjusted to adjust the color filter substrate ( 180).

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

101,141: upper mother substrate, lower mother substrate 102: gate electrode
108: source electrode 110: drain electrode
112 gate insulating film 114 active layer
116: ohmic contact layer 142: black matrix
144: color filter 210: sealant pattern
210a, 210b: first and second sealants 210c, 210d: dummy sealant

Claims (7)

Forming a plurality of color filter arrays on the upper mother substrate;
Forming a plurality of thin film transistor arrays on the upper mother substrate and the lower mother substrate corresponding to the upper mother substrate;
First sealants formed in a closed loop shape to enclose a plurality of array areas on either one of the upper mother board and the lower mother board, and in a closed loop shape so as to surround an outer portion of an area where a unit display panel is to be formed. Forming a sealant pattern including formed second sealants and at least one dummy sealant formed in a closed loop shape to surround an outer side of one of the upper and lower mother substrates;
Dropping liquid crystal into a space provided by the first sealant and then bonding the upper and lower mother substrates to form a plurality of display panels;
Curing the first and second sealants and the at least one dummy sealant;
Etching back surfaces of the bonded upper and lower mother substrates;
And scribing to separate the unit display panels. The method of claim 1,
And the at least one dummy sealant is formed to surround an end of an outer edge of the lower mother substrate. The method of claim 1,
The at least one dummy sealant is formed to surround the second sealants spaced apart from the end of the outer edge of the lower mother substrate by a predetermined distance. The method of claim 3,
The distance between the end of the outer edge of the lower mother substrate and the end of the dummy sealant is greater than 0 and less than 10mm. The method of claim 1,
The at least one dummy sealant
A first dummy sealant formed to surround an end of the lower mother substrate;
And a second dummy sealant spaced apart from the end of the outer edge of the lower mother substrate by a predetermined distance. The method of claim 5,
The distance between the end of the outer edge of the lower mother substrate and the end of the second dummy sealant is greater than zero and less than 10mm. The method of claim 1,
The at least one dummy sealant is a plurality of display panel manufacturing method, characterized in that formed in the 10mm range at the end of the outer edge of the lower mother substrate.

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