KR20120071743A - Active matrix display - Google Patents

Abstract

The present invention relates to an active matrix display device which can improve image quality by quickly removing ripple components of a common voltage.
The active matrix display device includes at least one first common line connecting common electrodes of liquid crystal cells being charged; A plurality of second common lines connecting common electrodes of uncharged liquid crystal cells; A first bus line to which a first common voltage is applied; A second bus line to which a second common voltage is applied; And sequentially generating scan pulses according to data application time to the liquid crystal cells, switching current paths between the first bus line and the first common line, and arranged in a horizontal line in which a charging operation is activated by the scan pulses. The second common lines arranged on a horizontal line applying the first common voltage to the first common line and switching a current path between the second bus line and the second common lines so that a charging operation is not activated. And a gate driving circuit for applying the second common voltage.

Description

Active Matrix Display

The present invention relates to an active matrix display device which can improve image quality by quickly removing ripple components of a common voltage.

An active matrix display device displays a moving image using a thin film transistor (TFT) as a switching element. Such an active matrix display device is typically a liquid crystal display (Liquid Crystal Display).

The liquid crystal display device includes pixel electrodes to which a data voltage is applied and common electrodes to which the common voltage is applied to the pixel electrodes. The liquid crystal cells are driven by the potential difference between the pixel electrode and the common electrode.

The common electrodes are supplied with the common voltage Vcom through the internal common lines VCL1 parallel to the gate lines and the external common line VCL2 to which the internal common lines VCL1 are connected in parallel. Since the internal common lines VCL1 are coupled to signal lines (data lines and gate lines, etc.) of the panel through parasitic capacitors, the common voltage Vcom on the internal common lines VCL1 is a data voltage and / or The gate voltage (scan pulse) is affected. That is, when the scan pulse (SCAN) or the data voltage (Vdata) changes, the common voltage (Vcom) is not maintained at a constant DC level, but as shown in FIG. The ripple component of the common voltage Vcom adversely affects the charging characteristics of the pixel, and thus must be rapidly attenuated. However, in the conventional liquid crystal display, since the ripple components of the common voltage Vcom due to the voltage change are discharged all at once through a single external common line VCL2, the decay rate of the actual ripple components becomes very slow. When the common voltage Vcom is changed by the ripple components, charging irregularities, horizontal stripes, and the like may occur.

In order to speed up the attenuation of the ripple components, a method of reducing the line resistance R1 of the common lines VCL1 and VCL2 by increasing the line width may be considered. However, in general, the line widths of the common lines VCL1 and VCL2 cannot be widened indefinitely, and even if the line widths are very wide, the ripple components are not attenuated quickly enough.

Accordingly, an object of the present invention is to provide an active matrix display device capable of quickly removing ripple components of a common voltage to improve image quality.

In order to achieve the above object, an active matrix display device according to an embodiment of the present invention includes at least one first common line connecting the common electrodes of the liquid crystal cells being charged; A plurality of second common lines connecting common electrodes of uncharged liquid crystal cells; A first bus line to which a first common voltage is applied; A second bus line to which a second common voltage is applied; And sequentially generating scan pulses according to data application time to the liquid crystal cells, switching current paths between the first bus line and the first common line, and arranged in a horizontal line in which a charging operation is activated by the scan pulses. The second common lines arranged on a horizontal line applying the first common voltage to the first common line and switching a current path between the second bus line and the second common lines so that a charging operation is not activated. And a gate driving circuit for applying the second common voltage.

A display area in a display panel is defined by the liquid crystal cells; The gate driving circuit is embedded in a non-display area of the display panel located outside the display area.

The gate driving circuit includes: a pull-up transistor connected between an input terminal and an output node of a gate shift clock signal and applying the scan pulse having a turn-on level to the output node according to a potential of a Q node; A pull-down transistor connected between the output node and an input terminal of a low potential driving voltage and applying the scan pulse having a turn-off level to the output node according to the potential of the QB node having an opposite potential to the Q node; A first switch element for switching a current path between the first bus line and the first common line according to the potential of the Q node; And a second switch element for switching a current path between the second bus line and the second common lines according to the potential of the QB node.

The gate driving circuit includes: a third switch element connected to be diode-connected between the Q node and the gate terminal of the first switch element; And a fourth switch element for applying the low potential driving voltage to the gate terminal of the first switch element according to the potential of the QB node.

The gate driving circuit includes: a pull-up transistor connected between an input terminal and an output node of a gate shift clock signal and applying the scan pulse having a turn-on level to the output node according to a potential of a Q node; A pull-down transistor connected between the output node and an input terminal of a low potential driving voltage and applying the scan pulse having a turn-off level to the output node according to the potential of the QB node having an opposite potential to the Q node; A first switch element for switching a current path between the first bus line and the first common line according to a potential of the output node; And a second switch element for switching a current path between the second bus line and the second common lines according to the potential of the QB node.

The gate driving circuit includes: a third switch element connected to the diode between the output node and the gate terminal of the first switch element; And a fourth switch element for applying the low potential driving voltage to the gate terminal of the first switch element according to the potential of the QB node.

The gate driving circuit includes: a pull-up transistor connected between an input terminal and an output node of a gate shift clock signal and applying the scan pulse having a turn-on level to the output node according to a potential of a Q node; A pull-down transistor connected between the output node and an input terminal of a low potential driving voltage and applying the scan pulse having a turn-off level to the output node according to the potential of the QB node having an opposite potential to the Q node; A third switch element configured to apply the gate shift clock signal or a high potential driving voltage to a first node according to the potential of the Q node; A first switch element for switching a current path between the first bus line and the first common line according to a potential of the first node; A second switch element for switching a current path between the second bus line and the second common lines according to a potential of the QB node; And a fourth switch element for applying the low potential driving voltage to the first node according to the potential of the QB node.

The active matrix display further includes a power supply circuit for generating the first common voltage and supplying it to the first bus line and generating the second common voltage and supplying the second bus line.

The power supply circuit generates the first common voltage and the second common voltage at the same level or at different levels.

The power supply circuit fixes the second common voltage at a constant level; The first common voltage is swinged at a predetermined period between a first level higher than the second common voltage and a second level lower than the second common voltage.

The active matrix display device according to the present invention comprises a first common line connecting the common electrodes of the liquid crystal cells being charged to the first bus line using a gate driving circuit and a common electrode of the non-charging liquid crystal cells. The two common lines are connected to the second bus line by using a gate driving circuit. Accordingly, the present invention is different from the discharge path of the ripple component present on the second common line by the discharge path of the ripple component existing on the first common line, thereby quickly removing the ripple component on the first common line, the charging unevenness In addition, horizontal stripes can be prevented and image quality can be greatly improved.

1 is a view showing a connection configuration of a conventional common line.
2 shows a ripple component of a common voltage;
3 is a view showing that the ripple components of a common voltage are discharged through a single external common line in a conventional liquid crystal display.
4 illustrates an active matrix display device according to an embodiment of the present invention.
5 is a view schematically showing a connection configuration of a common line according to an embodiment of the present invention.
6 is a diagram illustrating an array of a liquid crystal display panel in which a gate driving circuit is embedded.
FIG. 7 shows a first embodiment of the nth unit shown in FIG. 6;
8 shows a simulation result waveform for FIG.
FIG. 9 shows a second embodiment of the n-th unit shown in FIG. 6;
FIG. 10 shows a third embodiment of the nth unit shown in FIG. 6;
FIG. 11 shows a fourth embodiment of the n-th unit shown in FIG. 6;
12 shows a simulation result waveform for FIG. 11.
FIG. 13 shows a fifth embodiment of the nth unit UNT (n) shown in FIG.
14 and 15 show simulation result waveforms for FIG. 11;

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 15.

4 shows an active matrix display device according to an embodiment of the present invention.

Referring to FIG. 4, the active matrix display device according to the embodiment of the present invention is implemented as a liquid crystal display device. The liquid crystal display device includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a power supply circuit 14.

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 10 includes a plurality of liquid crystal cells Clc arranged in a matrix by a cross structure of a plurality of data lines DL and a plurality of gate lines GL.

The lower glass substrate of the liquid crystal display panel 10 faces the pixel electrodes 1 and the pixel electrodes 1 connected to the data lines DL, the gate lines GL, the TFTs, and the TFTs, respectively. Common electrodes 2 and the like that drive the liquid crystal cells Clc are formed. The common electrodes 2 are connected to the common line CL and may form a storage on common storage capacitor Cst in the pixel array.

Black matrices, color filters, and the like are formed on the upper glass substrate of the liquid crystal display panel 10.

On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal.

The timing controller 11 aligns the input digital video data RGB to the resolution of the liquid crystal display panel 10 and supplies the digital video data RGB to the data driving circuit 12.

The timing controller 11 receives timing signals such as the vertical / horizontal synchronization signals Vsync and Hsync, the data enable signal DE, and the dot clock signal DCLK to control the operation timing of the data driving circuit 12. A data control signal DDC and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13 are generated. The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock signal CLK, a gate output enable signal GOE, and the like. The data timing control signal DDC includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (Polarity: POL), and a source output enable signal (Source Output Enable, SOE) and the like.

The data driving circuit 12 latches the digital video data RGB under the control of the timing controller 11, and then converts the latched data into analog positive / negative data voltages and supplies them to the data lines DL. .

The gate driving circuit 13 sequentially generates scan pulses under the control of the timing controller 11 and supplies them to the gate lines GL. The gate driving circuit 13 supplies the first common voltage Vcom1 to the common line CL disposed on the horizontal line where the charging operation is activated by the scan pulse, and supplies the first common voltage Vcom1 to the horizontal lines where the charging operation is not activated. The second common voltage Vcom2 is supplied to the common line CL.

The gate driving circuit 13 includes a level shifter and a gate shift register. The level shifter level shifts the TTL logic level voltages of at least two phases of the gate shift clocks CLK input from the timing controller 11 to a gate high voltage and a gate low voltage. The gate shift register includes a plurality of units that sequentially output the scan pulse by shifting the gate start pulse GSP according to the gate shift clock CLK. The gate driving circuit 13 may be directly formed on the lower substrate of the liquid crystal display panel 10 by a gate in panel (GIP) method. In the GIP method, the level shifter is mounted together with the timing controller 11 on a control PCB (not shown), and the gate shift register is embedded on the lower substrate of the liquid crystal display panel 10. Hereinafter, for convenience of description, it will be described that the gate driving circuit 13 is embedded in the GIP method, but it should be noted that the gate shift register is embedded in the GIP method.

The power supply circuit 14 generates the first common voltage Vcom1 and the second common voltage Vcom2. The power supply circuit 14 supplies the first common voltage Vcom1 to the gate driving circuit 13 through the first bus wiring, and supplies the second common voltage Vcom2 through the second bus wiring. 13). The power supply circuit 14 may generate the first common voltage Vcom1 and the second common voltage Vcom2 at the same level or at different levels. When the first common voltage Vcom1 and the second common voltage Vcom2 are generated at different levels, the power supply circuit 14 may swing the first common voltage Vcom1 at a predetermined period. For example, the power supply circuit 14 fixes the second common voltage Vcom2 at a constant level, and sets the first common voltage Vcom1 to the second common voltage Vcom2 during the nth (n is a positive integer) frame period. The first common voltage Vcom1 may be generated at a second level lower than the second common voltage Vcom2 during the n + 1 frame period. On the other hand, when the liquid crystal display panel 10 is driven by the line inversion method, the power supply circuit 14 fixes the second common voltage Vcom2 to a constant level and sets the first common voltage Vcom1 to one horizontal period. The cycle may swing between the first level and the second level. In this case, the output swing width of the data voltage is reduced, so that power consumption in the data driving circuit 12 can be reduced.

5 schematically shows a connection configuration of a common line for rapidly attenuating a ripple component of a common voltage.

Referring to FIG. 5, the common line CL includes a first common line CL1 and second common lines CL2 connecting the common electrodes of the liquid crystal cells in a horizontal line unit.

The first common line CL1 connecting the common electrodes of the liquid crystal cells being charged is switched to be connected to the first bus line BL1 by the gate driving circuit 13, and connects the common electrodes of the non-charging liquid crystal cells. The second common lines CL2 are switched to be connected to the second bus line BL2 by the gate driving circuit 13. For example, assuming that the liquid crystal cells arranged on the nth horizontal line HL (n) are in a charged state, the common line arranged on the nth horizontal line HL (n) is referred to as the first common line CL1. Function lines connected to the first bus line BL1 and arranged on the non-charged horizontal lines HL (n-2), HL (n + 2), etc. are connected to the second common lines CL2. It is connected to the second bus line BL2. As a result, the ripple component on the first common line CL1 is discharged through the first discharge path including the first bus line BL1, and the ripple component on the second common lines CL2 is the second bus line BL2. Is discharged through the second discharge path including). When the discharge paths of the ripple components are different from each other, the line resistance Rl on the first discharge path is significantly reduced, so that the ripple component on the first common line CL1 is rapidly attenuated.

In order to eliminate the filling irregularity and the horizontal stripes, the ripple component on the first common line CL1 should be removed quickly. When the common voltage applied to the liquid crystal cells being charged is changed by the ripple component, it is difficult to set the potential difference between the pixel electrode and the common electrode to the desired value in the liquid crystal cells being charged. This is because the pixel electrodes of the charging liquid crystal cells are electrically connected to each data line. On the other hand, since the non-charging liquid crystal cells are floating from each data line, they are not affected by the variation of the common voltage. Since the uncharged liquid crystal cells are changed in the same direction as the potential variation of the common electrode by the coupling effect, the existing potential difference can be maintained as it is. Therefore, even if most of the second common lines CL2 are connected to the second bus line BL2, the image quality deterioration does not occur.

6 shows an array of the liquid crystal display panel 10 in which the gate driving circuit 13 is incorporated.

Referring to FIG. 6, a pixel array is formed in a display area AA in which an image is displayed on the liquid crystal display panel 10, and a gate driving circuit 13 is formed in a non-display area NAA outside the display area AA. Is formed.

The gate driving circuit 13 receives a plurality of driving voltages Vdd and Vss, shifts the gate start pulse GSP according to the gate shift clock CLK, and sequentially outputs the scan pulses Vg. UNT). Each of the units UNT receives the first common voltage Vcom1 through the first bus line BL1, receives the second common voltage Vcom2 through the second bus line BL2, and scan pulses. The first common voltage Vcom1 is supplied to the common line disposed on the horizontal line where the charging operation is activated by Vg, and the second common voltage is applied to the common line disposed on most horizontal lines where the charging operation is not activated. Supply (Vcom2). The common line to which the first common voltage Vcom1 is applied by any one of the units UNT functions as a first common line CL1 connecting the common electrodes of the liquid crystal cells being charged. Common lines to which the second common voltage Vcom2 is applied by the units UNT function as second common lines CL2 connecting common electrodes of non-charged liquid crystal cells.

FIG. 7 shows a first embodiment of the nth unit UNT (n) shown in FIG. 6. FIG. 8 shows a simulation result waveform for FIG. 7. In FIG. 8, 'VQ' represents a potential of the Q node NQ, and 'VQB' represents a QB node NQB, respectively.

7 and 8, the n th unit UNT (n) according to the first embodiment may include a first transistor T1, a second transistor T2, a pull-up transistor Tpu, and a pull-down transistor Tpd. The first switch element S1 and the second switch element S2 are included.

The first transistor T1 is switched according to the scan pulse PREV of one of the front end units to apply the high potential driving voltage Vdd to the Q node NQ to activate the Q node NQ to the first level. Let's do it. The inverter INV deactivates the QB node NQB when the Q node NQ is activated.

The second transistor T2 is switched according to the scan pulse NEXT of one of the subsequent units to apply the low potential driving voltage Vss to the Q node NQ to deactivate the Q node NQ. The inverter INV activates the QB node NQB when the Q node NQ is deactivated.

The pull-up transistor Tpu applies the gate shift clock signal CLK to the output node NO within a period during which the Q node NQ is boot-strapping to a second level higher than the first level. . The gate shift clock signal CLK applied to the output node NO is supplied to the nth gate line GL (n) as the nth scan pulse Vg (n) of the VGH level (turn on level).

The pull-down transistor Tpd applies the low potential driving voltage Vss to the output node NO during the period in which the QB node NQB is activated. The low potential driving voltage Vss applied to the output node NO is supplied to the nth gate line GL (n) as the nth scan pulse Vg (n) of the VGL level (turn off level).

The first switch element S1 has a gate terminal connected to the Q node NQ, a drain terminal connected to the first bus line BL1, and a source terminal connected to the nth common line CL (n). do. The first switch element S1 is turned on when the Q node NQ is activated to the first level to electrically connect the first bus line BL1 to the nth common line CL (n), thereby providing the nth The first common voltage Vcom1 is applied to the common line CL (n). In this case, the nth common line CL (n) may function as the first common line CL1 described with reference to FIG. 6.

The second switch element S2 has a gate terminal connected to the QB node NQB, a drain terminal connected to the second bus line BL2, and a source terminal connected to the nth common line CL (n). do. The second switch element S2 is turned on when the QB node NQB is activated to electrically connect the second bus line BL2 to the nth common line CL (n), thereby providing the nth common line CL. The second common voltage Vcom2 is applied to (n). In this case, the nth common line CL (n) may function as the second common line CL2 described with reference to FIG. 6.

In FIG. 8, the first common voltage Vcom1 is inputted to the nth unit UNT (n) at 5V and the second common voltage Vcom2 at 8V, respectively. As can be easily seen through FIG. 8, the common voltage Vcom (n) applied to the nth common line CL (n) through the nth unit UNT (n) is the Q node NQ. The first common voltage Vcom1 is 5V during the period of activation to the level, and 8V the second common voltage Vcom2 during the period of activation of the QB node NQB.

FIG. 9 shows a second embodiment of the nth unit UNT (n) shown in FIG.

Referring to FIG. 9, the n th unit UNT (n) according to the second embodiment may include a first transistor T1, a second transistor T2, a pull-up transistor Tpu, a pull-down transistor Tpd, and a first transistor. The switch element S1, the second switch element S2, the third switch element S3 and the fourth switch element S4 are included.

The first transistor T1, the second transistor T2, the pull-up transistor Tpu, the pull-down transistor Tpd, the first switch element S1, and the second switch element S2 are substantially the same as those described with reference to FIG. 7. Do.

The third switch element S3 is connected to be diode-connected between the Q node NQ and the gate terminal of the first switch element S1. The third switch element S3 increases the bootstraping effect of the Q node NQ by reducing the capacitance of the parasitic capacitance connected to the Q node NQ.

The fourth switch element S4 has a gate terminal connected to the QB node NQB, and a drain terminal connected to the first node NX between the gate terminal of the first switch element S1 and the third switch element S3. And a source terminal to which the low potential driving voltage Vss is input. The fourth switch element S4 applies the low potential driving voltage Vss to the first node NX when the QB node NQB is activated.

FIG. 10 shows a third embodiment of the nth unit UNT (n) shown in FIG.

Referring to FIG. 10, the n th unit UNT (n) according to the third embodiment may include a first transistor T1, a second transistor T2, a pull-up transistor Tpu, a pull-down transistor Tpd, and a first transistor. The switch element S1 and the second switch element S2 are included.

The first transistor T1, the second transistor T2, the pull-up transistor Tpu, the pull-down transistor Tpd, and the second switch element S2 are substantially the same as those described with reference to FIG. 7.

The first switch element S1 has a gate terminal connected to the output node NO, a drain terminal connected to the first bus line BL1, and a source terminal connected to the nth common line CL (n). do. The first switch element S1 is turned on from the time when the gate shift clock signal CLK is applied to the output node NO to the time when the QB node NQB is activated, so that the first switch element S1 is shared with the n-th bus line BL1. By electrically connecting the line CL (n), the first common voltage Vcom1 is applied to the nth common line CL (n). In this case, the nth common line CL (n) may function as the first common line CL1 described with reference to FIG. 6.

FIG. 11 shows a fourth embodiment of the nth unit UNT (n) shown in FIG. 6. 12 shows a simulation result waveform for FIG. 11. In FIG. 12, 'VQ' represents a potential of the Q node NQ, 'VQB' represents a QB node NQB, and 'VNX' represents a potential of the first node NX, respectively.

11 and 12, the n th unit UNT (n) according to the fourth embodiment includes a first transistor T1, a second transistor T2, a pull-up transistor Tpu, and a pull-down transistor Tpd. And a first switch element S1 and a second switch element S2, a third switch element S3, and a fourth switch element S4.

The first transistor T1, the second transistor T2, the pull-up transistor Tpu, the pull-down transistor Tpd, and the second switch element S2 are substantially the same as those described with reference to FIG. 7.

The first switch element S1 has a gate terminal connected to the first node NX, a drain terminal connected to the first bus line BL1, and a source terminal connected to the nth common line CL (n). Equipped. The first switch element S1 is turned on from the time when the gate shift clock signal CLK is applied to the output node NO to the time when the QB node NQB is activated, so that the first switch element S1 is shared with the n-th bus line BL1. By electrically connecting the line CL (n), the first common voltage Vcom1 is applied to the nth common line CL (n). In this case, the nth common line CL (n) may function as the first common line CL1 described with reference to FIG. 6.

The third switch element S3 is connected to be diode-connected between the output node NO and the gate terminal of the first switch element S1. The third switch element S3 stabilizes the output node NO by reducing the capacitance of the parasitic capacitance connected to the output node NO.

The fourth switch element S4 has a gate terminal connected to the QB node NQB, and a drain terminal connected to the first node NX between the gate terminal of the first switch element S1 and the third switch element S3. And a source terminal to which the low potential driving voltage Vss is input. The fourth switch element S4 applies the low potential driving voltage Vss to the first node NX when the QB node NQB is activated.

In FIG. 12, the first common voltage Vcom1 is 11V and the second common voltage Vcom2 is 8V, respectively, to the nth unit UNT (n). As can be easily seen from FIG. 12, the common voltage Vcom (n) applied to the nth common line CL (n) through the nth unit UNT (n) is gate shifted to the output node NO. 8V, which is 11V of the first common voltage Vcom1 and a second common voltage Vcom2 during the activation of the QB node NQB, from the time when the clock signal CLK is applied to the time when the QB node NQB is activated. to be.

FIG. 13 shows a fifth embodiment of the nth unit UNT (n) shown in FIG. 14 and 15 show simulation result waveforms for FIG. 11. 14 and 15, 'VQ' represents the potential of the Q node NQ, 'VQB' represents the QB node NQB, and 'VNX' represents the potential of the first node NX, respectively.

13 to 15, the n th unit UNT (n) according to the fifth embodiment includes a first transistor T1, a second transistor T2, a pull-up transistor Tpu, and a pull-down transistor Tpd. And a first switch element S1 and a second switch element S2, a third switch element S3, and a fourth switch element S4.

The first transistor T1, the second transistor T2, the pull-up transistor Tpu, the pull-down transistor Tpd, and the second switch element S2 are substantially the same as those described with reference to FIG. 7.

The third switch element S3 includes a gate terminal connected to the Q node NQ, a drain terminal to which the gate shift clock signal CLK or the high potential driving voltage Vdd is input, and a source connected to the first node NX. A terminal is provided. The third switch element S3 is turned on when the Q node NQ is activated to the first level to apply the gate shift clock signal CLK or the high potential driving voltage Vdd to the first node NX.

The first switch element S1 has a gate terminal connected to the first node NX, a drain terminal connected to the first bus line BL1, and a source terminal connected to the nth common line CL (n). Equipped. When the gate shift clock signal CLK is applied to the first node NX, the first switch element S1 starts from the time when the gate shift clock signal CLK is applied to the first node NX as shown in FIG. 14. It is turned on until the QB node NQB is activated to electrically connect the first bus line BL1 and the n-th common line CL (n) to the first to the nth common line CL (n). The common voltage Vcom1 is applied. When the high potential driving voltage Vdd is applied to the first node NX, the first switch element S1 is turned on during the period in which the Q node NQ is activated to the first level as shown in FIG. The first common voltage Vcom1 is applied to the nth common line CL (n) by electrically connecting the bus line BL1 and the nth common line CL (n). In this case, the nth common line CL (n) may function as the first common line CL1 described with reference to FIG. 6.

The fourth switch element S4 has a gate terminal connected to the QB node NQB, and a drain terminal connected to the first node NX between the gate terminal of the first switch element S1 and the third switch element S3. And a source terminal to which the low potential driving voltage Vss is input. The fourth switch element S4 applies the low potential driving voltage Vss to the first node NX when the QB node NQB is activated.

In FIG. 14, the first common voltage Vcom1 is 5V and the second common voltage Vcom2 is 8V, respectively, and is input to the nth unit UNT (n). As can be easily seen through FIG. 14, the common voltage Vcom (n) applied to the nth common line CL (n) through the nth unit UNT (n) is gated to the first node NX. From the time when the shift clock signal CLK is applied to the time when the QB node NQB is activated, it is 5 V, which is the first common voltage Vcom1, and the second common voltage Vcom2 during the period when the QB node NQB is activated. 8V.

In FIG. 15, the first common voltage Vcom1 is 11V and the second common voltage Vcom2 is 8V, respectively, to the nth unit UNT (n). As can be easily seen from FIG. 15, the common voltage Vcom (n) applied to the nth common line CL (n) through the nth unit UNT (n) is the Q node NQ. It is 11V which is the first common voltage Vcom1 during the period of activation to the level, and 8V which is the second common voltage Vcom2 during the period when the QB node NQB is activated.

In the above description, it is described that "the first common voltage Vcom1 is supplied to the common line connected to the liquid crystal cells in which the charging operation is activated by the scan pulse Vg." Here, it should be noted that that "supplied to the common line connected to the liquid crystal cells in which the charging operation is activated" does not mean that "supplied only to the common line connected to the liquid crystal cells in which the charging operation is activated". In the present invention, the first common voltage Vcom1 includes a common line connected to the liquid crystal cells of the horizontal line being charged, and includes at least one horizontal line adjacent to the horizontal line being charged vertically. It can also be supplied to a common line connected to the liquid crystal cells of. This is because the output period of the first common voltage Vcom1 is wider than the output period of the scan pulse Vg (n), as shown in the simulation results of FIGS. 8, 12, 14, and 15. For example, in the circuits of FIGS. 7 and 9, as shown in FIG. 8, since the output period of the first common voltage Vcom1 is wider by one horizontal period and one horizontal period later than the scan pulse Vg (n), the first period is wide. The common voltage Vcom1 may be supplied to the common line disposed on the nth horizontal line and the common line disposed on the n−1 and n + 1th horizontal lines. 10 and 11, since the output period of the first common voltage Vcom1 is wider by one horizontal period than the scan pulse Vg (n), as shown in FIG. 12, the first common voltage Vcom1. May be supplied to the common line disposed on the n-th horizontal line and the common line disposed on the n-th horizontal line. In addition, when the gate shift clock signal CLK is input in FIG. 13, the output period of the first common voltage Vcom1 is wider by one horizontal period than the scan pulse Vg (n) as shown in FIG. 14. The first common voltage Vcom1 may be supplied to the common line disposed on the n−1 th horizontal line and the common line disposed on the n th horizontal line. In addition, when the high potential driving voltage Vdd is input in FIG. 13, the output period of the first common voltage Vcom1 is one horizontal period forward and one horizontal period backward compared to the scan pulse Vg (n) as shown in FIG. 15. Since the period is wide, the first common voltage Vcom1 may be supplied to the common line disposed on the nth horizontal line and the common line disposed on the n−1 and n + 1th horizontal lines.

As described above, the active matrix display device according to the present invention connects the first common line connecting the common electrodes of the liquid crystal cells being charged to the first bus line using the gate driving circuit, and the common of the non-charging liquid crystal cells. The second common lines connecting the electrodes are connected to the second bus line by using a gate driving circuit. Accordingly, the present invention is different from the discharge path of the ripple component present on the second common line by the discharge path of the ripple component existing on the first common line, thereby quickly removing the ripple component on the first common line, the charging unevenness In addition, horizontal stripes can be prevented and image quality can be greatly improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10 liquid crystal display panel 11 timing controller
12; Data driving circuit 13: gate driving circuit
14: power circuit

Claims (10)

At least one first common line connecting common electrodes of the liquid crystal cells being charged;
A plurality of second common lines connecting common electrodes of uncharged liquid crystal cells;
A first bus line to which a first common voltage is applied;
A second bus line to which a second common voltage is applied; And
Scan pulses are sequentially generated in accordance with the time point at which data are applied to the liquid crystal cells, and the current paths between the first bus line and the first common line are switched to arrange the horizontal lines in which a charging operation is activated by the scan pulses. The first common voltage is applied to a first common line, and the current path between the second bus line and the second common lines is switched to the second common lines arranged in a horizontal line in which a charging operation is not activated. And a gate driving circuit applying the second common voltage. The method of claim 1,
A display area in a display panel is defined by the liquid crystal cells;
And the gate driving circuit is embedded in a non-display area of the display panel located outside the display area. The method of claim 2,
The gate driving circuit,
A pull-up transistor connected between an input terminal of the gate shift clock signal and an output node and configured to apply the scan pulse having a turn-on level to the output node according to a potential of a Q node;
A pull-down transistor connected between the output node and an input terminal of a low potential driving voltage and applying the scan pulse having a turn-off level to the output node according to the potential of the QB node having an opposite potential to the Q node;
A first switch element for switching a current path between the first bus line and the first common line according to the potential of the Q node; And
And a second switch element for switching a current path between the second bus line and the second common lines according to the potential of the QB node. The method of claim 3, wherein
The gate driving circuit,
A third switch element connected to the diode node between the Q node and the gate terminal of the first switch element; And
And a fourth switch element for applying the low potential driving voltage to a gate terminal of the first switch element according to the potential of the QB node. The method of claim 2,
The gate driving circuit,
A pull-up transistor connected between an input terminal of the gate shift clock signal and an output node and configured to apply the scan pulse having a turn-on level to the output node according to a potential of a Q node;
A pull-down transistor connected between the output node and an input terminal of a low potential driving voltage and applying the scan pulse having a turn-off level to the output node according to the potential of the QB node having an opposite potential to the Q node;
A first switch element for switching a current path between the first bus line and the first common line according to a potential of the output node; And
And a second switch element for switching a current path between the second bus line and the second common lines according to the potential of the QB node. The method of claim 5, wherein
The gate driving circuit,
A third switch element connected to the diode between the output node and the gate terminal of the first switch element; And
And a fourth switch element for applying the low potential driving voltage to a gate terminal of the first switch element according to the potential of the QB node. The method of claim 2,
The gate driving circuit,
A pull-up transistor connected between an input terminal of the gate shift clock signal and an output node and configured to apply the scan pulse having a turn-on level to the output node according to a potential of a Q node;
A pull-down transistor connected between the output node and an input terminal of a low potential driving voltage and applying the scan pulse having a turn-off level to the output node according to the potential of the QB node having an opposite potential to the Q node;
A third switch element configured to apply the gate shift clock signal or a high potential driving voltage to a first node according to the potential of the Q node;
A first switch element for switching a current path between the first bus line and the first common line according to a potential of the first node;
A second switch element for switching a current path between the second bus line and the second common lines according to a potential of the QB node; And
And a fourth switch element for applying the low potential driving voltage to the first node according to the potential of the QB node. The method of claim 1,
And a power supply circuit for generating the first common voltage and supplying the first common line to the first bus line, and generating the second common voltage and supplying the second common voltage to the second bus line. The method of claim 8,
And the power supply circuit generates the first common voltage and the second common voltage at the same level or at different levels. The method of claim 8,
The power supply circuit,
Fix the second common voltage to a constant level;
And swinging the first common voltage periodically for a predetermined period between a first level higher than the second common voltage and a second level lower than the second common voltage.

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