KR20120069115A

KR20120069115A - Semiconductor memory device and method for operating thereof

Info

Publication number: KR20120069115A
Application number: KR1020100130519A
Authority: KR
Inventors: 김명수
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2010-12-20
Filing date: 2010-12-20
Publication date: 2012-06-28

Abstract

PURPOSE: A semiconductor memory device and an operating method thereof are provided to reduce interference by decreasing a threshold voltage difference between memory cells in the following program operation. CONSTITUTION: A page buffer group(180) outputs a comparison result by comparing an erase verification voltage with threshold voltages of memory cells connected to a word line in which an erase verification operation is performed. A pass/fail check circuit(190) outputs a signal for checking whether a memory cell with a threshold voltage higher than a verification voltage exists in each world line by using comparison result data. A logic circuit(200) stores whether the memory cell with the threshold voltage higher than the verification voltage exists in each world line as a result value and outputs a signal for determining a voltage applied to each word line in the following erase operation according to the stored result value.

Description

Semiconductor memory device and method for operating same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device for performing an erase operation.

The NAND flash memory performs an erase operation in blocks. During the erase operation, 0 V is applied to all word lines WL, and a high voltage called an erase voltage Verase is applied to the well to erase the data stored in the memory cell.

An erase verify operation is performed to determine whether an erase is performed. 0 V is applied to all word lines to determine an erase pass / fail depending on whether a current flows through a cell string. do.

Since the verify operation is performed in units of blocks, even if all memory cells connected to a specific word line are erased, if the memory cells connected to the remaining word lines have not yet been erased, the memory block becomes an erase fail. In this case, the erase voltage is increased and the erase operation is performed again with a higher voltage than before. The erased memory cells also receive a high erase voltage pulse. As a result, the threshold voltage distribution is shifted to the left side more to the left to widen the threshold voltage distribution after the erase operation. In this case, there is a problem in that interference between the threshold voltages is increased during the program operation.

According to an exemplary embodiment of the present invention, an erase verification operation is performed on a word line basis and a positive voltage is applied to a word line that is erased during the next erase operation by using pass / fail information for each word line. Widening can be prevented.

A method of operating a semiconductor memory device according to an exemplary embodiment of the present invention may include performing an erase operation on a memory block including memory cells connected to a plurality of word lines; Sequentially performing an erase verify operation from memory cells connected to the first word line to memory cells connected to the last word line to check whether a memory cell whose threshold voltage is higher than the verify voltage exists; And performing an additional erase operation by differently setting a voltage applied to the word line according to whether a memory cell whose threshold voltage is higher than the verify voltage is present.

In the erasing operation of the memory block, a ground level voltage is applied to all word lines.

When the erase verify operation is performed, a verify voltage is applied to selected word lines and a positive voltage is applied to unselected word lines.

The verify voltage is a ground voltage, and the positive voltage is a voltage for turning on memory cells.

After the erase verification operation is performed, the next erase operation is performed by increasing the magnitude of the erase voltage.

The erase prohibition voltage is applied to a word line in which no memory cell having a threshold voltage higher than the verify voltage exists in the next erase operation.

The erase prohibition voltage increases in proportion to the number of erase operations performed on the memory cells connected to the word line.

The erase prohibition voltage increases in proportion to the magnitude of the erase voltage applied to the word lines during the erase operation.

In an embodiment, a semiconductor memory device may include a memory array including memory cells connected to a plurality of word lines; Comparison results of threshold voltages and erase verify voltages of memory cells connected to a word line where the erase verify operation is performed while the erase verify operations of the memory cells connected to the first word line to the memory cells connected to the last word line are sequentially performed A page buffer group configured to output data; A pass / fail check circuit configured to output a signal which checks whether a memory cell whose threshold voltage is higher than a verify voltage exists for each word line using the comparison result data; And storing, as a result value, whether or not a memory cell having a threshold voltage higher than a verify voltage exists in each word line, and outputting a signal for determining a voltage to be applied to each word line in a next erase operation according to the stored result value. And a logic circuit configured to.

When voltage information to be applied to each word line is input from the logic circuit, the voltage supply circuit may further generate a voltage to be applied to each word line and supply the voltage to each word line.

The logic circuit outputs voltage information to the voltage supply circuit to apply an erase prohibition voltage to a word line in which there is no memory cell in which the threshold voltage is higher than a verify voltage.

When the next erase operation is performed after the erase verify operation is performed, the voltage supply circuit increases and applies the magnitude of the erase voltage applied to the word lines.

According to an exemplary embodiment of the present invention, an erase verification operation is performed on a word line basis, and a voltage higher than 0 V is applied to an erase pass word line during the next erase operation by using erase pass / fail information for each word line. Reduce the voltage difference between the well and the control gate of the memory cell.

Therefore, the threshold voltage distribution may be prevented from being widened after the erase operation is performed, thereby reducing the interference voltage between the memory cells during the next program operation, thereby reducing interference.

1 is a flowchart illustrating a method of operating a semiconductor memory device according to a first embodiment of the present invention.
2 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention.
3 is a flowchart illustrating a method of operating a semiconductor memory device according to a second embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between .

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise. Also, the terms " part, "" module," and " module ", etc. in the specification mean a unit for processing at least one function or operation and may be implemented by hardware or software or a combination of hardware and software have.

1 is a flowchart illustrating a method of operating a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 1, in the method of operating a semiconductor memory device according to the first exemplary embodiment, a voltage of 0 V (ie, a ground voltage) is first applied to all word lines WL (step 110).

Then, an erase voltage Verase is applied to a well to perform an erase operation (step 120). In this case, the erase voltage should be high enough to allow electrons stored in the floating gate of the memory cell to escape by F-N tunneling, for example, 20V. Therefore, when the erase operation is performed by applying the erase voltage Verase to the well, the data stored in the memory cell is erased. This erase operation is performed in units of memory blocks.

Next, an erase verification operation is performed by applying a verification voltage of 0 V to all word lines WL (step 130). The threshold voltage Vth of the memory cells is lowered by the erase operation. The erase verification operation is performed to confirm whether the threshold voltage Vth of the memory cells is lower than 0V as a result of the erase operation.

For a plurality of memory cells included in the memory block by the erase verify operation, it may be determined whether a memory cell having a threshold voltage Vth higher than the verify voltage exists (step 140). If there is no memory cell whose threshold voltage Vth is higher than the verify voltage, the erase operation is passed and the operation ends. If there is a memory cell whose threshold voltage Vth is higher than the verify voltage, the erase operation is not passed. In this case, it is checked whether the current erase operation corresponds to the last erase loop (step 150). In the case of the last erase loop, since the erase operation can no longer be performed, the memory block is erase-failed (step 160) and the operation is terminated.

If the current erase operation does not correspond to the last erase loop, the erase voltage Verase is increased (step 170) to perform the erase operation again.

As described above, when the verify operation is performed in units of blocks, the erased memory cells also receive a high erase voltage pulse during the next erase operation. As a result, the threshold voltage distribution may be shifted to the left to widen the threshold voltage distribution after the erase operation.

2 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention.

2, a semiconductor memory device 100 according to an embodiment of the present invention includes a memory array 110, a page buffer group 180, a pass / fail check circuit 190, and a logic circuit 200. do. In addition, the operation circuit group may include a voltage supply circuit (120, 130, 140, 150, 160), and may further include a control circuit 170 configured to control the voltage supply circuit.

The voltage supply circuit includes a voltage generator circuit 120, a global word line switch 130, a high voltage switch circuit 140, a block decoder 150, and a block switch 160.

The memory array 110 includes a plurality of memory blocks. 2 shows the first and last memory blocks. Each memory block contains a number of strings. Each string includes a source select transistor SST connected to a common source line CSL, a plurality of memory cells Ca0 to Can, and a drain select transistor DST connected to a bit line BL1. The gate of the source select transistor SST is connected to the source select line SSL, the gates of the memory cells Ca0 to Can are respectively connected to the word lines WL0 to WLn, and the gate of the drain select transistor DST. Is connected to the drain select line DSL. The strings are respectively connected to the corresponding bit lines BL1 to BLk and commonly connected to the common source line CSL.

The control circuit 170 internally outputs the program operation signal PGM, the read operation signal READ or the erase operation signal ERASE in response to the command signal CMD, and internally in response to the address signal ADD. The page address signal PAGE ADD and the block address signal BLK ADD are output. The control circuit 170 also outputs an enable signal for turning on the switching elements in the high voltage switch circuit 140.

The voltage supply circuits 120, 130, 140, 150, and 160 may generate operating voltages required for program operation, erase operation, or read operation of the memory cells according to the signals READ, PGE, ERASE, and RADD of the control circuit 170. The drain select line DSL, the word lines WL [n: 0], and the source select line SSL are supplied to the drain select line DSL. The voltage supply circuit includes a voltage generator circuit 120, a global word line switch 130, a high voltage switch circuit 140, a block decoder 150, and a block switch 160.

The voltage generation circuit 120 outputs operating voltages for programming, reading, or erasing memory cells in response to the operation signals PGM, READ, and ERASE, which are internal command signals of the control circuit 170.

In response to the page address signal PAGE ADD of the control circuit 170, the global word line switch 130 may apply the operating voltages generated by the voltage generation circuit 120 to the global drain select line GDSL and the global word lines. GWL [n: 0]) and the global source select line GSSL. For example, when erasing the memory cells, operating voltages (eg, Verase, Vpass, and Vverify) for erasing are output to the global lines GDSL, GWL [n: 0], and GSSL.

The high voltage switch circuit 140 receives the operating voltages of the memory cells from the voltage generator circuit 120 and transfers the operating voltages of the memory cells to the block decoder 150.

The block decoder 150 receives the block address BLK ADD from the control circuit 170 and uses the voltage received from the high voltage switch circuit 140 as the block selection signals BSEL [0] to BSEL [i-1]. Output The memory block is selected according to the block selection signals BSEL [0] to BSEL [i-1] that are output.

The block switches 160 <0> to 160 <i-1> are global lines GDSL and GWL [according to the block select signals BSEL [0] to BSEL [i-1] output from the block decoder 150. n: 0], GSSL) and local lines (DSL, WL [n: 0], SSL). Through this, the operating voltages generated by the voltage generation circuit 120 are transferred to strings of the selected memory block among the memory blocks of the memory array 110. That is, operating voltages are applied to local lines DSL, WL [n: 0], SSL of the selected memory block. The block switches 160 <0> to 160 <i-1> include a plurality of switching elements having a positive threshold voltage. The switching elements may be implemented as high voltage NMOS transistors (hereinafter referred to as pass transistors).

The page buffer group 180 includes page buffers (not shown) connected to the bit lines BL1 to BLk, respectively. In response to the control signals PB SIGNALS of the control circuit 170, voltages necessary for storing data in the cells Ca0,..., Ck0 are applied to the bit lines BL1 to BLk, respectively. In detail, the page buffer group 180 may precharge the bit lines BL1 to BLk or may precharge the bit lines BL1 to BLk during the program operation, the erase operation, or the read operation of the cells Ca0,..., Ck0. Latches data corresponding to the threshold voltage levels of the detected memory cells Ca0,..., Ck0 according to the change in voltage. That is, the page buffer group 180 adjusts the voltages of the bit lines BL1 to BLk according to data stored in the memory cells Ca0,..., Ck0, and controls the memory cells Ca0,..., Ck0. Detects data stored in).

The page buffer group 180 is a memory connected to a word line to which an erase verify operation is performed while erase verification operations of memory cells connected to the first word line WL0 to memory cells connected to the last word line WLn are sequentially performed. And outputs the result of the comparison of the threshold voltages of the cells and the erase verification voltage data CS.

The pass / fail check circuit 190 checks whether an error cell having a threshold voltage lower than a target voltage (that is, a verify voltage) among the programmed memory cells is generated as a check signal in a program verify operation performed after the program operation. Output The pass / fail check circuit 190 determines whether a memory cell having a threshold voltage higher than the verify voltage exists for each word line among the memory cells erased using the comparison result data CS in the erase verify operation performed after the erase operation. Check and output the result as a check signal (ERAVERPF <n: 0>). In addition, the pass / fail check circuit 190 also counts the number of error cells generated when an error cell occurs and outputs a counting result as a counting signal.

The logic circuit 200 stores, as a result value, whether or not a memory cell having a threshold voltage higher than the verify voltage exists in each word line, and determines a voltage to be applied to each word line in the next erase operation according to the stored result value. It is configured to output a signal (Wordline Voltage Determining Signal, WVDS).

Hereinafter, an operation method for performing an erase verification operation for each word line in the semiconductor memory device described above will be described.

3 is a flowchart illustrating a method of operating a semiconductor memory device according to a second embodiment of the present invention.

2 and 3, in the method of operating a semiconductor memory device according to the second embodiment of the present invention, first, a voltage of 0 V (ie, ground) is applied to all word lines WL0-WLn in the voltage supply circuit 130. Voltage) (step 310).

Next, an erase voltage Verase is applied to a well to perform an erase operation (step 320). In this case, the erase voltage applied is a high voltage, for example, 20V.

In the second embodiment of the present invention, the erase operation is performed in units of memory blocks, but the erase verify operation is performed in units of memory cells connected to a word line. That is, the erase verification operation is sequentially performed from memory cells connected to the first word line WL0 to memory cells connected to the last word line WLn in order to check whether a memory cell having a threshold voltage higher than the verify voltage exists. .

In more detail, first, a voltage of 0 V is applied to the first word line WL0 to perform an erase verification operation on memory cells connected to the first word line WL0, and the remaining word lines WL1-WLn are applied to the first word line WL0. A pass voltage Vpass (pass voltage is a voltage capable of turning on the memory cell) is applied to the pass voltage (step 330).

Thereafter, whether a memory cell having a threshold voltage higher than the verify voltage exists among the memory cells connected to the first word line WL0 is stored as a result value (step 335). In detail, when an erase verify operation is performed on the memory cells connected to the first word line WL0, each page buffer included in the page buffer group 180 may be configured to correspond to each of the memory cells connected to the first word line WL0. The threshold voltage is compared with the verify voltage, and the comparison result data is output to the pass / fail check circuit 190. Then, the pass / fail check circuit 190 determines whether there is a memory cell whose threshold voltage is higher than the verify voltage among the memory cells connected to the first word line WL0 through the comparison result data input from the page buffer group 180. That is, whether the erase operation on the first word line WL0 has passed or failed is generated as a result value and output to the logic circuit 200 as an output signal ERAVERPF <0>.

Next, a voltage of 0 V is applied to the second word line WL1 and a pass voltage is applied to the remaining word lines WL0 and WL2-WLn in order to perform an erase verification operation on the memory cells connected to the second word line WL1. (Vpass) is applied (step 340).

Thereafter, whether a memory cell having a threshold voltage higher than the verify voltage among memory cells connected to the second word line WL1 exists is stored as a result value (step 345). In detail, when an erase verify operation is performed on the memory cells connected to the second word line WL1, each page buffer included in the page buffer group 180 may be configured to correspond to each of the memory cells connected to the second word line WL1. The threshold voltage is compared with the verify voltage, and the comparison result data is output to the pass / fail check circuit 190. Then, the pass / fail check circuit 190 determines whether there is a memory cell whose threshold voltage is higher than the verify voltage among the memory cells connected to the second word line WL1 through the comparison result data input from the page buffer group 180. That is, whether the erase operation on the second word line WL1 is pass or fail is generated as a result value and output to the logic circuit 200 as an output signal ERAVERPF <1>.

In the same manner, an erase verify operation is sequentially performed to memory cells connected to the last word line WLn.

A voltage of 0 V is applied to the last word line WLn and a pass voltage Vpass is applied to the remaining word lines WL1-WLn-1 to perform an erase verification operation on the memory cells connected to the last word line WLn. (Step 350).

Thereafter, whether a memory cell having a threshold voltage higher than the verify voltage among memory cells connected to the last word line WLn exists is stored as a result value (step 355). In detail, when an erase verify operation is performed on the memory cells connected to the last word line WLn, each page buffer included in the page buffer group 180 may have a threshold voltage of each memory cell connected to the last word line WLn. And the verification voltage are compared to output the comparison result data to the pass / fail check circuit 190. Then, the pass / fail check circuit 190 determines whether there is a memory cell whose threshold voltage is higher than the verify voltage among the memory cells connected to the last word line WLn through the comparison result data input from the page buffer group 180. As a result, whether the erase operation of the last word line WLn has passed or failed is generated as a result value and output to the logic circuit 200 as an output signal ERAVERPF <n>.

As described above, the pass / fail check circuit 190 performs an erase verification operation on the memory cells connected to each word line to determine whether a memory cell having a threshold voltage higher than the verify voltage exists for each word line, that is, each word line. If the erase operation passes or fails, the output signal ERAVERPF <n: 0> is output to the logic circuit 200 for each word line. The logic circuit 200 determines whether the erase operation passes or fails for each word line. Save the information.

After sequentially performing an erase verification operation on the memory cells connected to the first word line WL0 to the memory cells connected to the last word line WLn, and outputting a result value, the threshold voltages of all the memory cells are increased. It is determined whether it is lower than the verification voltage (step 360). That is, it is determined whether the threshold voltages of all the memory cells included in the memory block in which the erase operation is performed are lower than the verify voltage, that is, whether the erase passes. Thus, when the threshold voltages of all the memory cells are lower than the verify voltage, Pass), so the operation ends.

When the threshold voltages of all the memory cells are lower than the verify voltage, that is, when there are memory cells whose threshold voltage is higher than the verify voltage, it is determined whether the erase operation is performed according to the last erase loop. (Step 370). In the case of the last erase loop, since the erase operation can no longer be performed, the memory block is erase-failed (step 380) and the operation is terminated.

If the current erase operation does not correspond to the last erase loop, the erase voltage Verase is increased (step 390) to perform the erase operation again.

In this case, a voltage of 0 V is applied to the word line WL in which the memory cell whose threshold voltage is higher than the verification voltage, that is, the word line that is not erased. This is to perform the erase operation in the next erase loop. An erase prohibition voltage Vm is applied to a word line where no memory cell has a threshold voltage higher than the verify voltage, that is, an erase pass word line. This is to be less affected by the erase operation in the next erase loop.

In more detail, in the method of operating the semiconductor memory device according to the embodiment of the present invention, as the erase operation is repeatedly performed, that is, as the erase loop increases, the magnitude of the erase voltage applied to the well is increased. Let's do it. Thus, as the erase loop increases, the threshold voltages of the memory cells become lower and lower. In the characteristics of the threshold voltage, there are memory cells (called fast cells) whose threshold voltages rise or fall rapidly according to the voltage applied thereto, while memory cells (slow cells whose threshold voltages rise or fall slowly) It is also called). In the case of fast cells, even when a low erase voltage is applied, the threshold voltage is rapidly lowered. In the case of a slow cell, a threshold voltage may be lowered when a higher erase voltage is applied. However, when the erase loop is increased, if the erase operation is already passed and a voltage of 0 V is applied to the word line to which the memory cells whose threshold voltages are lower than the verify voltage are connected as before, the erase voltage is gradually increased. The threshold voltages of the cells become lower and lower, and thus the distribution of the threshold voltages becomes wider (over erase). In this case, when the erase prohibition voltage Vm is applied to the word line to which the erased memory cells are connected, the voltage difference between the control gate and the well of the memory cell decreases, so that 0 V is applied to the word line. The threshold voltage is lowered.

The expression of the erase prohibition voltage Vm does not mean that the erase operation is not performed at all in the next loop. Of course, the erase operation may not be performed by applying the same voltage as the erase voltage to the word line. Thus, if the threshold voltages of the erased pass-through memory cells are no longer lowered, it is of course desirable, but applying a positive voltage to less effect the erase operation than to apply the same high voltage to the word line. More preferred.

The erase prohibition voltage Vm may increase in proportion to the erase operation performed on the erase loop, that is, the memory cells connected to the word line. In addition, the erase prohibition voltage may increase in proportion to the magnitude of the erase voltage applied to the word lines during the erase operation. As the number of erase operations increases, the magnitude of the erase voltage applied to the well increases, and as the magnitude of the erase voltage increases, the threshold voltage of the memory cell decreases. The erase prohibition voltage may be applied to prevent the threshold voltages of the memory cells from lowering.

As described above, in the method of operating the semiconductor memory device according to the second exemplary embodiment, an erase verify operation is performed for each word line. The result is then transferred from the pass / fail check circuit 190 to the logic circuit 200. The logic circuit 200 stores information on whether or not an erase pass has been performed for each word line, and according to the information, a signal for determining a magnitude of a voltage to be applied to each word line in the next erase operation is determined by the global word line switch 130. ) Then, the global word line switch 130 applies a voltage to the global word line according to the voltage information for each word line input from the logic circuit 200. A word line WL in which a memory cell with a threshold voltage higher than the verify voltage exists, that is, a word line in which no memory cell has a threshold voltage higher than the verify voltage exists. A positive voltage (anti-clear voltage, Vm) is applied to the erased word line so as to be less affected by the erase operation in the next erase loop.

The number of times of the erase operation is determined, and the erase operation is repeatedly performed until the threshold voltages of all the memory cells included in the memory block in which the erase operation is performed are lower than the verification voltage.

As described above, according to an exemplary embodiment of the present invention, an erase verification operation is performed on a word line basis, and a voltage higher than 0 V is applied to an erase pass word line during the next erase operation by using erase pass / fail information for each word line. During the erase operation, the voltage difference between the well and the control gate of the memory cell is reduced.

The embodiments of the present invention described above are not only implemented by the apparatus and method but may be implemented through a program for realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded, The embodiments can be easily implemented by those skilled in the art from the description of the embodiments described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

110: memory array 120: voltage generating circuit
130: global word line switch 140: high voltage switch circuit
150: block decoder 160: block switch
170: control circuit 180: page buffer group
190: pass / fail check circuit 200: logic circuit

Claims

Performing an erase operation on a memory block including memory cells connected to a plurality of word lines;
Sequentially performing an erase verify operation from memory cells connected to the first word line to memory cells connected to the last word line to check whether a memory cell whose threshold voltage is higher than the verify voltage exists; And
And performing an additional erase operation by differently setting a voltage applied to the word line according to whether a memory cell whose threshold voltage is higher than the verify voltage is present.

The method of claim 1, wherein performing an erase operation of the memory block comprises:
A method of operating a semiconductor memory device which applies a ground level voltage to all word lines.

The method of claim 1, wherein when performing the erase verify operation,
A method of operating a semiconductor memory device, wherein a verify voltage is applied to selected word lines to perform a verify operation, and a positive voltage is applied to unselected word lines.

The method of claim 3, wherein the verification voltage is a ground voltage, and the positive voltage is a voltage for turning on memory cells.

The method of claim 1, wherein after the erase verify operation is performed, the erase voltage is increased when the erase operation is performed.

The method of claim 1, wherein an erase prohibition voltage is applied to a word line in which a memory cell having a threshold voltage higher than a verify voltage does not exist in a next erase operation.

The method of claim 6, wherein the erase prohibition voltage is
And a method of increasing the number of erase operations performed on memory cells connected to the word line.

The method of claim 6, wherein the erase prohibition voltage is
A method of operating a semiconductor memory device which increases in proportion to the magnitude of an erase voltage applied to word lines during an erase operation.

A memory array including memory cells connected to a plurality of word lines;
Comparison results of threshold voltages and erase verify voltages of memory cells connected to a word line where the erase verify operation is performed while the erase verify operations of the memory cells connected to the first word line to the memory cells connected to the last word line are sequentially performed A page buffer group configured to output data;
A pass / fail check circuit configured to output a signal which checks whether a memory cell whose threshold voltage is higher than a verify voltage exists for each word line using the comparison result data; And
Each word line stores as a result value whether a memory cell having a threshold voltage higher than a verify voltage exists as a result value, and outputs a signal for determining a voltage to be applied to each word line in a next erase operation according to the stored result value. A semiconductor memory device comprising a configured logic circuit.

The semiconductor memory of claim 9, further comprising: a voltage supply circuit configured to generate a voltage to be applied to each word line and to supply the voltage information to the word line when the voltage information to be applied to each word line is input from the logic circuit. Device.

The method of claim 10, wherein the logic circuit
And outputting voltage information to the voltage supply circuit to apply an erase prohibition voltage to a word line in which no memory cell exists in which the threshold voltage is higher than a verify voltage.

The method of claim 11, wherein the erase prohibition voltage is
The semiconductor memory device increases in proportion to the number of erase operations performed on the memory cells connected to the word line.

The method of claim 11, wherein the erase prohibition voltage is
A semiconductor memory device which increases in proportion to the magnitude of an erase voltage applied to word lines during an erase operation.

The circuit of claim 10, wherein the voltage supply circuit is
And increasing the magnitude of the erase voltage applied to word lines when the next erase operation is performed after the erase verify operation is performed.