KR20120060280A - Successive approximation register analog digital converter and operation method thereof - Google Patents

Abstract

PURPOSE: A SAR(Successive Approximation Register) ADC(Analog To Digital Converter) and an operation method thereof are provided to improve an operation speed of analog to digital conversion by optimizing latch movement. CONSTITUTION: An SAR(Successive Approximation Register) ADC(Analog To Digital Converter)(100) improves an operation speed in comparison with a general SAR ADC by using an asynchronous clock signal. The SAR ADC includes a digital conversion unit(110), an asynchronous clock generating circuit(120), and an SAR controller(130). The digital conversion unit changes an analog input voltage in response to a clock signal of the asynchronous clock generating circuit into digital signals. The asynchronous clock generating circuit generates the clock signal for controlling a sampling operation and a digital conversion operation in the digital conversion unit. The SAR controller controls the overall operation of the SAR ADC.

Description

SUCCESSIVE APPROXIMATION REGISTER ANALOG DIGITAL CONVERTER AND OPERATION METHOD THEREOF

The present invention relates to an analog to digital converter, and more particularly to a continuous approximation analog to digital converter and a method of operation thereof.

Recently, as the use of mixed-mode systems has increased, the necessity of analog digital converters (ADCs) has increased. In particular, systems such as a digital video disk player (DVDP) or a direct broadcast for satellite receiver (DRSR) have been actively researched for one chip through a CMOS process for a low price. To this end, the design technology of an ADC capable of directly processing a radio frequency signal (RF) is emerging as the biggest issue.

To date, various types of ADCs have been proposed. For example, Flash ADCs, Pipeline ADCs, and Successive Approximation Register ADCs (SAR ADCs) have been proposed, and are used in applications suitable for their characteristics. Flash ADCs operate relatively fast, but have the disadvantage of having high power consumption. Pipeline ADCs support fast operating characteristics and high resolution, but require a large area. SAR ADCs have a low power consumption of the circuit and are simple in circuit configuration, but have the disadvantage of operating relatively slowly.

SUMMARY OF THE INVENTION An object of the present invention is to provide a continuous approximation analog-to-digital converter that can improve the operation speed and at the same time improve the reliability of analog-to-digital conversion.

A method of operating a continuous approximation analog-to-digital converter according to an embodiment of the present invention includes converting an analog signal into a digital signal; Determining whether the time required for the digital conversion matches the time allocated for the digital conversion; And adjusting the shear amplification time if the time spent on the digital conversion does not match the time allocated to the digital conversion.

In an embodiment, adjusting the shear amplification time may include increasing the shear amplification time if the time required for the digital conversion is shorter than the time allocated to the digital conversion.

In an embodiment, the step of adjusting the shear amplification time may further include reducing the shear amplification time when the time required for the digital conversion is longer than the time allocated to the digital conversion.

Continuous approximation analog to digital converter according to an embodiment of the present invention is a controller; An asynchronous clock generation circuit for generating clock signals in response to the control of the controller; And a digital converter converting an analog signal into a digital signal in response to the clock signals, wherein the time required for performing the digital conversion in the digital converter does not match the time allocated to the digital conversion. The controller adjusts the shear amplification time performed by the digital converter.

In some embodiments, the digital converter may include a comparator configured to compare magnitudes of input voltages through a shear amplification operation; And a conversion confirmation unit connected to the comparator, wherein the conversion confirmation unit provides the controller with information regarding a time point at which the comparison operation of the comparator is completed.

In an embodiment, the comparator includes a delay circuit, and the controller adjusts the shear amplification time by increasing the delay time of the delay circuit.

In an embodiment, the comparator may include a multistage amplifier having a plurality of front end amplifiers connected in multiple stages; A latch coupled to the output of the multistage amplifier; A plurality of capacitors respectively storing voltages output from the plurality of front end amplifiers; A plurality of offset cancellation switches respectively connected to output ends of the plurality of front end amplifiers to respectively remove offsets from the outputs of the plurality of front end amplifiers; And a plurality of reset switches connected to output ends of the plurality of front end amplifiers, respectively, for resetting outputs of the plurality of front end amplifiers.

In an embodiment, when the time required to perform the digital conversion in the digital conversion unit does not match the time allocated to the digital conversion, the controller is further configured to control the front end amplification time of the clock signals. Adjust the duty ratio.

In an embodiment, when the time required to perform the digital conversion in the digital conversion unit is shorter than the time allocated to the digital conversion, the controller increases the duty ratio of the clock signal controlling the shear amplification time.

In an embodiment, when the time required to perform the digital conversion in the digital conversion unit is longer than the time allocated to the digital conversion, the controller reduces the duty ratio of the clock signal controlling the shear amplification time.

The continuous approximation analog-to-digital converter according to the embodiment of the present invention can improve the operation speed of the analog-to-digital conversion and optimize the reliability of the analog-to-digital conversion by optimizing the latch operation.

1 is a block diagram illustrating a SAR ADC according to an exemplary embodiment of the present invention.
FIG. 2 is a timing diagram for describing an operation of the SAR ADC of FIG. 1.
3 is a block diagram illustrating a SAR ADC according to another exemplary embodiment of the present invention.
4 is a timing diagram for describing an operation of the SAR ADC of FIG. 3.
5 is a flowchart illustrating an operation of a SAR ADC of FIG. 3.
6 to 8 are diagrams for describing an example of the comparator of FIG. 3.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

1 is a block diagram illustrating a SAR ADC 100 according to an exemplary embodiment of the present invention. The SAR ADC 100 of FIG. 1 uses an asynchronous clock signal to improve operating speed compared to a typical SAR ADC. Referring to FIG. 1, the SAR ADC 100 includes a digital converter 110, an asynchronous clock generation circuit 120, and a SAR controller 130.

The digital converter 110 receives the clock signals Qsmp, Qcvs, Qpre, and Qlatch from the asynchronous clock generation circuit 120. The digital converter 110 converts the analog input voltage Vin into a digital signal in response to the clock signals Qsmp, Qcvs, Qpre, and Qlatch. The digital converter 110 includes a digital analog converter (DAC), a comparator 112, and a SAR logic circuit 113.

The DAC 111 receives the analog input voltage Vin and the reference voltage Vref, and samples the analog input voltage Vin. The DAC 111 receives the digital bits D0 to Dn and generates first and second level voltages Vn and Vp in response to the digital bits D0 to Dn. The DAC 111 may be implemented using a plurality of capacitors and a plurality of switches having different capacitances.

The comparator 112 receives the first and second level voltages Vn and Vp from the DAC 111. The comparator 112 compares the magnitudes of the first and second level voltages Vn and Vp and outputs a comparison signal of logic high or logic low. The SAR logic circuit 113 receives the comparison signal from the comparator 112 and uses the same to determine the values of the digital bits D0 to Dn.

The asynchronous clock generation circuit 120 generates clock signals Qsmp, Qcvs, Qpre, and Qlatch for controlling the sampling operation and the digital conversion operation of the digital conversion unit 110, and the SAR controller 130 generates a SAR ADC ( 100) to control the overall operation.

FIG. 2 is a timing diagram for describing an operation of the SAR ADC 100 of FIG. 1. Hereinafter, the operation of the SAR ADC 100 will be described in more detail with reference to FIGS. 1 and 2.

The operation of the SAR ADC 100 is largely divided into a sampling operation and a digital converting operation. That is, when the analog input voltage Vin is provided, the DAC 111 samples the analog input voltage Vin. Thereafter, the SAR ADC 100 determines the digital bits D0 to Dn of the analog input voltage Vin.

The digital conversion operation is classified into a pre-amplifying operation and a latch operation. That is, the comparator 112 includes a front end amplifier (not shown) and a latch (not shown), and the front end amplifier amplifies the difference between the first and second level voltages Vn and Vp. For example, the latch latches '1' when the first level voltage Vn is greater than the second level voltage Vp, and when the first level voltage Vn is less than the second level voltage Vp. Latch 0 '. For convenience of description, delays by the DAC 111 and the SAR logic circuit 113 are omitted in FIG. 2.

As shown in FIG. 2, the latch operation in the SAR ADC 100 may be controlled by a Qlatch signal, which is an asynchronous clock signal. That is, the SAR controller 130 monitors a time point at which the latch completion operation is completed, and the asynchronous clock generation circuit 120 generates a Qlatch signal supporting the optimal latch operation. Therefore, the SAR ADC 100 of FIG. 1 may improve the operation speed as compared to a general SAR ADC.

On the other hand, in general, SAR ADC is designed in consideration of the problem of performance degradation due to process variation (process variation). That is, the SAR ADC should operate normally even in the slowest-slow conditions, and therefore the SAR ADC is designed to be optimized for the harshest conditions. In this case, under normal or fast-fast time, the actual digital conversion time is performed faster than the time allocated in the design process.

For example, assume that the SAR ADC 100 of FIG. 2 is designed to be optimized for the worst conditions and operates at the best conditions. In this case, as shown in FIG. 2, the SAR ADC 100 may perform an actual data conversion operation for a time of 'Tm'. As a result, a remaining time of 'Tr' may occur. Hereinafter, another embodiment of the present invention will be described that can utilize the remaining time to improve the reliability of the SAR ADC.

3 is a block diagram illustrating a SAR ADC 200 according to another embodiment of the present invention. Referring to FIG. 3, the SAR ADC 200 includes a digital converter 210, an asynchronous clock generation circuit 220, and a SAR controller 230. The SAR ADC 200 of FIG. 3 is similar to the SAR ADC 100 of FIG. 1. Therefore, the differences of the SAR ADC 100 of FIG. 1 will be described below.

 The SAR ADC 200 of FIG. 3 supports a normal mode and a digital converting optimize mode. In normal mode, the SAR ADC 200 performs a normal analog-to-digital conversion operation. Since this is similar to the description of FIGS. 1 and 2, the detailed description is omitted.

In the digital conversion optimal mode, the SAR ADC 200 of FIG. 3 allocates the remaining time to the time at which the shear amplification operation is performed. Therefore, since the time for performing the shear amplification operation is increased, the digital conversion reliability of the SAR ADC 200 can be improved.

In detail, when the Cal_en signal is activated, the SAR ADC 200 enters the digital conversion optimal mode. That is, the SAR controller 230 activates the Cal_en signal, and the Cal_en signal activated by the SAR controller 230 is provided to the digital converter 210. The SAR controller 230 may activate the Cal_en signal in response to an external request. In addition, the SAR controller 230 may activate the Cal_en signal at a predetermined cycle.

When the digital conversion optimum mode is entered, the digital conversion unit 210 performs a digital conversion operation in response to the clock signals Qsmp, Qcvs, Qpre, and Qlatch. When the digital conversion operation is completed, the conversion confirmation unit 214 provides the Cvr_en signal to the SAR controller 230. That is, the conversion confirmation unit 214 provides the SAR controller 230 with information about the time when the actual digital conversion operation is performed.

The SAR controller 230 receives the Cvr_en signal from the conversion confirming unit 214. That is, the SAR controller 230 receives information about the time at which the actual digital conversion operation is performed from the conversion confirmation unit 214. The SAR controller 230 compares the time allocated to the digital conversion operation with the time during which the actual digital conversion operation is performed, and determines whether there is a remaining time.

If there is remaining time, the SAR controller 230 controls the asynchronous clock generation circuit 220 to increase the time for which the shear amplification operation is performed. The asynchronous clock generation circuit 220 increases the duty ratio of the Qpre signal in response to the control of the SAR controller 230.

Thereafter, the digital conversion unit 210 performs a digital conversion operation in response to the clock signals Qsmp, Qcvs, Qpre, and Qlatch. In this case, since the duty ratio of the Qpr signal is increased, the time for performing the shear amplification operation in the comparator 212 is increased compared to the comparator 112 of FIG. Accordingly, the comparator 212 may accurately compare the magnitudes of the first and second level voltages Vn and Vp with those of the comparator 112 of FIG. 1. As a result, the reliability of the SAR ADC 200 is improved compared to the SAR ADC 100 of FIG.

When the digital conversion operation is completed, the conversion confirmation unit 214 provides the Cvr_en signal to the SAR controller 230, and the SAR controller 230 determines whether there is a remaining time. If there is a remaining time, the above digital conversion operation is repeatedly performed. If there is no remaining time, the state of the clock signals Qsmp, Qcvs, Qpre, Qlatch is maintained.

4 is a timing diagram for describing an operation of the SAR ADC 200 of FIG. 3. Hereinafter, the operation of the SAR ADC 200 will be described in more detail with reference to FIGS. 3 and 4. For convenience of description, it is assumed in FIG. 4 that the SAR ADC 200 is designed such that the sampling operation and the digital conversion operation are performed for 'T1' and 'T2' times, respectively.

When the Cal_en signal is activated, the SAR ADC 200 enters the digital conversion optimal mode. Thereafter, the digital conversion operation in the first cycle cycle1 is performed.

Specifically, the Qsmp signal is activated, and the DAC 211 performs a sampling operation for a 'T1' time. Thereafter, the Qcvs signal is activated, and the digital conversion unit 210 performs a digital conversion operation. In this case, the conversion confirming unit 214 activates the Cvr_en signal to be synchronized with the rising edge of the Qcvs signal. When the digital conversion operation in the first period is completed, the conversion confirmation unit 214 transitions the Cvr_en signal from logic high to logic low.

The SAR controller 230 receives the Cvr_en signal from the conversion confirming unit 214 and determines whether there is a remaining time. For example, in FIG. 4, it is assumed that a first remaining time Tr1 exists. In this case, the SAR controller 230 controls the asynchronous clock generation circuit 220 to increase the time for which the shear amplification operation is performed. The asynchronous clock generation circuit 220 increases the duty ratio of the Qpre signal (see FIG. 2) in response to the control of the SAR controller 230. Thereafter, the digital conversion operation in the second cycle cycle2 is performed.

After the digital conversion operation in the second cycle cycle2 is completed, for example, it is assumed that the second remaining time Tr2 exists. In this case, the duty ratio of the Qpre signal in the second period is increased than the duty ratio of the Qpre signal in the first period. Therefore, the second remaining time Tr2 is shorter than the first remaining time Tr1. Meanwhile, in order to allocate the second remaining time Tr2 to the time at which the shear amplification operation is performed, the SAR controller 230 controls the asynchronous clock generation circuit 220 to increase the time at which the shear amplification operation is performed. The asynchronous clock generation circuit 220 increases the duty ratio of the Qpre signal in response to the control of the asynchronous clock generation circuit 220. Thereafter, the digital conversion operation in the third cycle cycle3 is performed.

After the digital conversion operation in the third cycle cycle3 is completed, as an example, it is assumed that there is an excess time Tv. That is, it is assumed that the time Tm3 required for the digital conversion operation in the third period is longer than the time T2 allocated to the digital conversion operation. Here, the excess time Tv means a time (ie, Tv = T2-Tm3) excluding the time T2 allocated to the digital conversion operation from the time Tm3 at which the digital conversion operation is performed.

In this case, the SAR controller 230 controls the asynchronous clock generation circuit 220 to reduce the time for performing the shear amplification operation. The asynchronous clock generation circuit 220 reduces the duty ratio of the Qpre signal in response to the control of the SAR controller 230.

Therefore, in the fourth period cycle4 thereafter, substantially the time Tm4 at which the digital conversion operation is performed and the time T2 allocated to the digital conversion operation may coincide. In other words, the digital conversion optimization operation is completed. In this case, the Cal_en signal is deactivated and the SAR ADC 200 enters a normal mode.

5 is a flowchart illustrating an operation of the SAR ADC 200 of FIG. 3.

In step S10, the Cal_en signal is activated. When the Cal_en signal is activated, the SAR ADC 200 enters the digital converting optimize mode from the normal mode.

In operation S20, a sampling operation is performed, and in operation S30, a digital conversion operation is performed. In this case, as described in FIG. 2, the digital conversion operation may include a shear amplification operation and a latch operation.

In step S40, it is determined whether there is a remaining time. That is, the conversion confirmation unit 214 provides the SAR controller 230 with information about the time required for the actual digital conversion operation, and the SAR controller 230 provides the time allocated to the digital conversion operation and the actual digital conversion operation during the design process. By comparing the time required, it is determined whether the remaining time exists.

If the remaining time exists, the time for performing the shear amplification operation is increased (step S50). That is, the asynchronous clock generation circuit 220 increases the duty ratio of the Qpre signal in response to the control of the SAR controller 230. Thereafter, the sampling operation S20 and the digital conversion operation S30 are performed again.

If there is no remaining time, it is determined whether an over time exists (S40). That is, the SAR controller 230 compares the time allocated to the digital conversion operation with the time required for the actual digital conversion operation in the design process, and determines whether there is an excess time.

If there is an excess time, the time for performing the shear amplification operation is reduced (step S70). That is, the asynchronous clock generation circuit 220 reduces the duty ratio of the Qpre signal in response to the control of the SAR controller 230. Thereafter, the sampling operation S20 and the digital conversion operation S30 are performed again.

If no timeout exists, the Cal_en signal is deactivated (step S80) and the digital conversion optimization mode is terminated.

Meanwhile, in FIGS. 3 to 5, it is described that the time Tm4 substantially spent on the digital conversion during the digital conversion optimization mode and the time T2 allocated to the digital conversion operation in the design process are exactly the same. However, this is for exemplary purposes only, and the technical idea of the present invention is not limited thereto.

For example, if the unit of the increase amount of the duty ratio of the Qpre signal is large, substantially the time required for the digital conversion during the digital conversion optimization mode and the time allocated to the digital conversion operation during the design process may not match. In this case, the number of times the digital conversion operation is performed in the digital conversion optimization mode may be limited to a predetermined number.

On the other hand, the amplification time of the shear amplifier can be increased or decreased by various methods. For example, when the front end amplifier is implemented in a delay circuit, the amplification time of the front end amplifier can be easily adjusted by adjusting the delay time of the delay circuit. As another example, the amplification time of the shear amplifier can be adjusted using a multistage voltage comparator, described below.

6 to 8 are diagrams for describing an example of the comparator 212 of FIG. 3. 6 through 8 illustrate multi-stage voltage comparators as examples of the comparator 212 of FIG. 3. For ease of description, the same components and signals are described using the same reference numerals and symbols. The multi-stage voltage comparator 212 of FIGS. 6 to 8 can adjust the amplification time of the shear amplifier, and is particularly effective for minimizing the amplification time of the shear amplifier.

6 and 7 are diagrams for describing the multi-stage voltage comparator 212. 6 and 7, the multi-stage voltage comparator 212 includes a multi-stage amplifier A having first to third shear amplifiers A21 to A23 connected in multiple stages, and a latch L connected to an output terminal of the multi-stage amplifier A. ) Are connected to output terminals of the first to sixth capacitors C1 to C6 and the first to third shear amplifiers A21 to A23 that store voltages output from the first to third shear amplifiers A21 to A23. The first to sixth reset switches Srs1 to Srs6, and the first to sixth offset elimination switches Sof1 to Sof6 are included.

In the following, the connection relationship between each component is briefly described.

First and second capacitors C1 and C2 are connected between an output terminal of the first front amplifier A21 and an input terminal of the second front amplifier A22. The third and fourth capacitors C3 and C4 are connected between the output terminal of the second front end amplifier A22 and the input terminal of the third front end amplifier A23. Fifth and sixth capacitors C5 and C6 are connected between the output terminal of the third front end amplifier A23 and the input terminal of the latch L.

One end of the first and second capacitors C1 and C2 is connected to the first and second reset switches Srs1 and Srs2 that operate in response to the first clock CK1. The other ends of the first and second capacitors C1 and C2 are connected to the first and second offset elimination switches Sof1 and Sof2 that operate in response to the second clock CK2. One end of the third and fourth capacitors C3 and C4 is connected to the third and fourth reset switches Srs3 and Srs4 which operate in response to the third clock CK3. The other end of the third and fourth capacitors C3 and C4 is connected to the third and fourth offset elimination switches Sof3 and Sof4 which operate in response to the fourth clock Ck. One end of the fifth and sixth capacitors C5 and C6 is connected to fifth and sixth reset switches Srs5 and Srs6 that operate in response to the fifth clock CK5. The other ends of the fifth and sixth capacitors C5 and C6 are connected to fifth and sixth offset elimination switches Sof5 and Sof6 that operate in response to the sixth clock CK6.

In FIG. 6, for convenience of description, a structure in which the latch 1 is connected to the three-stage multi-stage amplifier A is exemplarily illustrated. However, this is merely an example, and the present invention is applicable to any structure having a multistage amplifier of two or more stages.

The multi-stage voltage comparator 212 of FIG. 6 removes the offset from the outputs of the front end amplifiers A21 to A23 through the first to sixth offset elimination switches Sof1 to Sof6. The multi-stage voltage comparator 212 minimizes the output recovery time of the front-end amplifiers A21 to A23 through the first to sixth reset switches Srs1 to Srs6. Thus, the multi-stage voltage comparator 212 of FIG. 6 can operate at high speed and can also adjust the shear amplification time.

FIG. 8 illustrates an operation of the multi-stage voltage comparator 212 of FIG. 6 in detail, and is an enlarged timing diagram of an oblique portion in the timing diagram of FIG. 7.

Referring to FIG. 8, when the first and second level voltages Vn and Vp are provided to the multi-stage voltage comparator 212, the first and second reset switches Srs1 and Srs2 are connected to the first clock CK1. Respond and stay on. Therefore, the output of the first front end amplifier A21 is reset during the initial operation time tao. That is, the first clock CK1 maintains logic high until after the crossing point of the first and second level voltages Vn and Vp, and serves to reduce the propagation delay time of the first front end amplifier A21.

Thereafter, the first front-end amplifier A21 amplifies the difference between the first and second input voltages Vn and Vp after the crossing point during the first operating time ta1 and the first and second output voltages Va. , Vb).

In a similar manner, the third clock CK3 remains logic high until after the crossing point of the output voltages Va and Vb of the first front end amplifier A21, and the fifth clock CK5 has the second front end amplifier ( The logic high is maintained until after the crossing point of the output voltages Vc and Vd of A22).

Accordingly, the second front end amplifier A22 is reset for a ta0 + ta1 time in response to the third clock CK3 and amplifies the difference between the first and second output voltages Va and Vb during the ta2 time. The third front-end amplifier A23 is reset for a ta0 + ta1 + ta2 time in response to the fifth clock CK5 and amplifies the difference between the third and fourth output voltages Vc and Vd during the ta3 time.

That is, it is sufficient to maintain the reset of the first front end amplifier A21 until the point where the first and second level voltages Vn and Vp intersect, but for a variety of reasons, the first clock CK1 is the first and second level. The intersection of the voltages Vn and Vp may be missed. In order to prevent this, the reset state is maintained up to the intersection of the level voltages in the second and third front end amplifiers A22 and A23 using the third clock CK3 and the fifth clock CK5.

In addition, when a large input voltage is provided to the second and third front end amplifiers A22 and A23 by amplification of the first front end amplifier A21, the fifth and sixth input voltages Ve and Vf are provided to the latch L. Before) is provided, the second and third shear amplifiers A22 and A23 may be saturated. Thus, the output recovery time can be long. In this case, the output recovery time can be minimized by resetting the second and third front end amplifiers A22 and A23 using the third clock CK3 and the fifth clock CK5. That is, the output recovery time can be minimized by keeping the first, third, and fifth clocks CK1, CK3, and CK5 at logic high only up to the intersection of the input voltages input to the respective front-end amplifiers A21 to A23.

Therefore, when designing a multi-stage voltage comparator, if a front amplifier having a relatively high operating speed is arranged at the front stage and a relatively slow operating speed is arranged at the rear stage, a dedicated amplifier having the same operating speed may be used. As compared with the conventional multi-stage voltage comparator, the overall operating speed can be improved.

6 to 8 reset the output of each of the front end amplifiers A21 to A23 using three different clocks CK1, CK3, and CK5, but it should be understood as an example. For example, it is also possible to reset each of the front end amplifiers A21 to A23 using one clock. In this case, using the fifth clock CK5 having the longest period is advantageous for high speed operation as compared to using the first and third clocks CK1 and CK3.

On the other hand, it is apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or technical spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

ADC: Analog Digital Converter DAC: Digital Analog Converter
SAR: Successive Approximation Register
100, 200: continuous approximation analog-to-digital converter (SAR ADC)
110, 210: digital converter 120, 220: asynchronous clock generation circuit
130, 230: SAR controller

Claims (10)

Converting an analog signal into a digital signal;
Determining whether the time required for the digital conversion matches the time allocated for the digital conversion; And
And adjusting the shear amplification time if the time taken for the digital conversion does not match the time allocated for the digital conversion. The method of claim 1,
Adjusting the shear amplification time
And increasing the shear amplification time if the time required for the digital conversion is shorter than the time allocated for the digital conversion. The method of claim 1,
Adjusting the shear amplification time
Reducing the shear amplification time if the time spent on the digital conversion is longer than the time allocated to the digital conversion. controller;
An asynchronous clock generation circuit for generating clock signals in response to the control of the controller; And
A digital converter converting an analog signal into a digital signal in response to the clock signals,
And the controller adjusts the execution time of the shear amplification operation of the digital conversion unit when the time required for performing the digital conversion in the digital conversion unit does not match the time allocated to the digital conversion. The method of claim 4, wherein
The digital conversion unit
A comparator for performing the shear amplification operation and comparing magnitudes of input voltages; And
And a conversion confirming unit connected to the comparator, the conversion confirming unit providing information to the controller about the completion time of the comparison operation of the comparator. The method of claim 5, wherein
And the comparator comprises a delay circuit, wherein the controller adjusts the execution time of the shear amplification operation by increasing the delay time of the delay circuit. The method of claim 5, wherein
The comparator
A multistage amplifier, in which a plurality of front end amplifiers are connected in multiple stages;
A latch coupled to the output of the multistage amplifier;
A plurality of capacitors respectively storing voltages output from the plurality of front end amplifiers;
A plurality of offset cancellation switches respectively connected to output ends of the plurality of front end amplifiers to respectively remove offsets from the outputs of the plurality of front end amplifiers; And
And a plurality of reset switches respectively connected to output ends of the plurality of front end amplifiers to reset the outputs of the plurality of front end amplifiers, respectively. The method of claim 4, wherein
If the time required to perform the digital conversion in the digital conversion unit does not match the time allocated to the digital conversion, the controller adjusts the duty ratio of the clock signal controlling the shear amplification time among the clock signals. Continuous approximation analog to digital converter. The method of claim 8,
And the controller increases the duty ratio of the clock signal controlling the shear amplification time when the time required to perform the digital conversion in the digital converter is shorter than the time allocated to the digital conversion. The method of claim 8,
And the controller reduces the duty ratio of the clock signal controlling the shear amplification time when the time required for performing the digital conversion in the digital converter is longer than the time allocated to the digital conversion.

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