KR20120039587A - Wafer level led package - Google Patents

Abstract

PURPOSE: A wafer level light-emitting diode package is provided to improve the reliability of a product by preventing thermal transformation and moisture penetration through a bonding plane and to improve reflecting efficiency. CONSTITUTION: An insulation reflecting layer(112) and an electrode pattern are formed on the upper side of a lower plate(110). The lower plate comprises conductive via hole(118) which electrically interlinks an interval of the electrode pattern and an external terminal. The external terminal comprises the electrode pattern which touches a lower end of the conductive via hole, and a eutectic electrode which is laminated on the electrode pattern. An upper plate(120) forms an opening for a cavity in a region corresponding to the electrode pattern. A light emitting diode(130) is mounted on the electrode pattern. The light emitting diode is composed of a light emitting structure(131).

Description

Wafer level LED package

The present invention relates to a light emitting diode package manufactured at the wafer level, to prevent moisture penetration and thermal deformation through the bonding surface to increase product reliability, to improve reflection efficiency when emitting light emitting chips, and to increase light extraction efficiency. The present invention relates to a wafer level light emitting diode package capable of improving optical characteristics.

In general, a light emitting diode (LED) refers to a semiconductor device capable of realizing various colors of light by forming a light emitting source by changing compound semiconductor materials such as GaAs, AlGaAs, GaN, and InGaInP.

Such a light emitting diode may generate light of various colors based on recombination of electrons and holes in a junction of p and n-type semiconductors when a current is applied, and thus may be used as a light source.

Criteria for determining device characteristics of light emitting diodes include color, brightness, luminance intensity, thermal, and electrical reliability. Device characteristics are primarily determined by compound semiconductor materials used in light emitting diode devices. Secondary factors are also greatly influenced by the structure of the package for mounting the light emitting chip.

That is, in order to obtain heat dissipation characteristics for releasing heat generated during light emission to the outside, only elements due to the development of materials of the package parts have limitations, and thus, much attention has been paid to package structures.

Such a light emitting diode package has a structure different from that of a conventional semiconductor package because it must exhibit not only thermal and electrical reliability but also optical characteristics.

In general, the light emitting diode package is formed through a package body which is injection molded from a resin material to form a cavity in which a light emitting chip is disposed, and a pair of lead frames and metal wires integrally formed to be spaced apart at a predetermined interval in the package body. BACKGROUND ART A lead frame mold package formed by wire bonding a light emitting chip and a lead frame is known.

In addition, the light emitting chip mounted on the upper surface of the ceramic substrate in which the plurality of ceramic sheets are stacked in multiple layers is electrically connected to each other through an electrode pattern and a metal wire formed on the upper surface of the ceramic substrate, and the transparency is provided on the upper surface of the ceramic substrate. BACKGROUND OF THE INVENTION Ceramic mold packages constituting resin packaging parts molded from resin materials are known.

However, since the conventional mold package has limitations in simplifying the manufacturing process, reducing the size of the package, and realizing the batch process, wafer-level packaging technology is being introduced to realize the simplification, miniaturization, and batch process. to be.

Meanwhile, Korean Patent Laid-Open Publication No. 10-2006-0095271 (2006.8.31) mounts a plurality of light emitting chips on a wafer substrate, applies a phosphor paste to the mounted upper surface of the light emitting chip, and hardens them to a chip size. A manufacturing method of manufacturing a package of a light emitting diode package at a wafer level by cutting is disclosed.

However, such a conventional light emitting diode package manufacturing process is due to the heterogeneous bonding between the wafer substrate and the phosphor paste and the difference of thermal expansion coefficients, so that external moisture is absorbed into the package at the bonding surface therebetween or the defect rate of the packaged product is caused by thermal deformation. Height acted as a factor

In addition, the conventional wafer-level LED package has a limit in improving the light extraction efficiency by increasing the efficiency of the light reflected to the outside when the light emitting chip emits light or by increasing the transmittance of light passing through the chip substrate of the light emitting chip.

Accordingly, the present invention is to solve the above problems, the object of which is to prevent moisture ingress and thermal deformation through the bonding surface to increase product reliability, increase the reflection efficiency during light emission of the light emitting chip, light extraction efficiency To provide a wafer-level light emitting diode package that can increase the optical properties of the package by increasing the.

As a specific means for achieving the above object, the present invention includes an insulating reflective layer and an electrode pattern on the upper surface, an external terminal on the lower surface, and a conductive via hole for electrically connecting between the electrode pattern and the external terminal. A lower substrate; An upper substrate bonded to the upper substrate by penetrating a cavity opening in an area corresponding to the electrode pattern; And a light emitting chip mounted on the electrode pattern and formed of a light emitting structure from which a chip substrate is removed. It provides a wafer level light emitting diode package comprising a.

Preferably, the light emitting structure includes a wavelength conversion unit made of a fluorescent layer coated on the upper surface of the light emitting structure or a fluorescent film laminated on the upper surface of the light emitting structure. .

Preferably, the external terminal includes an electrode pad in contact with a lower end of the conductive via hole, and a eutectic electrode stacked on the electrode pad.

Preferably, the upper substrate and the lower substrate is made of any one of SiC, Si, GaN, AlN.

Preferably, the opening for the cavity has a reflective layer on an inclined surface inclined at a predetermined angle.

More preferably, the insulating reflective layer and the reflective layer are made of the same reflective material or different reflective materials.

In addition, the present invention provides a lower substrate having at least one insulating reflective layer on the upper surface: forming a conductive via hole connecting between the electrode pattern formed on the lower substrate and the external terminal formed on the lower substrate ; Bonding an upper substrate through which an opening for a cavity is formed to an upper surface of the lower substrate; Mounting a light emitting chip on an electrode pattern exposed through the opening; Irradiating a laser beam on the light emitting chip to remove the chip substrate; Reducing the thickness of the upper substrate to correspond to the light emitting chip from which the chip substrate is removed; It provides a wafer level light emitting diode package manufacturing method comprising the step of cutting the upper and lower substrates into individual light emitting diode packages.

Preferably, the method may further include forming a wavelength conversion unit for wavelength converting light generated from the light emitting structure after removing the chip substrate.

More preferably, the wavelength conversion part may be formed of a fluorescent layer coated on the upper surface of the light emitting structure, or may be made of a fluorescent film laminated on the upper substrate and the upper surface of the light emitting structure, or may be formed of a resin phosphor filled in the opening for the cavity.

Preferably, the opening for the cavity is provided with an inclined surface inclined at a predetermined angle, and the inclined surface is provided with a reflective layer to reflect light generated when the light emitting structure emits light.

More preferably, the reflective layer is made of the same or different reflective material than the insulating reflective layer.

According to the present invention, a light emitting chip mounted on an upper substrate with a lower substrate having an insulating reflection layer and an electrode pattern on the upper surface, and an upper substrate formed through the cavity opening through the upper substrate are vertically bonded at the wafer level. Chip substrate is removed as a laser beam, and the upper surface of the upper substrate is reduced to correspond to the upper surface of the light emitting structure from which the chip substrate is removed, so that the light generated when the light emitting structure emits light does not penetrate the chip substrate. Since the light emitting efficiency is increased, the optical properties of the package can be improved by increasing the light extraction efficiency, and the reliability of the packaged products can be improved by preventing moisture penetration and thermal deformation through the bonding surface.

In addition, the optical reflection characteristics of the package are further enhanced by the reflection reflection layer formed at the interface between the upper and lower substrates, and the reflection layer formed on the inclined surface of the cavity for improving the reflection efficiency when the light emitting chip emits light. An effect which can be improved is obtained.

1A to 1H are flowcharts illustrating a method of manufacturing a wafer level light emitting diode package according to a first embodiment of the present invention.
2 is a process chart including a fluorescent film in the wafer level light emitting diode package manufacturing method according to a second embodiment of the present invention.
3 is a flowchart illustrating a resin phosphor in a method of manufacturing a wafer-level light emitting diode package according to a third embodiment of the present invention.
4 is a cross-sectional view illustrating a wafer level light emitting diode package according to a first embodiment of the present invention.
5 is a cross-sectional view illustrating a wafer level light emitting diode package according to a second embodiment of the present invention.
6 is a cross-sectional view illustrating a wafer level light emitting diode package according to a third embodiment of the present invention.

Preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

In the method 100 for manufacturing a wafer-level light emitting diode package 100 according to the first embodiment of the present invention, as shown in FIGS. 1A to 1H, providing a lower substrate, forming a conductive via hole, and bonding an upper substrate Comprising the steps of mounting the light emitting chip, removing the chip substrate, reducing the thickness of the upper substrate and cutting.

In the providing of the lower substrate 110, as shown in FIG. 1A, the light emitting chip 130 is mounted and the lower substrate 110 having at least one insulating reflective layer 112 formed on the upper surface thereof to a predetermined thickness. ) To provide.

The lower substrate 110 may be formed of any one of SiC, Si, GaN, and AlN substrate materials, and the insulating reflective layer 112 may reflect light generated when the light emitting chip 130 emits light upward. DBR (Distributed Bragg Reflector) can be provided, the insulating reflection layer 112 is a Ti, Si, Nb oxide to form an insulating layer between the junction surface and the upper substrate 120 while increasing the light extraction efficiency. Or Si nitride.

Forming the conductive via hole 118 may include forming an electrode pattern 114 and a lower portion of the insulating reflective layer 112 formed on the upper surface of the lower substrate 110 as shown in FIGS. 1B and 1C. The conductive via hole 118 is formed on the lower surface of the substrate 110 to electrically connect the external terminal 116 to the bottom surface of the substrate 110.

That is, a through hole penetrating the upper substrate 120 is formed in a region where the light emitting chip 130 is mounted, a conductive filler is filled in the through hole, and then patterned on the upper surface of the lower substrate 110. The external terminal 116 is electrically connected to the light emitting chip 130 mounted in the region and forms an electrode pattern 114 in contact with an upper end of the conductive via hole 118, and is in contact with a lower end of the conductive via hole 118. To form.

Here, the external terminal 116 is deposited on the electrode pad 116a which is pattern-printed on the lower surface of the lower substrate 110 to be in contact with the lower end of the conductive via hole 118, and is deposited on the electrode pad 116a. The eutectic electrode 116b is included.

The eutectic electrode 116b may be made of any one of Au / Sn, In, Al, Ag so as to obtain a stable adhesive force when mounting the package on a metal substrate or a silicon substrate.

The external terminal 116 is a power input terminal connected to an external circuit such as a PCB (not shown) to receive power.

The bonding of the upper substrate 120 may include bonding the upper substrate 120 through which the opening 124 of a predetermined size is formed on the upper surface of the lower substrate 110, as shown in FIG. 1D. will be.

The upper substrate 120 is formed of a substrate member through which a cavity opening 124 of a predetermined size is formed in a region corresponding to the electrode pattern 114 printed on the upper surface of the lower substrate 110. The opening 124 for the cavity may be formed by a wet etching process.

That is, a pattern for forming the opening 124 for the cavity is formed on the upper substrate 120 by photo-lithograph, and then a wet etching solution such as KOH solution, TMAH or EDP is used. The substrate 120 is etched to form a cavity opening 124 of a predetermined size in which the light emitting chip 130 is disposed.

The upper substrate 120 may be made of the same substrate material as that of the lower substrate 110 or may be made of different substrate materials.

Here, the cavity opening 124 is provided with an inclined surface inclined at a predetermined angle, the inclined surface is provided with a reflective layer 122 to reflect the light generated during the light emission of the light emitting chip in the full-wavelength band, such a reflective layer ( 122 may be made of the same or different reflective material as the insulating reflective layer 112 formed on the upper surface of the lower substrate 110.

The mounting of the light emitting chip 130 may be performed on the electrode pattern 114 of the lower substrate 110 exposed through the cavity opening 124 of the upper substrate 120, as shown in FIG. 1E. The light emitting chip 130 including the light emitting structure 131 and the chip substrate 132 is mounted by a flip bonding method.

In this case, the light emitting chip 130 includes a chip substrate 132 and a light emitting structure 131 including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer sequentially stacked on the chip substrate 132.

 The chip substrate 132 is a growth substrate provided for the growth of the nitride semiconductor layer. The chip substrate 132 may be a high resistance substrate, and a sapphire substrate may be mainly used.

These sapphire substrates are Hexa-Rhombo R3c symmetric crystals with lattice constants of 13.001 Å and 4.758 c in the c-axis and a-axis directions, respectively, and C (0001) plane, A (1120) plane, and R It has a (1102) plane and the like, and in this case, the C plane is mainly used as a substrate for nitride growth because it is relatively easy to grow a nitride thin film and stable at high temperature.

The n-type semiconductor layer and the p-type semiconductor layer has an Al _x In _y Ga _(1-xy) N composition formula (where 0≤x≤1, 0≤y≤1, 0≤x + y≤1), Each of the n-type and p-type impurities may be formed of a semiconductor material doped with GaN, AlGaN, InGaN.

In addition, Si, Ge, Se, Te or C may be used as the n-type impurity, and the p-type impurity may be representative of Mg, Zn or Be.

The n-type and p-type semiconductor layers may use a known process for growing nitride semiconductor layers. For example, organometallic vapor deposition (MOCVD), molecular beam growth (MBE), and hydride vapor deposition (HVPE) may be used. This corresponds.

Although not shown, a buffer layer (not shown) may be formed on the lower substrate 110 to mitigate lattice mismatch between the chip substrate and the n-type semiconductor layer, and the buffer layer may be a III-V nitride compound semiconductor. As an n-type material layer or an undoped material layer consisting of, may be a low temperature nucleus growth layer including AlN or n-GaN.

The active layer is a material layer in which light emission is generated by carrier recombination of electron-holes. Group III-V nitride-based compound semiconductor layer is preferable, and the quantum barrier layer is Al _x In _y Ga _(1-xy) N (0≤x≤1, 0 <y≤1, 0 <x + y≤ 1), the quantum well layer may be formed of In _z Ga _(1-z) N (0 ≦ _z ≦ 1). In this case, the quantum barrier layer may have a superlattice structure having a thickness through which tunnels of holes injected from the p-type semiconductor layer can be tunneled.

The light generated in the active layer is emitted to the outside through the chip substrate 132. Since the chip substrate 132 has a low light transmittance, the chip substrate 132 to increase the light extraction efficiency when the light emitting structure emits light. It is desirable to remove.

The removing of the chip substrate 132 may be performed by irradiating a laser beam L on the chip substrate 132 of the light emitting chip 130 to expose the light emitting structure 131 to the outside as illustrated in FIG. 1F. The chip substrate 132 is removed.

That is, when an excimer laser beam having a wavelength of about 198 nm to 248 nm is irradiated onto the surface of the chip substrate 132 on which the nitride semiconductor layer is grown, the interface between the nitride semiconductor layer, which is a grown epi layer, and the sapphire substrate, is an interface. Most of the laser beams are absorbed at, causing the temperature of the interface to rise rapidly.

In this case, as the temperature rises rapidly at the interface between the nitride semiconductor layer and the chip substrate, the chemical bond is broken at the interface of the sapphire substrate, so that the nitride semiconductor layer thin film is separated from the chip substrate 132 of the sapphire material.

Here, the wavelength of the excimer laser beam depends on the type of buffer layer grown on the sapphire chip substrate, and it is preferable to use an excimer laser beam having an energy larger than the band gap of the buffer layer (interface). In particular, an excimer laser having a short wavelength has an advantage of minimizing damage to the nitride semiconductor layer because the thickness of the light absorbing layer in the nitride semiconductor layer can be reduced.

In addition, the chip substrate 132 includes a process of forming the wavelength conversion unit 140 to convert the light generated from the light emitting structure 131 from which the chip substrate 132 is removed from the light emitting chip 130 into white light. It is preferable to carry out after the process of removing.

As shown in FIG. 1G, the wavelength conversion unit 140 is coated on the upper surface of the light emitting structure 131 to which the chip substrate 132 is removed to be exposed to the outside, and includes a fluorescent layer 141. As shown in FIG. 2 or as shown in FIG. 2, the upper substrate 120 and the upper surface of the light emitting structure 131 are stacked and provided with a fluorescent film 142 including a fluorescent material or as shown in FIG. 3. Likewise, the resin phosphor 143 may be formed by dispensing and filling the opening 124 for the cavity formed on the upper substrate and in which the light emitting chip is disposed, and including a fluorescent material.

Here, the fluorescent film 142 is shown and described as being bonded to the upper surface of the upper substrate 120 together with the upper surface of the light emitting structure 131, but is not limited thereto, and is the same as the fluorescent layer 141. It may be provided adhered only to the upper surface of the light emitting structure 131.

The fluorescent material included in the fluorescent layer 141, the fluorescent film 142, and the resin phosphor 143 has a wavelength that converts any one of red, blue, and green light emitted from the light emitting structure 131 into white light. Conversion means.

Such a fluorescent material is YAG (yttrium-aluminum-garnet-based) or TAG (terbium-) to convert wavelengths so that red, blue, or green light, which is emitted from the light emitting structure 131, is converted into white light, which is a second wavelength. Aluminum-garnet-based) or silicate-based powders.

Subsequently, reducing the thickness of the upper substrate 120 may include the upper surface and the upper substrate of the light emitting structure 131 from which the chip substrate 132 is removed from the light emitting chip 130, as shown in FIG. 1H. The upper and lower substrates 110 and 120 may be removed by grinding or removing the upper surface of the upper substrate 120 by using an abrasive, or by wet or dry etching so that the upper surface of the 120 is positioned on substantially the same horizontal line. To reduce the overall thickness of the package it contains.

Finally, the upper surface of the upper substrate is removed to reduce the thickness of the substrate, and as shown in FIG. 1H, the upper and lower substrates 110 and 120 are cut along the cutting line as a cutting tool, not shown, to emit light. Diode packages can be manufactured separately.

4 is a cross-sectional view illustrating a wafer level light emitting diode package according to a first embodiment of the present invention. The wafer level light emitting diode package 100 includes a lower substrate 110, an upper substrate 120, and a light emitting chip 130. It includes.

The lower substrate 110 is formed of any one of SiC, Si, GaN, and AlN substrate material, and an electrode that is electrically connected to the insulating reflection layer 112 and the light emitting chip which simultaneously perform an insulation function and a reflection function on the upper surface. Each of the patterns 114 is provided.

Here, the insulating reflection layer 112 is a DBR to be an insulating layer between the bonding surface and the upper substrate 120 while increasing the light extraction efficiency by refracting and reflecting light generated when the light emitting chip 130 emits light. (Distributed Bragg Reflector), and the insulating reflection layer 112 may increase the light extraction efficiency to form an insulating layer between the bonding surface and the upper substrate 120, Ti, Si, Nb oxide or Si It may be provided with any one of nitrides.

The lower surface of the lower substrate 110 includes an external terminal 116 and a conductive via hole 118 electrically connecting the electrode pattern 114 and the external terminal 116.

The external terminal 116 may include an electrode pad 116a in contact with a lower end of the conductive via hole 118, and a eutectic electrode 116b stacked on an outer surface of the electrode pad 116a.

The upper substrate 120 is formed of the same or different substrate material as that of the lower substrate 110 to form the insulating reflective layer 112, the electrode pattern 114, the external terminal 116, and the conductive via hole 118, respectively. The wafer member is integrally bonded to the upper surface of the lower substrate 110.

The upper substrate 120 penetrates the cavity opening 124 in a region corresponding to the electrode pattern 114 on which the light emitting chip 130 is mounted, and a portion of the upper surface of the upper substrate 120 emits light from which the chip substrate 132 is removed. It is removed by a polishing process, a wet or dry etching process so as to approximately coincide with the top surface of the structure 131.

Here, the opening 124 for the cavity is provided with an inclined surface that is inclined at a predetermined angle, and the inclined surface may reflect light generated when the light emitting chip mounted on the lower substrate emits light in a radio wave band to increase light extraction efficiency. The reflective layer 122 may be provided, and the reflective layer 122 may be made of the same or different reflective material as the insulating reflective layer 112 formed on the upper surface of the lower substrate 110.

The light emitting chip 130 is flip chip bonded and mounted on an electrode pattern 114 formed on an upper surface of the lower substrate 110, and has a light emitting structure in which the chip substrate 132 is removed by a laser beam L. 131) is a light emitting means for generating light when the power is applied.

The wavelength conversion unit 140 is provided to convert the light generated from the light emitting structure 131 from which the chip substrate 132 is removed to white light, and the wavelength conversion unit 140 is shown in FIG. 4. Likewise, the chip substrate 132 may be removed and coated on the upper surface of the light emitting structure 131 exposed to the outside, and may be formed of a fluorescent layer 141 including a fluorescent material.

In addition, as illustrated in FIG. 5, the wavelength conversion unit 140 is stacked on the upper surface of the upper substrate 120 and the light emitting structure 131, and is provided as a fluorescent film 142 including a fluorescent material. As shown in FIG. 6, a resin phosphor 143 is formed through the upper substrate 120 and dispensed and filled in an opening 124 for a cavity in which the light emitting chip is disposed, and includes a fluorescent material. Can be.

While the invention has been shown and described with respect to particular embodiments, it will be understood that various changes and modifications can be made in the art without departing from the spirit or scope of the invention as set forth in the claims below. It will be appreciated that those skilled in the art can easily know.

110: lower substrate 112: insulating reflective layer
114: electrode pattern 116: external terminal
116a: electrode pad 116b: eutectic electrode
118: conductive via hole 120: upper substrate
122: reflective layer 124: opening for the cavity
130: light emitting chip 131: light emitting structure
132; Chip substrate 140: wavelength conversion unit
141: fluorescent layer 142: fluorescent film
143: resin phosphor

Claims (6)

A lower substrate having an insulating reflection layer and an electrode pattern on an upper surface, an outer terminal on a lower surface, and a conductive via hole electrically connecting between the electrode pattern and the external terminal;
An upper substrate bonded to the lower substrate by penetrating an opening for a cavity in an area corresponding to the electrode pattern; And
A light emitting chip mounted on the electrode pattern and formed of a light emitting structure from which a chip substrate is removed; Wafer level light emitting diode package comprising a. The method of claim 1,
Further comprising a wavelength conversion portion made of a fluorescent layer coated on the upper surface of the light emitting structure or made of a fluorescent film laminated on the upper substrate and the upper surface of the light emitting structure or made of a resin phosphor filled in the opening for the cavity. A wafer level light emitting diode package. The method of claim 1,
And the outer terminal includes an electrode pad in contact with a lower end of the conductive via hole, and a eutectic electrode stacked on the electrode pad. The method of claim 1,
The upper substrate and the lower substrate is a wafer level light emitting diode package, characterized in that made of any one of SiC, Si, GaN, AlN. The method of claim 1,
The opening for the cavity is a wafer-level light emitting diode package, characterized in that it comprises a reflective layer on a slope inclined at a predetermined angle. The method of claim 5,
The insulating reflective layer and the reflective layer is a wafer level light emitting diode package, characterized in that made of the same reflective material or different reflective materials.

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