KR20110130214A - A method of manufacturing a semiconductor chip comprising a through electrode - Google Patents

Abstract

PURPOSE: A manufacturing method of a semiconductor chip including a penetration electrode is provided to remove an edge of a first substrate without adding a resizing process by removing a recess region in forming a penetration hole. CONSTITUTION: In a manufacturing method of a semiconductor chip including a penetration electrode, a first substrate(100) has first and second sides which are faced with each other. The first side of the first substrate is selectively etched to form a recess region and a reserved penetration hole. A metal layer(160) is formed on one side of the second substrate(150). The metal layer of the second substrate and the first side of the first substrate are combined to form a combination structure. A penetration hole exposes the metal layer to the outside. A penetration electrode(140) filling a penetration hole is formed.

Description

A manufacturing method of a semiconductor chip including a through electrode {A METHOD OF MANUFACTURING A SEMICONDUCTOR CHIP COMPRISING A THROUGH ELECTRODE}

The present invention relates to a method for forming a semiconductor chip, and more particularly to a method for manufacturing a semiconductor chip including a through electrode.

The present invention has been carried out as part of the industrial source technology development project of the Ministry of Knowledge Economy and the Korea Institute of Industrial Technology Evaluation and Management.

Recently, in the electronic industry such as mobile phones and notebooks, the demand for light weight, miniaturization, high speed, multifunction, high performance and high reliability of products is increasing. As a solution to satisfy these demands, research on semiconductor package technology is continuously conducted. Two-dimensional connections between integrated circuits using conventional wire bonding have disadvantages such as signal loss in wires, high power consumption, and design method limitations. In order to overcome this drawback, a three-dimensional integrated circuit package technology has been proposed in which semiconductor signal chips are vertically stacked and a long vertical signal line is a short vertical line. In this case, a vertical wire connecting the semiconductor chips vertically is referred to as a through electrode. Three-dimensional integrated circuit package technology using through electrodes can implement more integrated circuits in the same space and shorter circuit-to-circuit connections. In order to commercialize the 3D integrated circuit package technology, a process technology for forming a through electrode between vertically stacked wafers or chips, a process technology for electrically connecting them, and a stacking process by stacking and bonding between wafers Research is being done on process technology to form structures.

One technical problem to be solved by embodiments according to the concept of the present invention is to provide a method for manufacturing a semiconductor chip including a through electrode that can improve the productivity.

Provided is a method of manufacturing a semiconductor chip including a through electrode for solving the above technical problems. According to an embodiment of the inventive concept, a method of manufacturing a semiconductor chip including a through electrode may include preparing a first substrate having a first surface and a second surface facing each other, and the first surface of the first substrate. Selectively etching to form a recess region defining a chip array region in an edge region, and preliminary through holes in the chip array region, wherein each of the preliminary through holes and the recess region includes a bottom surface. Forming a bonding structure by forming a metal layer on one surface of a second substrate, combining the metal layer of the second substrate and the first surface of the first substrate, and forming a bonding structure of the first substrate in the bonding structure. Etching the second surface until the bottom surfaces of the preliminary contact holes and the recess region are removed to form through holes exposing the metal layer and to fill the through holes. It includes forming the penetrating electrode.

According to the exemplary embodiments of the present disclosure, since the recess region is removed by the process of forming the through holes, the edge region of the first substrate may be removed without the addition of the resizing process. Therefore, the process of forming the through electrode can be simplified, and the through electrode can be formed at a low manufacturing cost.

1A to 1I are cross-sectional views illustrating a method of manufacturing a semiconductor chip including a through electrode according to embodiments of the inventive concept.
1J and 1K are cross-sectional views illustrating a method of stacking semiconductor chips including a through electrode formed according to embodiments of the inventive concept.
FIG. 2 is a plan view showing the recessed region disclosed in FIG. 1B. FIG.
3A is a cross-sectional view illustrating a modified example of a recessed region in a method of manufacturing a semiconductor chip including a through electrode according to an embodiment of the inventive concept.
FIG. 3B is a plan view illustrating the recessed region of FIG. 3A.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

In the drawings, sizes, thicknesses, etc. of components are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween.

The expression 'and / or' is used herein to include at least one of the components listed before and after. Portions denoted by like reference numerals denote like elements throughout the specification. The thickness and relative thickness of the components represented in the drawings may be exaggerated to clearly express embodiments of the present invention.

1A to 1I are cross-sectional views illustrating a method of manufacturing a semiconductor chip including a through electrode according to example embodiments of the inventive concept, and FIG. 2 is a plan view illustrating a recessed region of FIG. 1B.

Referring to FIG. 1A, a first substrate 100 including a first surface 10 and a second surface 20 facing each other is provided. The first substrate 100 may be composed of a chip array region 1100 and an edge region 1200. The chip array region 1100 may include chip regions 1120 on which a plurality of semiconductor chips are formed and a scribe lane 1140 between the chip regions. The semiconductor chips may be formed on the first surface 10 of the first substrate 100. The edge region 1200 may surround the chip array region 1100 and correspond to a region where the semiconductor chips are not formed. The first substrate 100 may be a wafer.

Referring to FIGS. 1B and 2, the first surface 10 of the first substrate 100 may be selectively etched to form recesses 110 and chip array regions 1100 in the edge region 1200. Preliminary through holes 122 may be formed. The recess region 110 may be formed in the edge region 1200 to define the chip array region 1100. As shown in FIG. 2, the recess region 110 may be formed in a closed loop shape surrounding the chip array region 1100 in a plan view. The preliminary through holes 122 may be formed in the plurality of chip regions 1120 included in the chip array region 1100.

Each of the recess region 110 and the preliminary through holes 122 may have a bottom surface. Bottom surfaces of the preliminary through holes 122 and the recess region 110 may be at the same level from the second surface 20 of the first substrate 100. The recess region 110 may be formed in a portion of the edge region 1200. In this case, the recess region 110 may be adjacent to the chip array region 1100. Accordingly, the recess region 110 may have a first sidewall extending from the bottom surface and having a second sidewall adjacent to the chip array region and opposing the first sidewall.

The preliminary through holes 122 and the recess region 110 may be formed by the same process. Forming the preliminary through holes 122 and the recess region 110 may include depositing an etch mask layer on the first surface 10 of the first substrate 100, and patterning the etch mask layer. And the preliminary through holes 122 and the recess region 110 using the patterned etching mask layer as an etching mask. The preliminary through holes 122 and the recess region 110 may be formed by a dry etching process.

In contrast, the preliminary through holes 122 and the recess region 110 may be formed by a laser.

Referring to FIG. 1C, a first insulating layer 132 may be formed on the first substrate 100 including the preliminary through holes 122 and the recess region 110. The first insulating layer 132 may include a silicon oxide layer. The first insulating layer 132 may be formed by a chemical vapor deposition process.

A first barrier film 134 and a second insulating film 136 sequentially stacked on the first insulating film 132 may be further formed. The first barrier layer 134 may include at least one selected from titanium, titanium nitride, tantalum, and tantalum nitride. The first barrier layer 134 may minimize diffusion of the metal material included in the through electrode 140 of FIG. 1H into the first insulating layer 132.

The second insulating layer 136 may include a silicon oxide layer. When the second substrate 150 of FIG. 1E is coupled to the first substrate 100 to form a coupling structure, the second insulating layer 136 may form the first barrier layer 134 and the metal layer of FIG. 1E. The 160 may be prevented from being electrically connected.

As illustrated in FIG. 1C, the first insulating layer 132, the first barrier layer 134, and the second insulating layer 136 may include the first surface 10 and the second surface of the first substrate 100. It may be formed on the face 20. In contrast, the first insulating layer 132, the first barrier layer 134, and the second insulating layer 136 may have the preliminary through holes 122 on the first surface 10 of the first substrate 100. May be formed on the inner surfaces of the substrate and the inner surface of the recess region 110, and may not be formed on the second surface 20.

Referring to FIG. 1D, a second substrate 150 including a first side 30 and a second side 40 is provided. The metal layer 160 may be formed on the second substrate 150. The metal layer 160 may be formed by a physical vapor deposition process (PVD) or an evaporation process. The metal layer 160 may include gold (Au). In contrast, the metal layer 160 may be made of the same material as the metal material forming the through electrode 140 of FIG. 1H. For example, the metal material may be copper.

The metal layer 160 may be formed on the first surface 30 and the second surface 40 on the second substrate 150 as shown in FIG. Alternatively, the metal layer 160 may be formed only on the second surface 40 on the second substrate 150, but not on the first surface 30.

The method may further include forming a first adhesive layer (not shown) on the second substrate 150 before forming the metal layer 160. The first adhesive layer (not shown) is any one selected from a metal organic chemical vapor deposition process (MOCVD), a physical vapor deposition process (PVD), and an evaporation process (Evaporation Process) It can be formed by the process of. The first adhesive layer (not shown) may include titanium tungsten (TiW). The first adhesive layer (not shown) may increase the bonding force between the second substrate 150 and the metal layer 160.

Referring to FIG. 1E, a bonding structure is formed by combining the second surface 40 of the second substrate 150 on which the metal layer 160 is formed with the first surface 10 of the first substrate 100. Can be formed. Accordingly, in the bonding structure, the first insulating film 132 or the second insulating film 136 on the first insulating film 132 and the second substrate (on the first surface 10 of the first substrate 100). The metal layer 160 may contact the second surface 40 of the 150. The process of forming the bonding structure may be performed by at least one process selected from a heat treatment process, a pressing process, and a thermocompression bonding process. For example, the heat treatment process may be performed under process conditions in which the reaction temperature is 200 ° C. and the reaction time is 30 minutes. By the heat treatment process, the elements included in the first insulating layer 132 or the second insulating layer 136 and the metal elements included in the metal layer 160 react to form a bonding structure, thereby forming the first substrate ( 100 and the second substrate 150 may be combined to form a bonding structure.

The method may further include performing plasma treatment on the first substrate 100 and the second substrate 150 before forming the bonding structure. The plasma treatment process may be performed by at least one selected from plasma of nitrogen, oxygen, and argon atmosphere. For example, the plasma treatment process may be performed under process conditions in which the power is 250W to 400W and the reaction time is 150 seconds. Since the reactivity of molecules increases on the surfaces of the insulating films 132 and 136 by the plasma treatment process, the bonding force between the first insulating film 132 and the metal layer 160 or the first insulating film in a subsequent bonding process. A bonding force between the second insulating layer 136 and the metal layer 160 may be increased on the 132.

Referring to FIG. 1F, before forming the bonding structure, the method may further include forming a second adhesive layer 170 on the metal layer 160 on the second surface 40 of the second substrate 150. have. Accordingly, the second adhesive layer 170 may be disposed between the metal layer 160 and the first insulating layer 132 or the second insulating layer 136 on the first surface 10 of the first substrate 100 in the bonding structure. Can be published on The second adhesive layer 170 may be a resist-based material. For example, the second adhesive layer 170 may be a photoresist or a dry film resist. When the second adhesive layer 170 forms the bonding structure, a bonding force between the metal layer 160 and the first insulating layer 132 on the first substrate 100 or the metal layer 160 and the first insulating layer A bonding force of the second insulating layer 136 on the 132 may be increased.

Referring to FIG. 1G, the second surface 20 of the first substrate 100 in the bonding structure is etched until the bottom surfaces of the preliminary contact holes 122 and the recess region 110 are removed. Thus, the through holes 120 exposing the metal layer 160 may be formed. The removal process may be performed by a chemical mechanical polishing process.

The bottom surface of the recess region 110 is removed by the removal process. Accordingly, a portion of the substrate of the edge region 1200 including the second sidewall of the recess region 110 may be removed from the coupling structure. Accordingly, the metal layer 160 formed on the edge of the second surface 40 of the second substrate 150 may be exposed. The exposed metal layer 160 may be used as a plating electrode when forming the through electrode 140 of FIG. 1H to be described later.

If the recess region 110 is not formed, the bonding structure is formed in order to expose the metal layer located at the edge of the second surface 40 of the second substrate 150 in the bonding structure. Before the first substrate 100 must be resized (Resizing). In this case, productivity of the semiconductor device may be lowered due to the addition of the resizing process. However, according to an exemplary embodiment of the present invention, the resizing process is not required due to the recess region 110. As a result, productivity of a semiconductor element can be improved. This simplifies the process and lowers manufacturing costs since no expensive equipment is used for the resizing process.

Referring to FIG. 1H, a through electrode 140 may be formed to fill the through holes 120. The through electrode 140 may electrically connect the plurality of stacked semiconductor chips in a package method of vertically stacking and connecting the plurality of semiconductor chips.

The through electrode 140 may include a metal material. For example, the through electrode 140 may be copper (Cu). When the through electrode 140 includes a metal material, the through electrode 140 may be formed by an electroplating process using the metal layer 160 as a plating electrode. The through holes 120 may be filled by bottom-up electroplating by the metal layer 160 exposed by the through holes 120. Therefore, the through electrode 140 may be prevented from forming voids therein, and the resistance of the through electrode 140 may be improved.

The through electrode 140 may be formed at a level higher than an upper surface of the second surface 20 of the first substrate 100. In this case, the process of planarizing the upper surface of the through electrode 140 is performed to make the same height between the through electrode 140 and the upper surface of the second surface 20 of the first substrate 100. can do. The planarization process may be performed by a chemical mechanical polishing process.

Referring to FIG. 1I, a third insulating film 182, a second barrier film 184, and a fourth insulating film 186 that are sequentially stacked on the second surface 20 of the first substrate 100 are formed. The films 182, 184, and 186 may expose the through electrode 140.

Forming the third insulating layer 182 may deposit the third insulating layer on the second surface 20 of the first substrate 100 and expose the through electrode 140 to expose the through electrode 140. And etching a portion of the third insulating layer in contact with the semiconductor layer. By the etching process, the third insulating layer 182 exposes the through electrode 140 and is disposed on the second surface 20 of the first substrate 100.

The second barrier layer 184 may be formed by depositing a second barrier layer on the third insulating layer 182 and the through electrode 140 and exposing the through electrode 140. And etching a portion of the second barrier layer in contact with By the etching process, the second barrier layer 184 may expose the through electrode 140, and the third insulating layer 182 may include the second barrier layer 184 and the first substrate 100. It may have a form surrounded by the second surface (20) of.

The fourth insulating layer 186 may be formed by depositing a fourth insulating layer on the second barrier layer 184 and the through electrode 140 and exposing the through electrode 140. And etching a portion of the fourth insulating layer in contact with The fourth insulating layer 186 may include sidewall portions that contact the sidewalls of the second barrier layer 184. Accordingly, a recess structure may be formed in which one surface of the through electrode 140 exposed from the layers 182, 184, and 186 is a bottom surface, and sidewall portions of the fourth insulating layer 186 are sidewalls. .

The third insulating layer 182 and the fourth insulating layer 186 may include a silicon oxide layer. The third insulating layer 182 and the fourth insulating layer 186 may be formed by a chemical vapor deposition process.

The second barrier layer 184 may include at least one selected from titanium, titanium nitride, tantalum, and tantalum nitride.

The third insulating layer 182 may be formed of the same material as the first insulating layer 132, and the second barrier layer 184 may be formed of the same material as the first barrier layer 134. The fourth insulating layer 186 may be formed of the same material as the second insulating layer 136.

Referring to FIG. 1J, the second substrate 150 and the metal layer 160 may be removed from the through electrode 140. Removing the second substrate 150 may be performed by a grinding process or chemical mechanical polishing process, and removing the metal layer 160 may be performed by an etching process. . When a first adhesive layer (not shown) is disposed between the second substrate 150 and the metal layer 160, the first adhesive layer (not shown) may be removed by an etching process.

Referring to FIG. 1K, bumps 192 and 194 may be formed on the second surface 20 of the first substrate 100 to be electrically connected to the through electrode 140. The bumps 192 and 194 may not be electrically connected to another through electrode adjacent to the through electrode 140 that is electrically connected to the bumps 192 and 194.

The bumps 192 and 194 may include a first structure 192 and a second structure 194 in contact with the through electrode 140. The first structure 192 fills the recess structure formed by one surface of the through electrode 140 and a sidewall portion of the fourth insulating layer 186, and on the second surface 20 of the first substrate 100. Can be formed on. The second structure 194 may be formed on the first structure 192. The first structure 192 and the second structure 194 may be formed of a metal material. The first structure 192 may include copper, and the second structure 194 may include nickel.

After the bumps 192 and 194 are formed, the scribe lanes 1140 of the first substrate 100 may be cut to separate the plurality of chip regions 1120, respectively.

1L and 1M are cross-sectional views illustrating a method of stacking semiconductor chips including a through electrode formed by embodiments of the present invention.

Referring to FIG. 1I, a first semiconductor chip 200 including a through electrode 220 formed by embodiments of the present invention is provided. The first semiconductor chip 200 may include a first surface 50 and a second surface 60 facing the first surface 50. A bump 230 may be formed on the second surface 60 of the first semiconductor chip 200 to be electrically connected to the through electrode 220. The bump 230 may not be electrically connected to another through electrode adjacent to the through electrode 220 that is electrically connected to the bump 230. The bump 230 may include a first structure 232 and a second structure 234. The first structure 232 may include copper, and the second structure 234 may include nickel.

Referring to FIG. 1K, a second semiconductor chip 300 including a through electrode 320 formed by embodiments of the present invention is provided. The second semiconductor chip 300 may include a first surface 70 and a second surface 80 opposite to the first surface 70. A bump 330 may be formed on the surface 80 to be electrically connected to the through electrode 320. The bump 330 may not be electrically connected to another through electrode adjacent to the through electrode 320 that is electrically connected to the bump 330. The bump 330 may include a first structure 332 and a second structure 334. The first structure 332 may include copper, and the second structure 334 may include nickel.

The bump 230 of the first semiconductor chip 200 and the through electrode 320 of the second semiconductor chip 300 are coupled to each other so that the first semiconductor chip 200 and the second semiconductor chip 300 are coupled to each other. Can be electrically connected. Therefore, the first semiconductor chip 200 is positioned on the second semiconductor chip 300. The connecting of the first semiconductor chip 200 and the second semiconductor chip 300 may be performed by at least one selected from a heat treatment process and a reflow process. The heat treatment process and the reflow process may be performed, for example, at a temperature of 240 ° C. for 3 minutes.

In the method of manufacturing the semiconductor chips described above, the recess region 110 may be formed in a portion of the edge region 1200. Alternatively, the recess region 112 may be formed in the entire edge region 1200. This will be described with reference to the drawings.

3A is a cross-sectional view illustrating a modified example of a recessed region in a method of manufacturing a semiconductor chip including a through electrode according to an embodiment of the inventive concept, and FIG. 3B is a plan view illustrating the recessed region of FIG. 3A. .

3A and 3B, the recess region 112 may be formed in the entire edge region 1200 of the first substrate 100. Accordingly, the recess region 112 may include only a bottom surface and sidewalls adjacent to the chip array region 1100. In other words, one side of the recess region 112 facing the outside of the first substrate 100 may be in an opened state. As shown in FIG. 3B, the recess region 112 may also have a closed loop shape surrounding the chip array region 1100 in a plan view.

100: first substrate 110, 112: recess region
120: through holes 122: preliminary through holes
132: insulating film 140: through electrode
150: second substrate 160: metal layer

Claims (1)

Preparing a first substrate having a first side and a second side facing each other;
Selectively etching the first surface of the first substrate to form a recess region defining a chip array region in an edge region, and preliminary through holes in the chip array region, wherein the preliminary through holes and recess region Each of which comprises a bottom surface;
Forming a metal layer on one surface of the second substrate;
Combining the metal layer of the second substrate and the first surface of the first substrate to form a coupling structure;
Etching the second surface of the first substrate in the bonding structure until the bottom surfaces of the preliminary contact holes and the recess region are removed to form through holes exposing the metal layer;
And forming through electrodes filling the through holes.

Images