KR20110130158A - Vertical semiconductor device and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A vertical type semiconductor device and a method of manufacturing thereof are provided to be applied to a circuit structure needing different performance characteristics by forming the thickness of the gate oxidation film of two transistors to be different. CONSTITUTION: In a vertical type semiconductor device and a method of manufacturing thereof, a common source region(108) is arranged in an active region(110) and the silicon substrate in the lower part of an element isolation film. A gate(G) is formed to be overlapped with the common source area. Gate oxidation films(116a,116b) are respectively formed between the gate and the active region in both sides of the gate. A drain region(126) is formed on the active area of both side of the gate. A LDD(Lightly Doped Drain) domain(114) is formed between the gate oxidation film and the common source area.

Description

Vertical semiconductor device and manufacturing method of the same

The present invention relates to a semiconductor device, and more particularly, to a vertical semiconductor device capable of operating two transistors with one vertical gate and a method of manufacturing the same.

In general, a semiconductor is one of a class of materials according to electrical conductivity, and is a material belonging to an intermediate region between conductors and non-conductors. In a pure state, a semiconductor is similar to non-conductor, but the electrical conductivity is increased by the addition of impurities or other operations. Such semiconductors are used to add impurities and connect conductors to create semiconductor devices such as transistors, and devices having various functions made using semiconductor devices are called semiconductor devices. A representative example of such a semiconductor device is a semiconductor memory device.

The semiconductor memory device includes a plurality of transistors. A transistor is composed of three regions: a gate, a source, and a drain. Charge occurs between a source and a drain in accordance with a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region, which uses the nature of the semiconductor.

In a typical transistor manufacturing method, a gate is formed on a semiconductor substrate, and a source and a drain are formed by doping impurities on both sides of the gate. In this case, the region between the source and the drain under the gate becomes the channel region of the transistor. Since a transistor having such a horizontal channel region occupies a semiconductor substrate having a predetermined area, it is difficult to reduce the total area due to the plurality of transistors included in a complex semiconductor memory device.

In order to solve this problem, various methods have been proposed. One of them uses a 3D transistor including a vertical transistor having a vertical channel region instead of a conventional horizontal transistor having a horizontal channel region. will be.

As a method of manufacturing such a vertical transistor, a method of forming a vertical channel region by etching a substrate to form a cylindrical pillar and forming a surrounding gate surrounding the pillar is generally used.

However, the vertical transistor according to the conventional method is very likely to collapse the pattern in the process of etching the pillar pattern. Moreover, as the degree of integration of semiconductor devices continues to increase, a situation may arise where the structure of such conventional vertical transistors has reached a limit and does not meet the required density.

The present invention is to provide a semiconductor device having a vertical gate of a novel structure for high integration of the semiconductor device.

In an exemplary embodiment, a vertical semiconductor device may include a common source region formed in a silicon substrate under an active region and a device isolation layer, a gate embedded in the active region and having a lower portion overlapping the common source region. And a double gate oxide layer formed between the active regions on both sides of the gate, and a drain region formed on the active regions on both sides of the gate.

In the vertical semiconductor device of the present invention, the double gate oxide layer may have a different thickness.

The vertical semiconductor device of the present invention may further include a lightly doped drain (LDD) region formed between the gate oxide layer and the common source region, and a lower portion of the gate overlapping the common source region is surrounded by an insulating layer and is surrounded by the insulating layer. Is electrically isolated from the source region.

The vertical semiconductor device of the present invention may be formed on the upper silicon layer of the silicon on insulator (SOI) substrate.

According to an embodiment of the present disclosure, a method of manufacturing a vertical semiconductor device may include forming a common source region by implanting impurities into a silicon substrate, forming a device isolation layer defining an active region on the silicon substrate, and forming the active region. Forming a trench to expose the common source region by forming a trench, forming a gate insulated from the common source region and buried in the trench, and forming a drain region on the active region on both sides of the upper gate. It includes.

In the method of manufacturing a vertical semiconductor device according to the present invention, the method of forming the trench may include forming a first trench by etching the active region, and connecting the common source region in the silicon substrate under the first trench. Forming a lightly doped drain (LDD) region, forming a gate oxide film on an inner surface of the first trench, forming a first conductive layer on the gate oxide film to fill the first trench, and forming the gate oxide film Etching the first conductive layer and the gate oxide layer to form a second trench that exposes the common source region.

Another method of forming the trench in the method of manufacturing a vertical semiconductor device according to the present invention includes forming a first trench that exposes the common source region by etching the active region, and forming a gate oxide film on an inner surface of the first trench. Forming a first conductive layer on the gate oxide layer so that the first trench is buried, and forming a second trench that exposes the common source region by etching the first conductive layer and the gate oxide layer. Steps.

The method of manufacturing the vertical semiconductor device according to the present invention may further include injecting impurities for adjusting the threshold voltage into both sidewalls of the first trench before forming the gate oxide layer.

In the method of manufacturing a vertical semiconductor device according to the present invention, the forming of the gate oxide layer may include impinging an impurity on only one sidewall of both sidewalls of the first trench and performing an oxidation process on both sidewalls of the first trench. Wherein the impinging the impurity impinges F or Ar ions on the one sidewall such that the surface of the sidewall is rugged.

In the method of manufacturing a vertical semiconductor device according to the present invention, the forming of the gate may include forming an insulating film on an inner surface of the second trench, and forming a second conductive layer on the insulating film to fill the second trench. Forming an upper gate under the second trench by etching back the insulating layer and the second conductive layer; and forming an upper gate by forming a third conductive layer on the lower gate to fill the second trench. It includes a step.

According to the present invention, two transistors can be operated with one gate, thereby enabling high integration of semiconductor devices.

In addition, the present invention can be applied to a circuit structure requiring different operating characteristics because the gate oxide films of the two transistors can be formed in different thicknesses.

1 is a view illustrating a configuration of a vertical semiconductor device according to an embodiment of the present invention.
2A to 2H are cross-sectional views illustrating a method of manufacturing the vertical semiconductor device of FIG. 1.
3 is a cross-sectional view illustrating a configuration of a vertical semiconductor device according to another embodiment of the present invention.
4 is a cross-sectional view illustrating a configuration of a vertical semiconductor device according to still another embodiment of the present invention.
5A through 5C are cross-sectional views illustrating a method of manufacturing the vertical semiconductor device of FIG. 4.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a view illustrating a configuration of a vertical semiconductor device according to an embodiment of the present invention. FIG. 1A is a cross-sectional view and FIG. 1B is a plan view of an active region in which a transistor is formed in FIG. 1A. 1, only one transistor is shown for convenience of description.

The vertical semiconductor device of the present invention preferably has a silicon on insulator (SOI) substrate having a structure in which a lower silicon layer 102, an buried oxide film 104, and an upper silicon layer 106 are stacked in order to realize stable performance of a transistor. Are manufactured.

In the vertical semiconductor device of the present invention, a common source region 108 in which impurities are implanted is formed under the upper silicon layer 106, and the common source region 108 is connected to the ground voltage Vss through the source contact 130. .

The gate G includes a metal (TiN or W) layer 124 and poly layers 118a and 118b formed on both sides of the metal layer 124, and is formed to be buried perpendicular to the active region 110. To form a vertical channel structure. A double gate oxide layer in which gate oxide layers 116a and 116b are formed is formed between the gate G and the active regions 110 at both sides of the gate G, and the common source region 108 is formed under the gate oxide layers 116a and 116b. LDD (Lightly Doped Drain) region 114 is formed. In this case, the gate oxide layers 116a and 116b at both sides of the gate may be formed to have the same thickness, but may be formed to have different thicknesses as necessary. A method of forming the double gate oxide films 116a and 116b to have different thicknesses will be described later.

Drain regions 126a and 126b, which are junction regions, are formed on the active regions 110 at both sides of the gate G, and drain contacts 132 are formed on the drain regions 126a and 126b.

That is, in the present invention, the gate G is formed to be buried perpendicular to the active region 110 to form a vertical channel having a length that can prevent a short channel effect, and is formed on both sides of the gate G. By forming the gate oxide layers 116a and 116b and the drain region 126 and forming a common source region 108 under the gate oxide layers 116a and 116b, the two transistors can be operated with one gate.

2A to 2H are cross-sectional views illustrating a method of manufacturing the semiconductor device shown in FIG. 1 described above.

Referring to FIG. 2A, first, impurity ions (eg, BF ₂ and As) are implanted into the upper silicon layer 106 to form a common source region 108 under the upper silicon layer 106. Since the impurity ion implantation may control the peak point of the impurity concentration by controlling the implantation energy, the impurity may be implanted to concentrate the impurity under the upper silicon layer 106 as shown in FIG. 2A. In the present embodiment, the implantation energy for impurity implantation is controlled at 150 KeV ± 20% level.

 Next, a trench (not shown) for forming an isolation layer in the silicon layer 106 is formed through an etching process using a shallow trench isolation (STI) mask. In this case, the etching process may be performed by a dry etching process, and the trench is etched until the common source region 108 is exposed.

Next, an isolation film 112 defining the active region 110 is formed by depositing an insulating film (oxide film) so that the inside of the trench is completely filled. Accordingly, the common source region 108 is formed in the silicon substrate under the active region 110 and the isolation layer 112.

Referring to FIG. 2B, after forming a photoresist pattern (not shown) defining a gate region on the upper silicon layer 106, a trench T1 is formed by etching the active region to a predetermined depth using the photoresist pattern as an etching mask. At this time, the sidewall of the trench T1 is a region where the vertical channel is formed when the transistor is operated, and the trench T1 is etched to a depth enough to prevent the vertical channel from preventing the short channel effect.

Next, impurities are implanted into the bottom of the trench T1 to form a lightly doped drain (LDD) region 114. In this case, the LDD region 114 is formed to be connected to the common source region.

Referring to FIG. 2C, impurities (eg, boron) for adjusting the threshold voltage VT are injected into both sidewalls of the trench T1.

Next, referring to FIG. 2D, the gate oxide film 116 is formed on the inner surface of the trench T1 by performing a thermal process, for example, on the trench T1, and then a conductive layer on the gate oxide film 116 is formed so as to completely fill the inside of the trench T1. 118). In this case, the conductive layer 118 may be formed of poly.

Next, referring to FIG. 2E, the device-separated gate is formed by sequentially etching the conductive layer 118, the gate oxide layer 116, and the LDD region 114 until the common source region 108 is exposed to form a trench T2. Oxide films 116a and 116b, poly layers 118a and 118b, and LDD regions 114 are formed.

Next, referring to FIG. 2F, an insulating film (nitride film) 120 is deposited on the inner surface of the trench T2, and a gate conductive material is deposited on the nitride film 120 to fill the trench T2. In this case, the insulating layer 120 is formed to electrically separate the gate conductive material from the common source region 108 and the LDD region 114, and the gate conductive material may be formed of metal (eg, TiN, W) or poly. (poly).

Next, the lower gate 122 is formed on the bottom of the trench T2 by etching back the insulating film 120 and the gate conductive material. In this case, since the insulating layer 120 is to electrically separate the lower gate 122 from the common source region 108 and the LDD region 114, the insulating layer 120 and the lower gate 122 may have a lower portion. The gate 122 may be formed to have a height sufficient to insulate the gate 122, for example, such that the top surface thereof reaches the bottom of the conductive layers 118a and 118b.

Next, referring to FIG. 2G, a gate conductive material is deposited on the lower gate 122 to fill the trench T2, and then planarized to form the upper gate 124. In this case, preferably, the upper gate conductive material and the lower gate conductive material are formed of the same material.

As a result, the vertical gate G including the poly layers 118a and 118b and the lower gate 122 and the upper gate 124 is formed.

Subsequently, impurities are implanted into the surfaces of the active regions 110 at both sides of the gate G to form junction regions (drain regions) 126a and 126b. As a result, two MOS transistors TR1 and TR2 sharing one gate G are formed. That is, the MOS transistor TR1 including the common source 108, the drain 126b and the gate G, and the MOS transistor TR2 including the common source 108, the drain 126b and the gate G are Is formed.

Next, referring to FIG. 2H, after forming the interlayer insulating layer 128 on the resultant of FIG. 2G, the interlayer insulating layer 128 is etched until the junction regions 126a and 126b are exposed to form contact holes for drain contacts. The interlayer insulating layer 128 and the upper silicon layer 106 are etched until the common source region is exposed to form contact holes for source contacts.

Subsequently, the source contact 130 and the drain contact 132 are formed by filling the source contact contact hole and the drain contact contact hole with a conductive material and then planarizing the contact contact hole.

3 is a cross-sectional view illustrating a configuration of a vertical semiconductor device according to another embodiment of the present invention.

FIG. 3 illustrates a case in which the thicknesses of the gate oxide films 116c and 116d of the two MOS transistors TR1 and TR2 sharing the gates are formed differently from those of FIG. 1. That is, two transistors having different operating characteristics may be operated as one gate by forming different thicknesses of the two oxide films 116c and 116d sharing the gate.

A method of forming the double gate oxide films 116c and 116d will be described below.

After the above-described processes of FIGS. 2A and 2B, an impurity (eg, F or Ar) ion implantation process using low energy is selectively performed only on the sidewall of the trench T1 to form a thick gate oxide film, and intentionally It causes damage. That is, F or Ar ions collide with only the surfaces of either sidewalls of the silicon sidewalls of the trench T1 in contact with the active region, causing damage to the surface of the sidewalls. Subsequently, impurities (for example, boron) for adjusting the threshold voltage are injected into both sidewalls of the trench T1. At this time, the implantation concentration of the impurity for adjusting the threshold voltage varies depending on the thickness of the gate oxide film to be deposited. In other words, an impurity implantation concentration is increased in the region where the thick gate oxide film 116c is to be formed, and impurities are implanted at a relatively low concentration in the region where the thin gate oxide film 116c is to be formed.

Next, as shown in FIG. 2D, for example, a thermal process is performed on the trench T1 to form a gate oxide film on the inner surface of the trench T1.

At this time, since the oxide growth rate on the damaged silicon surface is higher than the oxide growth rate on the opposite silicon surface, the gate oxide film formed on the damaged sidewall when the oxidation process is performed under the same conditions for both sidewalls. 116c becomes thicker than the gate oxide film 116d formed on the opposite sidewall.

Since the process is the same as in the above-described embodiment, description thereof will be omitted.

4 is a cross-sectional view illustrating a configuration of a vertical semiconductor device according to still another embodiment of the present invention.

In the above-described embodiments, the case of forming the LDD region 114 has been described. However, the present embodiment does not form the LDD region 114 in a case where the size of the transistor is larger than that of FIG. 1.

A manufacturing method of the semiconductor device shown in FIG. 4 will be described with reference to FIGS. 5A to 5C. For convenience of description, the same reference numerals are assigned to the same components as those in FIG. 1.

Referring to FIG. 5A, an impurity ion is implanted into the upper silicon layer 106 to form a common source region 108 under the upper silicon layer 106, and through an etching process using a shallow trench isolation (STI) mask. An isolation layer 112 defining an active region 110 is formed.

Next, the trench T3 is formed by etching the active region by a predetermined depth using a photoresist pattern (not shown) defining the gate region.

Next, referring to FIG. 5B, a threshold voltage control impurity (eg, boron) is injected into both sidewalls of the trench T3, and a thermal process is performed to form a gate oxide film (not shown) on the inner surface of the trench T3. Next, a conductive layer (not shown) is formed on the gate oxide film so as to completely fill the inside of the trench T3. In this case, the conductive layer may be formed of poly.

Next, the conductive layer 118 and the gate oxide film 116 are sequentially etched to form the trench T4 until the common source region 108 is exposed, thereby forming the gate oxide films 116e and 116f and the poly layer 118c which are separated from each other. 118d).

Next, referring to FIG. 5C, an insulating film (nitride film) 134 is formed on the inner surface of the trench T4, and a gate conductive material is deposited on the insulating film 134 to fill the trench T4. In this case, the insulating layer 134 is formed to electrically separate the gate conductive material from the source region 108, and the gate conductive material is formed of metal (eg, TiN, W) or poly.

Next, the insulating layer 134 and the gate conductive material are etched back to form a lower gate 136 at the bottom of the trench T4.

Subsequently, the method of forming the upper gate, the drain region, and the contact is the same as in FIGS. 2G and 2H described above, and a description thereof will be omitted.

Embodiment of the present invention described above is for the purpose of illustration, those skilled in the art will be capable of various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

For example, the above-described embodiment has been described in which the transistor of the present invention is formed on a silicon on insulator (SOI) substrate in order to realize stable performance of the transistor, but may be formed on a general bulk silicon substrate.

102 lower silicon layer 104 buried oxide film
106: upper silicon layer 108: common source region
110: active region 112: device isolation film
114: Lightly Doped Drain (LDD) 116, 116a to 116f: Gate Oxide Film
118, 118a-118d: poly layer 120, 134: insulating film
122, 136: lower gate 124: upper gate
126 drain region 128 interlayer insulating film
130: source contact 132: drain contact
TR1, TR2: MOS transistors T1 to T4: trench

Claims (13)

A common source region formed in the silicon substrate under the active region and the isolation layer;
A gate embedded in the active region and having a lower portion overlapping the common source region;
A double gate oxide layer formed between the gate and the active region on both sides of the gate; And
And a drain region formed on the active region on both sides of the gate. The method of claim 1, wherein the double gate oxide film
Vertical semiconductor device, characterized in that having a different thickness. The method of claim 1,
And a lightly doped drain (LDD) region formed between the gate oxide layer and the common source region. The method of claim 1,
A lower portion of the gate overlapping the common source region is surrounded by an insulating layer to be electrically separated from the common source region. The method of claim 1, wherein the silicon substrate is
A vertical semiconductor device, characterized in that the upper silicon layer of a silicon on insulator (SOI) substrate. Implanting impurities into the silicon substrate to form a common source region;
Forming an isolation layer defining an active region on the silicon substrate;
Etching the active region to form a trench exposing the common source region;
Forming a gate insulated from the common source region and embedded in the trench; And
And forming a drain region on the active region on both sides of the upper gate. The method of claim 6, wherein the forming of the trench
Etching the active region to form a first trench;
Forming a lightly doped drain (LDD) region connected to the common source region in the silicon substrate under the first trench;
Forming a gate oxide layer on an inner surface of the first trench;
Forming a first conductive layer on the gate oxide layer to fill the first trench; And
And etching the first conductive layer and the gate oxide layer to form a second trench that exposes the common source region. The method of claim 6, wherein the forming of the trench
Etching the active region to form a first trench that exposes the common source region;
Forming a gate oxide layer on an inner surface of the first trench;
Forming a first conductive layer on the gate oxide layer to fill the first trench; And
And etching the first conductive layer and the gate oxide layer to form a second trench that exposes the common source region. The method according to claim 7 or 8,
And injecting impurities for adjusting the threshold voltage into both sidewalls of the first trenches before forming the gate oxide layer. The method of claim 7 or 8, wherein forming the gate oxide film
Impinging impurities on only one sidewall of both sidewalls of the first trench; And
And performing an oxidation process on both sidewalls of the first trench. The method of claim 10, wherein the impinging the impurity
A method of manufacturing a vertical semiconductor device, characterized in that the surface of the side wall is bumpy by colliding F or Ar ions with the one side wall. The method of claim 7 or 8, wherein the first conductive layer is
It is a poly layer, The manufacturing method of the vertical semiconductor device. The method of claim 7 or 8, wherein forming the gate
Forming an insulating film on an inner surface of the second trench;
Forming a second conductive layer on the insulating film to fill the second trench;
Etching back the insulating layer and the second conductive layer to form a lower gate under the second trench; And
And forming an upper gate by forming a third conductive layer on the lower gate such that the second trench is buried.

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