KR20110120536A - Method for fabricating non-volatile memory device - Google Patents

Abstract

PURPOSE: A non-volatile memory apparatus manufacturing method is provided to arrange a film with a single evaporation process, thereby preventing apparatus performance degradation by minimizing a thickness difference between the films. CONSTITUTION: A plurality of first gate electrode films(13) and sacrificial film are alternatively laminated on a substrate(10). A trench for eliminating the sacrificial film and a trench for arranging a support stand are arranged by etching the multiple first gate electrode films and sacrificial film. An insulating film(15) is buried within the sacrificial film eliminating trench and support stand arranging trench. The buried insulating layer is selectively eliminated. A second gate electrode film is arranged on the surface of the first gate electrode film.

Description

Non-volatile memory device manufacturing method {METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE}

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a nonvolatile memory device having a vertical channel.

As the degree of integration of semiconductor devices increases, techniques for forming 3D devices having vertical channels have been proposed. The most important point of a 3D device having a vertical channel is to repeatedly stack a high quality heterogeneous material (for example, oxide / polysilicon) in several layers.

The stacked dissimilar materials serve as interlayer insulating films and memory cells, respectively, and when 16 layers are formed based on 16 cells, 16 layers should be stacked when an oxide film / polysilicon is 1 stage in a 3D device.

In order to stack dissimilar materials (e.g., oxide / polysilicon) in 16 steps, 16 steps of forming an oxide film and forming polysilicon should be repeated 16 times. This is done. Oxides and polysilicon are formed in furnace equipment.

On the other hand, since the thickness and quality of each layer in the 3D structure must be the same, various problems may occur in the process.

First, there is no mass production due to the process time and equipment required because the different materials are continuously stacked, and there is a problem in that device performance is degraded due to the thickness difference between the layers. In addition, the process life and PM cycles are shortened due to excessive process progress, there is a problem that the difference in the film properties between each layer. This is because the first stacked layer is subjected to 31 thermal budgets until the 32nd layer is formed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a method of manufacturing a nonvolatile memory device capable of securing mass productivity when forming a vertical channel.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device capable of minimizing a thickness difference between layers and improving device performance degradation.

A nonvolatile memory device manufacturing method according to an embodiment of the present invention for achieving the above object comprises the steps of alternately stacking a plurality of first gate electrode film and a sacrificial film on a substrate; Etching the plurality of first gate electrode layers and the sacrificial layer to form a trench for forming a sacrificial layer and a trench for forming a support stand; Filling an insulating film in the sacrificial film removing trench and the support forming trench; Selectively removing the insulating layer embedded in the sacrificial layer removing trench; Selectively removing the sacrificial layer; And removing the sacrificial film to form an interlayer insulating film and a second gate electrode film on the exposed first gate electrode film surface.

In particular, after the forming of the second gate electrode layer, the method may include etching the second gate electrode layer and the interlayer insulating layer to form a memory cell, wherein the first gate electrode layer is etched together.

In the forming of the interlayer insulating film, the interlayer insulating film may be deposited by oxidizing a surface of the first gate electrode film or along a step of the entire structure including the first gate electrode film.

The first and second gate electrode layers may be formed of polysilicon, and further comprising forming an etch stop layer on the substrate before the step of alternately stacking the first gate electrode layer and the sacrificial layer. The insulating film embedded in the sacrificial film removing trench and the support forming trench is formed of a material having an etching selectivity with respect to the first gate electrode film and the sacrificial film, and the forming of the sacrificial film removing trench and the supporting support is performed. The insulating film embedded in the trench is formed of a nitride film.

According to still another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device, the method comprising: alternately stacking a plurality of sacrificial films and a first interlayer insulating film on a substrate; Etching the plurality of sacrificial layers and the first interlayer insulating layer to form a trench for removing a sacrificial layer and a trench for forming a support stand; Filling an insulating film in the sacrificial film removing trench and the support forming trench; Selectively removing the insulating layer embedded in the sacrificial layer removing trench; Selectively removing the sacrificial layer; And removing the sacrificial film to form a gate electrode film and a second interlayer insulating film on the exposed surface of the first interlayer insulating film.

In particular, after the forming of the second interlayer insulating layer, the gate electrode layer is etched and the memory cell is formed, wherein the first and second interlayer insulating layers are etched together.

In addition, the thickness of the sacrificial film is formed to be three times the thickness of the first interlayer insulating film, the gate electrode film is formed of polysilicon, and before the step of alternately stacking the sacrificial film and the first interlayer insulating film, on the substrate It characterized in that it further comprises the step of forming an etch stop film.

The insulating film embedded in the sacrificial film removing trench and the support forming trench is formed of a material having an etching selectivity with respect to the first interlayer insulating film and the sacrificial film, and the sacrificial film removing trench and the support forming trench The insulating film embedded therein is formed of a nitride film.

The nonvolatile memory device manufacturing method according to the embodiment of the present invention described above has the effect of reducing the deposition stress by reducing the process step by reducing the deposition process by half, thereby reducing the process yield.

In addition, it is possible to prevent damage to the lower layer due to the reduction of the deposition process, and to form a film by the deposition process once, thereby minimizing the thickness difference between the films, thereby preventing device performance degradation.

1A to 1H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a first embodiment of the present invention;
2A to 2H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

((Example 1))

1A to 1H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a first embodiment of the present invention. In the present embodiment, a description will be made on the assumption that 16 memory cells are used as one string.

As shown in FIG. 1A, an etch stop layer 11 is formed on the substrate 10. The etch stop layer 11 is to prevent contact between the substrate 10 and subsequent memory cells, and may be formed of an insulating material, for example, an oxide film.

Subsequently, the plurality of sacrificial films 12 and the first gate electrode film 13 are alternately and repeatedly stacked. In the case of forming 16 memory cells, the plurality of sacrificial films 12 and the first gate electrode film 13 are repeatedly stacked eight times.

The sacrificial layer 12 is to secure a space for forming subsequent memory cells, and is preferably formed of a material having a selectivity with respect to the first gate electrode layer 13 and the subsequent insulating layer.

The first gate electrode film 13 serves as a gate electrode, and may be formed of, for example, polysilicon.

The first gate electrode film 13 is preferably formed in consideration of the thickness that is changed to the interlayer insulating film through a subsequent oxidation process. Accordingly, the first gate electrode film 13 is formed to be thicker than the sacrificial film 12, and preferably, the first gate electrode film 13 is formed to have a thickness three times the thickness of the sacrificial film 12.

As illustrated in FIG. 1B, the sacrificial layer 12 and the first gate electrode layer 13 are etched to form trenches for removing the sacrificial layer and trenches 14A and 14B for forming the support.

The sacrificial film removal trench 14A is a region for separation between each memory cell, and the support forming trench 14B is a region for forming a channel. In addition, the sacrificial film removing trench 14A is used to remove the sacrificial film 12, and the support forming trenches 14A and 14B may collapse the first gate electrode film 13 after removing the sacrificial film 12. It is used as an area to be formed a support for preventing.

The sacrificial film removal trench 14A and the support forming trench 14B may be adjusted differently from each other, and the sacrificial film removing trench 14A may be formed to have a line width wider than the line width of the supporting forming trench 14B. Can be.

In addition, the support forming trenches 14B may be formed on both sides of the sacrificial layer removing trench 14A, respectively.

The sacrificial film removing trench and the support forming trenches 14A and 14B are formed by etching the plurality of sacrificial films 12 and the first gate electrode layer 13, and the etch stop layer 11 is formed on the substrate 10. It remains as it is not etched to prevent damage to the substrate 10.

As shown in FIG. 1C, an insulating film 15 for forming a support is buried in the sacrificial film removing trench and the support forming trench 14A and 14B. The insulating layer 15 may be formed of a material having a different etching selectivity with respect to the sacrificial layer 12 and the etch stop layer 11. For example, the insulating film 15 may be formed of a nitride film.

The insulating film 15 fills the sacrificial film removing trench and the support base forming trenches 14A and 14B, and is formed on the gate electrode film 13 of the uppermost layer.

As shown in FIG. 1D, the insulating film 15 embedded in the sacrificial film removing trench 14A is removed to expose the sacrificial film removing trench 14A.

This is to secure a space for removing the sacrificial film 12. The insulating film 15 embedded in the sacrificial film removal trench 14A is selectively etched and removed, and is embedded in the support forming trench 14B. The insulating film 15 remains as it is. To this end, the photoresist is coated on the insulating film 15, and the photoresist pattern is formed by patterning the photoresist trench 14A to be opened by exposure and development. Then, the photoresist pattern is formed as an etch barrier. A process of selectively etching the insulating film 15 filling the 14A can be performed.

 In addition, the etch stops in the etch stop layer 11 to prevent damage to the substrate 10 when the insulating layer 15 is removed.

As shown in FIG. 1E, the sacrificial layer 12 is removed. The sacrificial layer 12 may be removed by wet etching, and since the sacrificial layer 12 is formed of a material having a different etching selectivity from that of the gate electrode layer 13 and the insulating layer 15, only the sacrificial layer 12 may be selectively removed.

By removing the sacrificial layer 12, only the first gate electrode layer 13 remains on the substrate 10, and the portion of the sacrificial layer 12 remains as a space. At this time, the remaining first gate electrode film 13 can maintain its shape without being collapsed by the insulating film 15.

As shown in FIG. 1F, an oxidation process is performed to change the surface of the first gate electrode film 13 to the oxide film 16. The oxide layer 16 serves as an interlayer insulating layer to insulate between memory cells in a subsequent process. Hereinafter, the oxide layer 16 is referred to as an 'interlayer insulating layer 16'.

Since the interlayer insulating film 16 is formed by oxidizing the surface of the first gate electrode film 13, the interlayer insulating film 16 is formed along the surface of the first gate electrode film 13, and thus the upper and lower portions of the first gate electrode film 13 are formed. An interlayer insulating film 16 is formed.

On the other hand, since it is formed by surface oxidation of the first gate electrode film 13 of the interlayer insulating film 16, the space by removing the sacrificial film 12 remains as it is. In addition, the interlayer insulating film 16 is preferably formed to have the same thickness as that of the oxidized and remaining first gate electrode film 13, which is also the same as the thickness of the space by removing the sacrificial film 12.

As shown in FIG. 1G, the second gate electrode film 17 is buried in the space formed between the interlayer insulating films 16, that is, by removing the sacrificial film 12. The second gate electrode film 17 is used to form a gate electrode together with the first gate electrode film 13, and is preferably formed of polysilicon.

As shown in FIG. 1H, the second gate electrode layer 17 and the interlayer insulating layer 16 are etched to form a memory cell. The first gate electrode layer 13 may be etched together when the memory cell is formed, and all of the insulating layer 15 (see FIG. 1G) buried in the support forming trench 14B is also removed.

Subsequently, although not shown, the anti-etching film 11 under the sacrificial film removing trench and the support forming trenches 14A and 14B is etched to open the substrate 10, and the subsequent forming of the supporting forming trench 14B is performed. A tunnel insulating film is formed on the sidewall, a channel is formed by filling a conductive material, and an oxide film is embedded in the sacrificial film removing trench 14A to insulate each memory cell.

As described above, in the present invention, since the sacrificial layer 12 and the first gate electrode layer 13 are repeatedly stacked eight times to form eight stages, the memory cells of 16 stages are formed through oxidation and deposition processes. There are advantages of reducing the deposition process by 32 for stacking the stages in half, and thus reducing the stress caused by the deposition.

In addition, the interlayer insulating film 16 is formed through the oxidation process of the first gate electrode film 13, and the second gate electrode film 17 is buried in the space where the sacrificial film 12 is removed. By minimizing the difference, it is possible to prevent the deterioration of the device due to the thickness difference.

((Example 2))

2A to 2H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a second embodiment of the present invention. In the present embodiment, a description will be made on the assumption that 16 memory cells are used as one string.

As shown in FIG. 2A, an etch stop layer 21 is formed on the substrate 20. The etch stop layer 21 is to prevent contact between the substrate 20 and subsequent memory cells, and is formed of an insulating material, and the insulating material includes an oxide film.

Subsequently, the plurality of sacrificial films 23 and the first interlayer insulating film 22 are alternately and repeatedly stacked. In the case of forming sixteen memory cells, the plurality of sacrificial films 23 and the first interlayer insulating film 22 are repeatedly stacked eight times.

The sacrificial layer 23 is to secure a space in which the subsequent gate electrode and the second interlayer insulating layer are to be formed. The sacrificial layer 23 is preferably formed of a material having an etch selectivity with respect to the first interlayer insulating layer 22 and the subsequent supporting insulating layer. . The first interlayer insulating film 22 serves as an interlayer insulating layer between the memory cells together with a subsequent second interlayer insulating film, and is formed of an oxide film.

The sacrificial film 23 is adjusted in thickness in consideration of a space for forming a subsequent second interlayer insulating film and a gate electrode, and is preferably three times the thickness of the first interlayer insulating film 22.

As shown in FIG. 2B, the sacrificial film 23 and the first interlayer insulating film 22 are etched to form trenches for removing the sacrificial film and trenches 24A and 24B for forming the support.

The sacrificial film removal trench 24A is a region for separation between each memory cell, and the support forming trench 24B is a region for forming a channel. In addition, in the case of the sacrificial film removing trench 24A, the sacrificial film 23 is used to remove the subsequent sacrificial film 23, and the support forming trenches 24A and 24B collapse the first gate electrode film 23 after the sacrificial film 23 is removed. It is used as an area to be formed a support for preventing.

Sacrificial film removal trenches 24A and support forming trenches 24B may have different line widths, and sacrificial film removing trenches 24A may be formed with a line width wider than that of the support forming trenches 24B. Can be.

In addition, the support forming trenches 24B may be formed on both sides of the sacrificial layer removing trench 24A, respectively.

The trench support forming trenches 24A and 24B may be formed by etching the plurality of sacrificial layers 23 and the first interlayer insulating layer 22, and the etch stop layer 21 is not etched on the substrate 20. This remains as it is, and prevents damage to the substrate 20.

As shown in FIG. 2C, an insulating film 25 for forming a support is buried in the sacrificial film removal trench and the support formation trenches 24A and 24B. The insulating layer 25 may be formed of a material having a different etching selectivity with respect to the sacrificial layer 23 and the etch stop layer 21. For example, the insulating film 25 may be formed of a nitride film.

The insulating film 25 fills the sacrificial film removing trench and the support base forming trenches 14A and 14B and is formed on the sacrificial film 23 of the uppermost layer.

As shown in FIG. 2D, the insulating film 25 embedded in the sacrificial film removing trench 24A is removed to expose the sacrificial film removing trench 24A.

This is to secure a space for removing the sacrificial film 23, and selectively removes only the insulating film 25 embedded in the sacrificial film removal trench 24A by removing it, and is embedded in the support forming trench 24B. The insulating film 25 is left as it is. To this end, the photoresist is coated on the insulating film 25, and the photoresist pattern is formed by patterning the photoresist removal trench 24A to be opened by exposure and development to form a photoresist pattern. A process of selectively etching the insulating film 25 filling the 24A can be performed.

 In addition, etching is stopped in the etch stop layer 21 to prevent damage to the substrate 20 when the insulating layer 25 is removed.

As shown in FIG. 2E, the sacrificial layer 22 (see FIG. 2D) is removed. The sacrificial layer 22 (refer to FIG. 2D) may be removed by wet etching, and since only the sacrificial layer 23 may be selectively removed because the etching selectivity is different from that of the first interlayer insulating layer 22 and the insulating layer 25. It is possible.

By removing the sacrificial layer 23, only the first interlayer insulating layer 22 remains on the substrate 20, and the portion of the sacrificial layer 23 remains as a space. At this time, the remaining first interlayer insulating film 22 can be maintained in its shape without being collapsed by the insulating film 15.

As shown in FIG. 2F, the gate electrode film 26 is formed along a step of the entire structure including the first interlayer insulating film 22. The gate electrode film 26 functions as a gate electrode of the memory cell, and may be formed of, for example, polysilicon.

Since the gate electrode film 26 is formed along a step of the entire structure, both the gate electrode film 26 is formed above and below the first interlayer insulating film 22, and the thickness of the gate electrode film 26 is equal to the thickness of the first interlayer insulating film 22. It is preferable to form so that.

After the gate electrode film 26 is formed, the space between each gate electrode film 26 preferably remains the same thickness as that of the first interlayer insulating film 22. In FIG. 2A, since the sacrificial layer is formed to be three times the thickness of the first interlayer dielectric layer 22, two gate electrode layers 26 are formed in the space where the sacrificial layer has been removed, and thus, the first interlayer dielectric layer is formed. Only the thickness of 22) remains.

As shown in FIG. 2G, a second interlayer insulating film 27 filling the remaining space in which the gate electrode film 26 is formed is formed. The second interlayer insulating layer 27, together with the first interlayer insulating layer 22, serves as an interlayer insulating layer for insulating the memory cells.

As shown in FIG. 2H, the gate electrode layer 26 is etched to form a memory cell. When the memory cell is formed, the first and second interlayer insulating films 22 and 27 may be etched together, and the insulating film 25 (see FIG. 2G) embedded in the support forming trench 24B is also removed.

Subsequently, although not shown, the substrate 20 is opened by etching the anti-etching film 21 under the trench support forming trenches 24A and 24B for removing the sacrificial film, and the sidewall of the support forming trench 24B is subsequently processed. A tunnel insulating film is formed in the trench, a conductive material is filled in to form a channel, and an oxide film is embedded in the sacrificial film removal trench 24A to insulate each memory cell.

As described above, in the present invention, the sacrificial film 23 and the first interlayer insulating film 22 are repeatedly stacked eight times to form eight stages, and the thickness of the sacrificial film 23 is equal to the thickness of the first interlayer insulating film 22. 16 times of memory cells are formed by forming the gate electrode film 26 and the second interlayer insulating film 27 in the space where the sacrificial film 23 is removed and forming the 16-layer memory cell. The process can be cut in half, thus reducing the stress due to deposition in half.

In addition, the gate electrode film 26 may be processed only once without forming 32 processes in order to form 16 memory cells. The gate electrode film 26 and the uppermost gate electrode film ( Since 26 is formed at the same time, thermal damage to the lower gate electrode film due to the stacking of the gate electrode film 26 can be prevented. In addition, since the deposition process is performed once, it is possible to minimize device thickness by minimizing the thickness difference between the films.

Meanwhile, in the second embodiment of the present invention, the sacrificial film and the first gate electrode film are formed instead of the first interlayer insulating film, the sacrificial film is removed, and the interlayer insulating film is formed along the step of the entire structure including the first gate electrode film. It is also possible to form a memory cell by forming the second gate electrode film filling the space and etching the same.

As such, although the technical idea of the present invention has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

10: substrate 11: etching prevention film
12: sacrificial film 13: first gate electrode film
14A, 14B: open portion 15: insulating film
16 interlayer insulating film 17 second gate electrode film

Claims (17)

Alternately stacking a plurality of first gate electrode films and a sacrificial film on a substrate;
Etching the plurality of first gate electrode layers and the sacrificial layer to form a trench for forming a sacrificial layer and a trench for forming a support stand;
Filling an insulating film in the sacrificial film removing trench and the support forming trench;
Selectively removing the insulating layer embedded in the sacrificial layer removing trench;
Selectively removing the sacrificial layer; And
Removing the sacrificial layer to form an interlayer insulating layer and a second gate electrode layer on the exposed first gate electrode layer;
Nonvolatile memory device manufacturing method comprising a.
The method of claim 1,
After the forming of the second gate electrode film,
And forming a memory cell by etching the second gate electrode layer and the interlayer insulating layer.
The method of claim 2,
In the forming of the memory cell,
And the first gate electrode film is etched together.
The method of claim 1,
Forming the interlayer insulating film,
And oxidizing a surface of the first gate electrode film.
The method of claim 1,
Forming the interlayer insulating film,
And depositing an interlayer insulating film along a step of the entire structure including the first gate electrode film.
The method of claim 1,
The first and second gate electrode films are formed of polysilicon.
The method of claim 1,
Before the step of alternately stacking the first gate electrode film and the sacrificial film,
And forming an etch stop layer on the substrate.
The method of claim 1,
And forming the insulating layer embedded in the sacrificial layer removing trench and the support forming trench with a material having an etch selectivity with respect to the first gate electrode layer and the sacrificial layer.
The method of claim 1,
And forming the insulating film embedded in the sacrificial film removing trench and the support forming trench. The insulating film is formed of a nitride film.
Alternately stacking a plurality of sacrificial films and a first interlayer insulating film on a substrate;
Etching the plurality of sacrificial layers and the first interlayer insulating layer to form a trench for removing a sacrificial layer and a trench for forming a support stand;
Filling an insulating film in the sacrificial film removing trench and the support forming trench;
Selectively removing the insulating layer embedded in the sacrificial layer removing trench;
Selectively removing the sacrificial layer; And
Removing the sacrificial layer to form a gate electrode film and a second interlayer insulating film on the exposed surface of the first interlayer insulating film
Nonvolatile memory device manufacturing method comprising a.
The method of claim 10,
After the forming of the second interlayer insulating film,
Etching the gate electrode layer to form a memory cell
A nonvolatile memory device manufacturing method further comprising.
The method of claim 11,
In the forming of the memory cell,
And the first and second interlayer dielectric layers are etched together.
The method of claim 10,
The thickness of the sacrificial layer is formed to be three times the thickness of the first interlayer insulating layer.
The method of claim 10,
The gate electrode film is formed of polysilicon.
The method of claim 10,
Before the step of alternately stacking the sacrificial film and the first interlayer insulating film,
And forming an etch stop layer on the substrate.
The method of claim 10,
And forming the insulating layer embedded in the sacrificial film removing trench and the support forming trench with a material having an etch selectivity with respect to the first interlayer insulating film and the sacrificial film.
The method of claim 10,
And forming the insulating film embedded in the sacrificial film removing trench and the support forming trench. The insulating film is formed of a nitride film.

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