KR20110114038A - Reram memory device with multi-level and manufacturing method of the same - Google Patents

Abstract

The present invention discloses a ReRAM memory device and a method of manufacturing the same. The ReRAM memory device of the present invention can program multiple levels by selectively changing a resistance state of each region by forming a plurality of regions having different electrical thicknesses in a resistance change layer whose resistance state changes in accordance with an applied electric field. Can be. Accordingly, the present invention can manufacture a ReRAM memory device that can be easily multi-level programmed by adjusting the type of the resistive change material constituting each region of the resistive change layer and the physical thickness of the material.

Description

Relevel memory device with multi-level and manufacturing method of the same

The present invention relates to a nonvolatile memory device, and more particularly to a resistance change memory device.

A semiconductor memory device is a memory device that stores data and can be read out when needed. Semiconductor memory devices can be roughly divided into random access memory (RAM) and read only memory (ROM). ROM is nonvolatile memory that does not lose its stored data even when its power is interrupted. The ROM includes PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), and Flash Memory Device. RAM is a so-called volatile memory that loses its stored data when the power is turned off. RAM includes Dynamic RAM (DRAM) and Static RAM (SRAM).

In addition, semiconductor memory devices that replace DRAM capacitors with nonvolatile materials are emerging. Phase change memory devices using ferroelectric RAM (FRAM) using ferroelectric capacitors, magnetic RAM (MRAM) using TMR (tunneling magneto-resistive) films, and chalcogenide alloys (phase change memory device), a memory device of a SONOS structure for capturing charge in a nitride film and performing a program, and a resistance memory (ReRAM) using a resistance change.

Among these, a resistive random access memory device (hereinafter referred to as a "ReRAM") refers to a device to be used as a nonvolatile memory by using a rapidly changing resistance state of a thin film according to a specific voltage applied to the thin film. .

ReRAM devices have no deterioration for infinite recording and playback, can operate at high temperatures, and have excellent advantages such as non-volatile data stability. In addition, when the input pulse is applied, high-speed operation is possible about 10 to 20 ns when the resistance change is more than 1000 times. In addition, since the resistive layer of the ReRAM device has a single layer structure in process, high integration and high speed are possible, and the conventional CMOS process and integration process technology can be used to minimize energy consumption.

1 is a cross-sectional view of a conventional ReRAM device. Referring to FIG. 1, a ReRAM device has a structure including a lower electrode 12, a resistance layer 14, and an upper electrode 16 sequentially formed on a substrate 10. In this case, the lower electrode 12 and the upper electrode 16 are made of a general conductive material, and mainly made of metal.

As the material of the resistive layer 24 of the ReRAM device, oxides are currently used. Specifically, binary oxides and perovskite oxides are used as oxides, and recently, the perovskite oxides are used. The metal is doped or contained in the oxide.

However, the conventional ReRAM device has a single bit structure representing either the logic value '0' or the logic value '1' depending on the size of the resistor. Therefore, there is a need for a memory device having an increased information storage capability capable of programming two or more states without increasing the size of the memory device.

An object of the present invention is to provide a multi-level ReRAM memory device capable of programming a plurality of levels in one cell and a method of manufacturing the same.

A multilevel ReRAM memory device according to a preferred embodiment of the present invention for solving the above problems is a semiconductor substrate; A lower electrode layer formed on the semiconductor substrate; A resistance change layer in which a plurality of regions having different electrical thicknesses are formed in parallel on the lower electrode layer and whose resistance is changed according to the intensity of an applied electric field, thereby controlling the amount of current flowing; And the upper electrode layer formed on the resistance change layer.

The resistance change layer may include: a first region in which a first resistance change material is formed; A second region formed such that the first resistance change material and the second resistance change material are sequentially stacked; And a third region in which the second resistance change material is formed.

In addition, the dielectric constant of the second resistance change material is preferably smaller than the dielectric constant of the first resistance change material.

In addition, the physical thickness of the first region is preferably the same as the physical thickness of the first resistance change material formed in the second region.

In addition, the physical thickness of the third region is preferably the same as the physical thickness of the second region.

In addition, it is preferable that the electrical thickness of the third region is the thickest and the electrical thickness of the first region is the thinnest.

In addition, the resistance change layer may be formed of resistance change materials in which a plurality of regions have different dielectric constants.

On the other hand, the multi-level ReRAM memory device manufacturing method according to a preferred embodiment of the present invention for solving the above problems, (a) forming a lower electrode layer on a semiconductor substrate; (b) forming a resistance change layer on the lower electrode layer to control an amount of current flowing according to an applied electric field such that a plurality of regions having different electrical thicknesses are formed in parallel on the lower electrode layer; And (c) forming the upper electrode layer on the resistance change layer.

In the step (b), the first region is formed of a first resistance change material, and the second region is formed so that the first resistance change material and the second resistance change material are sequentially stacked, and the second resistance is formed. The third region may be formed of the change material.

In addition, the dielectric constant of the second resistance change material is preferably smaller than the dielectric constant of the first resistance change material.

In addition, in the step (b), it is preferable to form the resistance change layer such that the physical thickness of the first region is the same as the physical thickness of the first resistance change material formed in the second region.

In addition, in the step (b), it is preferable to form the resistance change layer such that the physical thickness of the third region is the same as the physical thickness of the second region.

In the step (b), it is preferable to form the resistance change layer such that the electrical thickness of the third region is the thickest and the electrical thickness of the first region is the thinnest.

In addition, the step (b) may include: (b1) forming a first resistance change material layer in the first region and the second region on the lower electrode layer; (b2) forming a photoresist on the first resistive change material layer corresponding to the first region and depositing a second resistive change material thicker than the first resistive change material layer to form the photoresist in the second region. Forming a second resistive change material layer over the first resistive change material layer and the lower electrode layer in the third region; And (b3) removing and planarizing an upper portion of the second resistance change material layer to expose the photoresist, and removing the photoresist.

According to the present invention, a plurality of regions having different electrical thicknesses are formed in a resistance change layer in which a resistance state changes in accordance with an applied electric field, thereby selectively changing the resistance state of each region, thereby enabling multi-level programming. Accordingly, the present invention can manufacture a ReRAM memory device that can be easily multi-level programmed by adjusting the type of the resistive change material constituting each region of the resistive change layer and the physical thickness of the material.

1 is a view showing the structure of a conventional ReRAM memory device.
2 is a diagram showing the structure of a multi-level ReRAM memory device according to a preferred embodiment of the present invention.
3 is a diagram illustrating an operation of a multilevel ReRAM memory device according to an exemplary embodiment of the present invention.
4A-4F illustrate a method of manufacturing a multilevel ReRAM memory device in accordance with a preferred embodiment of the present invention.
5 is a diagram illustrating an example of a modified embodiment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a diagram showing the structure of a multi-level ReRAM memory device according to a preferred embodiment of the present invention. Referring to FIG. 2, a multilevel ReRAM memory device according to an exemplary embodiment of the present invention has a structure in which a lower electrode layer 220, a resistance change layer 230, and an upper electrode layer 240 are sequentially formed on a semiconductor substrate 210. Has

The semiconductor substrate 210 and the lower electrode layer 220 are formed in the same manner as the manufacturing method of the conventional general ReRAM memory device described above.

The resistance change layer 230 has a path (filament) through which current can flow according to the magnitude of the applied bias voltage (that is, the magnitude of the applied electric field) to control the flow of the current, thereby changing the internal resistance characteristics. do. In particular, the resistance change layer 230 according to the preferred embodiment of the present invention uses three resistance change materials to form three regions having different electrical thicknesses in parallel on the lower electrode layer 220, thereby providing four levels ( 2bit) state can be programmed.

The upper electrode layer 240 is formed on the resistance change layer 230, and an electric field may be applied to the resistance change layer 230 by applying a voltage to the upper electrode layer 240.

3 is a diagram illustrating an operation of a multilevel ReRAM memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the general resistance change material has a defect therein, such as silicon nitride (Si ₃ N ₄ ), and tunnels from the lower electrode layer 220 and the upper electrode layer 240 to flow therein. It is formed of a material capable of capturing a charged charge.

In addition, when a program voltage (bias voltage) is applied to the upper electrode layer 240 and the lower electrode layer 220, charges are introduced into the resistance change layer 230 to be trapped, and the introduced charges are arbitrarily connected to each other to flow a current. To form a path (filament 235). The current flows through the thus formed path, so that the resistance change layer 230 is changed and maintained in a low resistance state.

Then, when the program erase voltage is applied, charges trapped inside the resistance change layer 230 flow out to the upper electrode layer 240 or the lower electrode layer 220, and the connected filaments are disconnected one by one in the low resistance state, thereby changing to a high resistance state. Until the next program voltage is applied.

As shown in FIG. 2 and FIG. 3, the resistance change layer 230 according to the preferred embodiment of the present invention may include a first region 230-1 and a first resistance change composed of only the first resistance change material layer 231. The second region 230-2 in which the material layer 231 and the second resistance change material layer 232 are stacked, and the third region 230-3 consisting of only the second resistance change material layer 232 are provided in the lower electrode layer. 220 is arranged in parallel with each other above.

At this time, the first resistance change material layer 231 of the first region 230-1 and the first resistance change material layer 231 positioned in the second region 230-2 are integrally formed to have the same thickness. desirable. In addition, the entire thickness of the second region 230-2 is preferably the same as the entire thickness of the third region 230-3. Accordingly, the top surface of the second resistance change material layer 232 disposed in the second region 230-2 may be planarized to coincide with the top surface of the second resistance change material layer 232 of the third region 230-3. have.

In addition, the first region 230-1 to the third region 230-3 are formed so that electrical thicknesses are different from each other, and the resistance state of each region of the resistance change layer is applied by applying an electric field having a size corresponding to each region. It can be selectively changed to enable multi-level programming.

In the preferred embodiment of the present invention shown in Figs. 2 and 3, the resistance change layer 230 is divided into three regions, and an electric field is applied to the resistance change layer 230 in a three-step size. The three regions are configured to switch between high and low resistance states, respectively, thereby implementing a multi-level program. The thicker the electrical thickness, the higher the field means that the resistance state changes when a larger electric field is applied.

In the example shown in FIGS. 2 and 3, the materials are selected such that the dielectric constant of the first resistance change material is greater than the dielectric constant of the second resistance change material, such that the electrical thickness of each region is increased by the third region 230. -3) was formed to be the largest and the first region 230-1 to be the smallest.

Referring to FIG. 3, the dielectric constant of the first resistance change material A is 9, the dielectric constant of the second resistance change material B is 4, and the physical thickness of the first region 230-1 is Assuming that the physical thickness of 10 nm, the second region 230-2 is 20 nm, and the physical thickness of the third region 230-3 is 20 nm, the first region 230-based on the first resistance change material The electrical thickness EOT of each of the first through third regions 230-3 is 10 nm (the first region 230-1) and 32.5 nm (the second region 230-2), respectively, according to Equation 1 below. , 45 nm (third region 230-3).

In Equation 1, d represents the physical thickness, k _A represents the dielectric constant of the reference material, k of the molecule represents the dielectric constant of the material to be measured relatively.

In the lower part of FIG. 3, the magnitude of the electric field required to change the resistance corresponding to the electrical thickness is schematically illustrated. As shown in FIG. 3, even when a small electric field is applied, the resistance state of the first region 230-1 having a small electrical thickness can be changed, while the third region 230-3 has a thick electrical thickness. To change the resistance state, a large electric field must be applied. Therefore, the multi-level can be programmed by dividing the magnitude of the electric field required for the resistance change by adjusting the electrical thickness in three stages.

Set the state (programmed state) of logic value [00] to level 0, set the state programmed with logic value [01] to level 1, and set the state programmed with logic value [10] to level 2 When the state in which the logic value [11] is programmed is set to level 3, in the level 0 state, no current flows as the high resistance state in all of the first region 230-1 to the third region 230-3.

In order to program the level 1, when the first set voltage Vset1 sufficient to change the resistance state of the first region 230-1 is applied to the upper electrode layer 240, the resistance of the first region 230-1 is applied. The change material A changes from a high resistance state to a low resistance state so that a current can flow. However, the second region 230-2 and the third region 230-3 remain in a high resistance state so that no current flows.

In order to program level 2, when the second set voltage Vset2 (Vset2> Vset1) sufficient to change the resistance state of the second region 230-2 is applied to the upper electrode layer 240, the first region 230 -1) and the resistance change material A located in the second region 230-2, as well as the resistance change material B in the second region 230-2, change from a high resistance state to a low resistance state, Both the first region 230-1 and the second region 230-2 are changed from a high resistance state to a low resistance state, and current flows through the first region 230-1 and the second region 230-2. Will flow. Therefore, a larger amount of current can flow than level 1. However, the third region 230-3 is maintained in a high resistance state so that no current flows.

Finally, in order to program level 3, if a third set voltage Vset3 (Vset3> Vset2> Vset1) sufficient to change the resistance state of the third region 230-3 is applied to the upper electrode layer 240, All the resistance change materials (A, B) of the first region 230-1 to the third region 230-3 are changed from the high resistance state to the low resistance state, and through all the regions of the resistance change layer 230. Current will flow. Therefore, a larger amount of current can flow than level 2.

The state programmed as described above is identified by checking the amount of current flowing when a read voltage is applied to the upper electrode layer 240.

The programmed state may be erased by applying a voltage having a polarity opposite to that applied during programming to the upper electrode layer 240.

In the above-described preferred embodiment of the present invention, the program set voltages Vset3, Vset2, and Vset1 are set to 3V, 2V, and 1V, respectively, and applied to the upper electrode layer 240 for a time of 500 ns.

So far, the configuration of the multi-level ReRAM memory device according to the preferred embodiment of the present invention has been described. Hereinafter, a manufacturing method thereof will be described with reference to FIGS. 4A to 4F.

4A-4F illustrate a method of manufacturing a multilevel ReRAM memory device in accordance with a preferred embodiment of the present invention. Referring to FIGS. 4A to 4F, first, the lower electrode layer 220 is formed on the semiconductor substrate 210 by depositing it (see FIG. 4A).

The semiconductor substrate 210 can be any one as long as it is used for fabricating a conventional semiconductor memory device and is not particularly limited in the present invention. Typically, a Si substrate, a SiO ₂ substrate, a Si / SiO ₂ multilayer substrate, a polysilicon substrate, or the like may be used.

The lower electrode layer 220 formed on the substrate may be formed of the same material and thickness as an electrode generally used in a ReRAM device. That is, the lower electrode layer 220 may be formed using Ag, Pt, Au, Al, Cu, Ti, alloys thereof, or the like with a thickness of 5 to 500 nm.

When the lower electrode layer 220 is formed, as shown in FIG. 4B, the first resistance change material is deposited on the lower electrode layer 220 to form the first resistance change material layer 231 having a thickness of 5 to 500 nm. . The first resistance change material may be Nb2O5, NiO, MgO, TiO2, ZrO2, CuO2, or Cubic perobskite oxides, Nb: SrTiO3, Cr: SrTiO3, Cr: SrZrO3, or PrxCa1-xMnO3. And the like can be used.

Thereafter, as shown in FIG. 4C, a position at which the first region 230-1, the second region 230-2, and the third region 230-3 of the resistance change layer 230 is formed is formed. The photoresist 410 is formed in a position corresponding to the first region 230-1 and the second region 230-2 on the first resistance change material layer 231, and the third region 230. The first resistance change material layer 231 formed at the position corresponding to −3) is etched and removed.

When the resistive change material layer of the third region 230-3 is removed, as shown in FIG. 4D, the existing photoresist 410 is removed, and the first resistive material layer 231 remains on the first resistive change material layer 231. The photoresist 420 is again formed at a position corresponding to the region 230-1, and a second resistance change material layer is deposited thereon to form the second resistance change material layer 232. In this case, as the second resistance change material, a material having a different dielectric constant from the first resistance change material is used among the above-described resistance change materials, and preferably, a material having a smaller dielectric constant than the first resistance change material is used. do.

When the process illustrated in FIG. 4D is performed, the first resistive change material layer 231, the photoresist 420, and the second resistive change material layer 232 may be formed in the first region 230-1 of the resistive change layer 230. ) Is sequentially formed, and the first resistive change material layer 231 and the second resistive change material layer 232 are sequentially formed in the second region 230-2, and in the third region 230-3. The second resistance change material layer 232 is formed on the lower electrode layer 220.

Thereafter, as shown in FIG. 4E, after the upper portion of the second resistance change material layer 232 is removed and planarized, the photoresist 420 formed in the first region 230-1 is removed. Then, only the first resistance change material layer 231 remains in the first region 230-1, and the first resistance change material layer having the same thickness as the first region 230-1 remains in the second region 230-2. 231 and a second resistance change material layer 232 are formed, and a second resistance change material layer 232 having the same thickness as that of the second area 230-2 is formed in the third region 230-3. have.

Thereafter, as illustrated in FIG. 4F, the upper electrode layer 240 having the same material as the lower electrode layer 220 over the resistance change layer 230 over the first region 230-1 to the third region 230-3. ) To complete the multilevel ReRAM memory device.

As described above, according to the present invention, when the first resistance change material and the second resistance change material are selected as materials having different dielectric constants, and the physical thicknesses of these material layers are adjusted, each region of the resistance change layer 230 The electrical thickness can be set differently. Therefore, the magnitude of the electric field to be applied in order to change the resistance state can be separated into a plurality, thereby enabling a plurality of levels of programming.

In addition to the above-described preferred embodiments of the present invention, the area of the resistance change layer 230 is divided into a plurality of areas, and the magnitude of the electric field (that is, the magnitude of the voltage applied to the electrode) required for changing the resistance state of each area is clearly defined. If the modified form so that it can be separated, it is included within the scope of the technical idea of the present invention.

For example, as shown in FIG. 5, the lower electrode layer 520, the resistance change layer 530, and the upper electrode layer 540 are sequentially formed on the semiconductor substrate 510, and the resistance change layers 530 are identical to each other. It is also possible to form three resistance change material layers 530-1, 530-2, and 530-3 having a physical thickness and different dielectric constants in parallel with each other.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

210 semiconductor substrate
220 Lower electrode layer
230 resistance change layer
230-1 first area
230-2 second area
230-3 third area
231 first resistance change material layer
232 second resistance change material layer
240 upper electrode layer

Claims (14)

A semiconductor substrate;
A lower electrode layer formed on the semiconductor substrate;
A resistance change layer in which a plurality of regions having different electrical thicknesses are formed in parallel on the lower electrode layer and whose resistance is changed according to the intensity of an applied electric field, thereby controlling the amount of current flowing; And
And an upper electrode layer formed on the resistance change layer. The method of claim 1, wherein the resistance change layer
A first region in which a first resistance change material is formed;
A second region formed such that the first resistance change material and the second resistance change material are sequentially stacked; And
And a third region in which the second resistance change material is formed. The method of claim 2,
And the dielectric constant of the second resistance change material is less than the dielectric constant of the first resistance change material. The method of claim 3, wherein
And wherein the physical thickness of the first region is the same as the physical thickness of the first resistive change material formed in the second region. The method of claim 3, wherein
The physical thickness of the third region is the same as the physical thickness of the second region. The method of claim 3, wherein
And wherein the electrical thickness of the third region is the thickest and the electrical thickness of the first region is the thinnest. The method of claim 1, wherein the resistance change layer
And wherein the plurality of regions are formed of resistive change materials having different dielectric constants. (a) forming a lower electrode layer on the semiconductor substrate;
(b) forming a resistance change layer on the lower electrode layer to control an amount of current flowing according to an applied electric field such that a plurality of regions having different electrical thicknesses are formed in parallel on the lower electrode layer; And
(c) forming an upper electrode layer over the resistance change layer. The method of claim 8, wherein step (b)
Forming a first region with a first resistance change material,
Forming a second region such that the first resistance change material and the second resistance change material are sequentially stacked;
And forming a third region of the second resistance change material. The method of claim 9,
And wherein the dielectric constant of the second resistance change material is less than the dielectric constant of the first resistance change material. The method of claim 10, wherein step (b)
And forming the resistance change layer such that the physical thickness of the first region is equal to the physical thickness of the first resistance change material formed in the second region. The method of claim 10, wherein step (b)
And forming the resistance change layer such that the physical thickness of the third region is equal to the physical thickness of the second region. The method of claim 10, wherein step (b)
And forming the resistance change layer such that the electrical thickness of the third region is the thickest and the electrical thickness of the first region is the thinnest. The method of claim 10, wherein step (b)
(b1) forming a first resistance change material layer in the first region and the second region on the lower electrode layer;
(b2) forming a photoresist on the first resistive change material layer corresponding to the first region and depositing a second resistive change material thicker than the first resistive change material layer to form the photoresist in the second region. Forming a second resistive change material layer over the first resistive change material layer and the lower electrode layer in the third region; And
(b3) removing and planarizing an upper portion of the second resistive change material layer to expose the photoresist, and removing the photoresist.

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