KR20110104861A - Image display device - Google Patents

Abstract

The present invention relates to an image display device capable of selectively implementing 2D and 3D images.
The image display device includes a display panel for selectively implementing a 2D image and a 3D image including a plurality of red, green, and blue subpixels; And a pattern retarder disposed in front of the display panel and dividing light from the display panel into first polarized light and second polarized light when the 3D image is implemented. Each of the subpixels includes: a main subpixel including a first pixel electrode to which a data voltage from a data line is applied, and a common electrode opposite to the first pixel electrode and to which a common voltage from a common line is applied; A second sub-pixel including a second pixel electrode to which the data voltage is applied, the common electrode facing the second pixel electrode, and a discharge TFT selectively connecting the second pixel electrode and the common electrode according to an implementation image; do.

Description

Video display device {IMAGE DISPLAY DEVICE}

The present invention relates to an image display device capable of realizing a two-dimensional plane image (hereinafter referred to as '2D image') and a three-dimensional stereoscopic image (hereinafter referred to as '3D image').

The image display device implements a 3D image by using a binocular parallax technique or an autostereoscopic technique.

The binocular parallax method uses a parallax image of the left and right eyes with a large stereoscopic effect, and there are glasses and no glasses, both of which are put to practical use. The spectacle method displays polarized images by changing the polarization direction of the left and right parallax images on a direct-view display device or a projector or time-division method, and implements a stereoscopic image using polarized glasses or liquid crystal shutter glasses. An optical plate, such as a parallax barrier, is installed in front of or behind the display screen to separate the display.

The spectacle method may include a patterned retarder 5 for switching polarization characteristics of light incident on the polarizing glasses 6 on the display panel 3 as shown in FIG. 1. The spectacle method alternately displays the left eye image L and the right eye image R on the display panel 3, and switches the polarization characteristics incident on the polarizing glasses 6 through the pattern retarder 5. By doing so, the spectacle method can spatially divide the left eye image (L) and the right eye image (R) to implement a 3D image. In FIG. 1, reference numeral '1' denotes a backlight unit for irradiating light onto the display panel 3, and reference numerals '2' and '4' denote polarizers attached to upper and lower surfaces of the display panel 3 to select linear polarization. Respectively.

In the glasses method, visibility of the 3D image is inferior due to the crosstalk generated at the upper and lower viewing angle positions. As a result, the upper and lower viewing angles for viewing a 3D image with good image quality in a conventional spectacle system are very narrow. In the crosstalk, the left eye image L passes not only the left eye pattern retarder area but also the right eye pattern retarder area at the upper and lower viewing angle positions. Is caused because it passes through. Accordingly, as shown in FIG. 2, the black stripe BS is formed in the pattern retarder area corresponding to the black matrix BM of the display panel to secure the upper and lower viewing angles to increase the visibility of the 3D image. It was proposed through Japanese Unexamined Patent Publication No. 2002-185983. In FIG. 2, when viewed at a distance D, the viewing angle α in which no crosstalk occurs theoretically is determined by the size of the black matrix BM of the display panel, the size of the black stripe BS of the pattern retarder, and the display panel. And the spacer S between the pattern retarder and the pattern retarder. The viewing angle α becomes wider as the size of the black matrix BM and the black stripe BS increases, and the smaller the spacer S between the display panel and the pattern retarder becomes smaller.

However, the prior art has the following problems.

First, the black stripe of the pattern retarder used to improve the visibility of the 3D image by improving the viewing angle generates moire by interacting with the black matrix of the display panel, thereby greatly reducing the visibility of the 2D image when implementing the 2D image. Drop. 3 is a result of observing a sample of a 47-inch display device at a distance of 4 m from the display device to which the black stripe is applied. It is recognized as 355mm.

Second, the black stripe used to improve the visibility of the 3D image by improving the viewing angle causes a side effect that greatly reduces the brightness of the 2D image. As shown in (b) of FIG. 4, the pixel of the display panel is partially hidden by the black stripe (BS) pattern in the prior art, so that the black stripe (BS) is not formed in the 2D image. This is because the amount of light transmitted is reduced by about 30% compared to the case of (a).

Accordingly, an object of the present invention is to provide an image display device capable of improving both visibility of 2D and 3D images and preventing luminance reduction when implementing 2D images.

In order to achieve the above object, an image display apparatus according to an embodiment of the present invention comprises a display panel for selectively implementing a 2D image and a 3D image including a plurality of red, green and blue subpixels; And a pattern retarder disposed in front of the display panel and dividing light from the display panel into first polarized light and second polarized light when the 3D image is implemented. Each of the subpixels includes: a main subpixel including a first pixel electrode to which a data voltage from a data line is applied, and a common electrode opposite to the first pixel electrode and to which a common voltage from a common line is applied; A second sub-pixel including a second pixel electrode to which the data voltage is applied, the common electrode facing the second pixel electrode, and a discharge TFT selectively connecting the second pixel electrode and the common electrode according to an implementation image; do.

The present invention divides each of the subpixels into a main subpixel and an auxiliary subpixel, displays the same 2D image as the main subpixel in the auxiliary subpixel when implementing the 2D image, and displays a black image in the auxiliary subpixel when implementing the 3D image. Display.

As a result, the image display device according to the present invention can improve both visibility of 2D and 3D images, and can prevent a decrease in luminance, particularly when realizing 2D images.

1 is a view schematically showing an eyeglass type image display device.
2 is a view illustrating an image display apparatus in which a conventional black stripe pattern is formed.
3 is a diagram showing that moiré is generated due to a black stripe pattern.
4 is a diagram showing a decrease in the amount of light transmitted due to the black stripe pattern.
5 is a block diagram illustrating an image display device according to an embodiment of the present invention.
6 shows a unit pixel structure.
7 illustrates a first example of a connection structure of sub-pixels.
8 shows a second example of a connection structure of sub-pixels.
9 shows a charging waveform of a subpixel, together with a waveform of signals for operating the subpixels of FIGS. 7 and 8;
10 is a view showing a third example of the connection structure of sub-pixels.
11 shows a fourth example of the connection structure of sub-pixels.
12 shows a charging waveform of a subpixel along with a waveform of signals for operating the subpixels of FIGS. 10 and 11;
Fig. 13 shows an example of extension of the period during which the discharge TFT is turned on.
14A shows an image displayed on a unit pixel in 3D mode.
14B is a view showing an image displayed on a unit pixel in 2D mode.
15 is a graph showing the relationship between the vertical pitch of the auxiliary subpixels and the 3D viewing angle.
FIG. 16 is a diagram schematically illustrating an operation of an image display apparatus in a 3D mode. FIG.
FIG. 17 is a view schematically showing an operation of an image display device in a 2D mode. FIG.
18 is a graph illustrating crosstalk values of 3D images according to 3D viewing angles.
19 is a graph comparing the image side angle of view of the 3D image according to an embodiment of the present invention with the prior art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 19.

5 shows an image display apparatus according to an embodiment of the present invention. 6 shows a unit pixel structure of an image display device.

Referring to FIG. 5, an image display apparatus according to an exemplary embodiment of the present invention may include a display element 11, a controller 12, a panel driving circuit 14, a pattern retarder 18, a polarizing glasses 20, and the like. Equipped. The pattern retarder 18 and the polarizing glasses 20 are 3D driving elements to spatially separate the left eye image and the right eye image to implement binocular disparity.

The display element 11 may be implemented as a liquid crystal display element. The liquid crystal display device includes a display panel 10, a backlight unit 17 disposed under the display panel 10, and an upper polarizer disposed between the display panel 10 and the pattern retarder 18. 16a and a lower polarizing film 16b disposed between the display panel 10 and the backlight unit 17.

The display panel 10 has two glass substrates and a liquid crystal layer sandwiched therebetween. A TFT array (Thin Film Transistor Array) is formed on the lower glass substrate. The TFT array includes a plurality of data lines supplied with R (red), G (green), and B (blue) data voltages, and a plurality of gate lines provided with gate pulses (or scan pulses) crossing the data lines. Or scan lines), a plurality of TFTs (Thin Film Transistors) formed at intersections of the data lines and the gate lines, each pixel electrode for charging a data voltage to the liquid crystal cells, and a pixel electrode connected to the pixel electrode. Storage capacitors for maintaining the voltage of the storage unit (Storage Capacitor) and the like. A color filter array is formed on the upper glass substrate. The color filter array includes a black matrix, a color filter, and the like. The common electrode, which forms an electric field facing the pixel electrode, is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and is formed in IPS (In Plane Switching) mode and FFS (Fringe). In a horizontal electric field driving method such as a field switching mode, the pixel electrode may be formed on the lower glass substrate together with the pixel electrode. The liquid crystal cell is driven in a normally black mode in which the transmittance or gray level increases as the potential difference between the data voltage and the common voltage increases. The upper polarizing film 16a is attached to the upper glass substrate, and the lower polarizing film 16b is attached to the lower glass substrate, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal. Column spacers may be formed between the glass substrates to maintain a cell gap of the liquid crystal cell.

The unit pixel P formed in the display panel 10 includes an R subpixel SPr, a G subpixel SPg, and a B subpixel SPb. The R subpixel SPr includes an R main subpixel SPr1 and an R auxiliary subpixel SPr2 disposed on both sides of the gate line GLj. The R main sub pixel SPr1 and the R auxiliary sub pixel SPr2 are electrically connected to the first data line DLj when the gate line GLj is activated. The G subpixel SPg includes a G main subpixel SPg1 and a G auxiliary subpixel SPg2 disposed on both sides of the gate line GLj. The G main sub pixel SPg1 and the G auxiliary sub pixel SPg2 are electrically connected to the second data line DL (j + 1) when the gate line GLj is activated. The B subpixel SPb includes a B main subpixel SPb1 and a B auxiliary subpixel SPb2 disposed on both sides of the gate line GLj. The B main subpixel SPb1 and the B auxiliary subpixel SPb2 are electrically connected to the third data line DL (j + 2) when the gate line GLj is activated. The connection structure and operation effect of the subpixel in detail will be described later with reference to FIGS. 7 to 15.

The panel driving circuit 14 includes a data driving circuit for driving data lines of the display panel 10 and a gate driving circuit for driving gate lines of the display panel 10. The data driving circuit converts the RGB digital video data of the 2D / 3D data format into an analog gamma voltage under the control of the controller 12 to generate RGB data voltages, and supplies the RGB data voltages to the data lines. The gate driving circuit generates a scan pulse under the control of the controller 12 and uses the scan pulse to sequentially activate the gate lines.

The controller 12 may display the panel driving circuit in the 2D mode (Mode_2D) or 3D mode (Mode_3D) in response to the mode selection signal input through the user interface (not shown) or the 2D / 3D identification code extracted from the input image signal. 14). The controller 12 may generate the control voltage Vct at different levels according to the mode as shown in FIG. 9. For example, the controller 12 generates the control voltage Vct at the first level L1 under the 3D mode Mode_3D and lowers the control voltage Vct at the first level L1 under the 2D mode Mode_2D. Can occur at two levels (L2). In addition, the controller 12 may generate the same or different voltages applied to the first control line VL1 and the second control line VL2 according to the mode as shown in FIG. 12. For example, the controller 12 generates the voltage applied to the first control line VL1 at the first level Vdd and the voltage applied to the second control line VL2 under the 3D mode Mode_3D. The second level Vss may be lower than the level Vdd. The controller 12 may generate voltages applied to the first and second control lines VL1 and VL2 at the second level Vss under the 2D mode Mode_2D.

The controller 12 uses the 3D data format RGB digital video data input from the video source under the 3D mode (Mode_3D), respectively, according to the resolution of the display panel 10. The left eye RGB data (hereinafter, referred to as "left eye data") And right eye RGB data of the 3D data format (hereinafter referred to as "right eye data"), the left eye data and the right eye data are alternately supplied to the data driving circuit one by one horizontal line. The data detach operation may be performed on an external system board. The controller 12 aligns the RGB digital video data of the 2D data format input from the video source under the 2D mode (Mode_2D) according to the resolution of the display panel 10 and supplies them to the data driving circuit.

The controller 12 generates timing control signals for controlling the operation timing of the panel driving circuit 14 by using synchronization signals such as a vertical synchronization signal, a horizontal synchronization signal, a dot clock, and a data enable input from the system board. . The controller 12 may control the operation of the panel driving circuit 14 at a frame frequency of N × f (N is a positive integer greater than or equal to 2 and f is an input frame frequency) Hz by doubling the timing control signals by an integer multiple.

The backlight unit 17 includes a plurality of light sources and a plurality of optical members that convert light from the light sources into a surface light source and irradiate the display panel 10. The light sources may be one or more of Hot Cathode Fluorescent Lamp (HCFL), Cold Cathode Fluorescent Lamp (CCFL), External Electrode Fluorescent Lamp (EEFL), Flange Focal Length (FFL), and Light Emitting Diode (LED). Can be. Optical members include a light guide plate (or diffuser plate), a prism sheet, a diffuser sheet, and the like to increase the plane uniformity of light from the light sources.

The pattern retarder 18 may be patterned on any one of a glass substrate, a transparent plastic substrate, and a film. The substrate on which the pattern retarder 18 is formed is attached to the upper polarizing film 16a through an adhesive. The pattern retarder 18 includes first and second retarders in which the light absorption axes are perpendicular to each other to divide the 3D image into polarization components. The first retarder is formed in the radix line of the pattern retarder 18 to transmit the first polarized light (circularly polarized light or linearly polarized light) component among the light incident through the upper polarizing film 16a. The second retarder is formed on the even line of the pattern retarder 18 to transmit a second polarized light (circularly polarized light or linearly polarized light) component among the light incident through the upper polarizing film 16a. For example, the first retarder may be implemented as a polarization filter that transmits left circularly polarized light, and the second retarder may be implemented as a polarization filter that transmits right circularly polarized light.

The polarization glasses 20 have different light absorption axes according to polarization components emitted from the pattern retarder 18. For example, the left eye of the polarizing glasses 20 transmits the left circularly polarized light incident from the first retarder of the pattern retarder 18 and blocks light of other polarization components, and the right eye of the polarizing glasses 20 is It transmits right circularly polarized light incident from the second retarder of the pattern retarder 18 and blocks light of other polarization components. In this case, the left eye of the polarizing glasses 20 may include a left circular polarization filter, and the right eye of the polarizing glasses 20 may include a right circular polarization filter.

7 to 15 are diagrams for describing a connection structure and an operation effect of a subpixel. Here, the subpixels correspond to the R subpixels, the G subpixels, and the B subpixels, respectively.

As shown in FIGS. 7 and 8, the subpixel SP includes a main subpixel SP1 and an auxiliary subpixel SP2 disposed on both sides of the gate line GLk.

Referring to FIG. 7, the main sub pixel SP1 includes a first pixel electrode Ep1 and a common electrode Ec that face each other. The first pixel electrode Ep1 is selectively connected to the data line DLk through the first TFT ST1. The first TFT ST1 is turned on in response to the k (k is a positive integer) th scan pulse SPk to apply the data voltage Vdata on the kth data line DLk to the first pixel electrode Ep1. do. To this end, the gate electrode of the first TFT ST1 is connected to the k-th gate line GLk, the source electrode is connected to the k-th data line DLk, and the drain electrode is connected to the first pixel electrode Ep1. do. The common electrode Ec is connected to the common line CL charged with the common voltage Vcom.

The auxiliary sub-pixel SP2 includes the second pixel electrode Ep2 and the common electrode Ec which face each other, and the second pixel electrode Ep2 and the common electrode (2) according to the driving mode (2D / 3D mode). A discharge TFT (DST) for selectively connecting Ec). The second pixel electrode Ep2 is selectively connected to the first pixel electrode Ep1 through the second TFT ST2. The second TFT ST2 is turned on in response to the k-th scan pulse SPk to apply the data voltage Vdata on the first pixel electrode Ep1 to the second pixel electrode Ep2. To this end, the gate electrode of the second TFT ST2 is connected to the k-th gate line GLk, the source electrode is connected to the first pixel electrode Ep1, and the drain electrode is connected to the second pixel electrode Ep2. do. The discharge TFT DST is turned on in response to the k + 1th scan pulse SP (k + 1) applied through the control TFT CT to share the data voltage Vdata of the second pixel electrode Ep2. Discharge at the voltage Vcom level. To this end, the gate electrode of the discharge TFT DST is connected to the k + 1th gate line GL (k + 1) through the control TFT CT, and the source electrode is connected to the second pixel electrode Ep2. The drain electrode is connected to the common electrode Ec.

The control TFT CT for switching the current path between the k + 1th gate line GL (k + 1) and the gate electrode of the discharge TFT DST is switched according to the control voltage Vct input from the controller. The action is controlled. The gate electrode of the control TFT CT is connected to the input terminal of the control voltage Vct, the source electrode is connected to the k + 1th gate line GL (k + 1), and the drain electrode of the discharge TFT DST. It is connected to the gate electrode. The control TFT CT may be disposed in the non-display area NAA of the display panel in which no image is displayed. On the other hand, "AA" shown in the drawing indicates a display area of a display panel that displays an image including subpixels.

8, the second TFT ST2 is connected differently than in FIG. Referring to FIG. 8, the second pixel electrode Ep2 is connected to the k th data line DLk through the second TFT ST2. The second TFT ST2 is turned on in response to the k-th scan pulse SPk to apply the data voltage Vdata on the k-th data line DLk to the second pixel electrode Ep2. To this end, the gate electrode of the second TFT ST2 is connected to the k-th gate line GLk, the source electrode is connected to the k-th data line DLk, and the drain electrode is connected to the second pixel electrode Ep2. do.

The operation and effects of the subpixel SP according to the driving mode will be described with reference to the signal waveform and the charging waveform of FIG. 9 together with the connection configuration of FIGS. 7 and 8 as follows.

First, under the 3D mode Mode_3D, the control TFT CT continues to be turned on in response to the control voltage Vct of the first level L1.

During the T1 period during which the kth scan pulse SPk is input, the first pixel electrode Ep1 and the auxiliary subpixel of the main subpixel SP1 are turned on by turning on the first and second TFTs ST1 and ST2. The same data voltage Vdata is applied to the second pixel electrodes Ep1 and Ep2 of SP2. Since the discharge TFT DST is maintained in the turned-off state during this T1 period, the main sub-pixel SP1 is applied to the potential difference Vdata-Vcom or Vcom-Vdata between the first pixel electrode Ep1 and the common electrode Ec. The corresponding first pixel voltage Vpu is charged, and the auxiliary subpixel SP2 corresponds to the potential difference Vdata-Vcom or Vcom-Vdata between the second pixel electrode Ep2 and the common electrode Ec, and the first pixel. The second pixel voltage Vpd equal to the voltage Vpu is charged.

During the T2 period in which the k + 1th scan pulse SP (k + 1) is input, the first and second TFTs ST1 and ST2 are turned off and the discharge TFT DST is turned on to the k + 1th scan pulse ( As turned on in response to SP (k + 1), the first pixel voltage Vpu of the main subpixel SP1 is maintained at the charge level, and the second pixel voltage Vpd of the auxiliary subpixel SP2 is maintained. Is discharged to the common voltage Vcom level.

During the period T3 after T2 in the frame, the main subpixel SP1 continuously maintains the first pixel voltage Vpu at the charge level to display a 3D image as shown in FIG. The two pixel voltage Vpd is continuously maintained at the discharge level to display a black image as shown in Fig. 14A. Here, the black image serves to widen the display interval between vertically neighboring 3D images. Accordingly, the present invention can greatly improve the 3D visibility of the 3D up / down viewing angle through the black image even if a separate black stripe pattern is not formed.

On the other hand, under the 2D mode Mode_2D, the control TFT CT continues to be turned off in response to the control voltage Vct of the second level L2. As a result, the discharge TFT DST also continues to be turned off.

During the T1 period during which the kth scan pulse SPk is input, the first pixel electrode Ep1 and the auxiliary subpixel of the main subpixel SP1 are turned on by turning on the first and second TFTs ST1 and ST2. The same data voltage Vdata is applied to the second pixel electrodes Ep1 and Ep2 of SP2. During this T1 period, the main sub-pixel SP1 charges the first pixel voltage Vpu by the potential difference Vdata-Vcom or Vcom-Vdata between the first pixel electrode Ep1 and the common electrode Ec, and auxiliary. The subpixel SP2 charges the second pixel voltage Vpd equal to the first pixel voltage Vpu by the potential difference Vdata-Vcom or Vcom-Vdata between the second pixel electrode Ep2 and the common electrode Ec. do.

The main sub-pixel is turned off by turning off the first and second TFTs ST1 and ST2 during the period T2 to which the k + 1th scan pulse SP (k + 1) is input or the period T3 after T2 in the corresponding frame. SP1 continuously maintains the first pixel voltage Vpu at the charge level to display a 2D image as shown in FIG. 14B, and the auxiliary subpixel SP2 continuously maintains the second pixel voltage Vpd at the charge level. 14B, the same 2D image as the main subpixel SP1 is displayed. Here, the 2D image displayed on the auxiliary subpixel SP2 serves to increase the luminance of the 2D image. Accordingly, the present invention can greatly improve the 2D visibility by preventing the moiré phenomenon while preventing a decrease in luminance when implementing the 2D image.

On the other hand, since the control TFT CT of FIGS. 7 and 8 is continuously turned on under the 3D mode Mode_3D, the control TFT CT is likely to be degraded by gate bias stress. To compensate for this, the control TFT CT of FIGS. 7 and 8 may be replaced with a mux switch circuit MST as shown in FIGS. 10 and 11. In addition, the subpixel structures of FIGS. 10 and 11 are substantially the same as the subpixel structures of FIGS. 7 and 8, respectively.

10 and 11, the mux switch circuit MST is disposed between the first control line VL1 and the gate electrode of the discharge TFT DST in response to the k + 1 th scan pulse SP (k + 1). The voltage on the first control line VL1 is applied to the gate electrode of the discharge TFT DST by switching the current paths of. Also, the mux switch circuit MST switches the current path between the second control line VL2 and the gate electrode of the discharge TFT DST in response to any one of the k + 2th and subsequent scan pulses. The voltage on the line VL2 is applied to the gate electrode of the discharge TFT DST.

The mux switch circuit MST includes a first control TFT CT1 and a second control TFT CT2. The gate electrode of the first control TFT CT1 is connected to the k + 1th gate line GL (k + 1), the source electrode is connected to the first control line VL1, and the drain electrode is the discharge TFT DST. Is connected to the gate electrode. The gate electrode of the second control TFT CT2 is connected to the k + 2th gate line GL (k + 2), the source electrode is connected to the second control line VL2, and the drain electrode is the discharge TFT DST. Is connected to the gate electrode. The first and second control lines VL1 and VL2 and the mux switch circuit MST may be formed in the non-display area NAA of the display panel 10 in which no image is displayed. Meanwhile, "AA" shown in the drawing indicates a display area of the display panel 10 displaying an image including subpixels.

The operation and effects of the subpixel SP according to the driving mode will be described with reference to the signal waveform and the charging waveform of FIG. 12 together with the connection configuration of FIGS. 10 and 11 as follows.

First, in the 3D mode Mode_3D, the voltage of the first level Vdd is applied to the first control line VL1, and the voltage of the second level Vss is applied to the second control line VL2. The mux switch circuit MST outputs the control voltage VNg of the second level Vss during the periods T1 and T3 and outputs the control voltage VNg of the first level Vdd during the period T2.

During the T1 period during which the kth scan pulse SPk is input, the first pixel electrode Ep1 and the auxiliary subpixel of the main subpixel SP1 are turned on by turning on the first and second TFTs ST1 and ST2. The same data voltage Vdata is applied to the second pixel electrodes Ep1 and Ep2 of SP2. During this T1 period, the discharge TFT DST is maintained in the off state in response to the control voltage VNg of the second level Vss, so that the main sub-pixel SP1 is connected to the first pixel electrode Ep1 and the common electrode. The first pixel voltage Vpu corresponding to the potential difference Vdata-Vcom or Vcom-Vdata is charged, and the auxiliary subpixel SP2 has a potential difference between the second pixel electrode Ep2 and the common electrode Ec. The second pixel voltage Vpd corresponding to (Vdata-Vcom or Vcom-Vdata) and equal to the first pixel voltage Vpu is charged.

During the T2 period in which the k + 1th scan pulse SP (k + 1) is input, the first and second TFTs ST1 and ST2 are turned off, and the discharge TFT DST reaches the first level Vdd. As turned on in response to the control voltage VNg, the first pixel voltage Vpu of the main subpixel SP1 is maintained at the charge level, and the second pixel voltage Vpd of the auxiliary subpixel SP2 is common. Discharged to the voltage Vcom level.

During the period T3 after T2 in the frame, the main subpixel SP1 continuously maintains the first pixel voltage Vpu at the charge level to display a 3D image as shown in FIG. The two pixel voltage Vpd is continuously maintained at the discharge level to display a black image as shown in Fig. 14A. Here, the black image serves to widen the display interval between vertically neighboring 3D images. Accordingly, the present invention can greatly improve the 3D visibility of the 3D up / down viewing angle through the black image even if a separate black stripe pattern is not formed.

Within the T3 period, the discharge TFT DST is turned off in response to the control voltage VNg of the second level Vss. The period during which the discharge TFT DST is turned on in response to the control voltage VNg of the first level Vdd may be set to one horizontal period 1H as shown in FIG. 12, and further, one horizontal period as shown in FIG. 13. A larger j (j is a positive integer greater than 1) can be set to the horizontal period jH. In order for the sustaining width of the first level Vdd of the control voltage VNg to extend to the j horizontal period jH, the gate electrode of the second control TFT CT2 is the k + 1 + j gate line GL (k + 1 + j)).

On the other hand, under the 2D mode Mode_2D, voltages of the second level Vss are applied to the first and second control lines VL1 and VL2. The mux switch circuit MST continuously outputs the control voltage VNg of the second level Vss during the periods T1 to T3. As a result, the discharge TFT DST also continues to be turned off.

During the T1 period during which the kth scan pulse SPk is input, the first pixel electrode Ep1 and the auxiliary subpixel of the main subpixel SP1 are turned on by turning on the first and second TFTs ST1 and ST2. The same data voltage Vdata is applied to the second pixel electrodes Ep1 and Ep2 of SP2. During this T1 period, the main sub-pixel SP1 charges the first pixel voltage Vpu by the potential difference Vdata-Vcom or Vcom-Vdata between the first pixel electrode Ep1 and the common electrode Ec, and auxiliary. The subpixel SP2 charges the second pixel voltage Vpd equal to the first pixel voltage Vpu by the potential difference Vdata-Vcom or Vcom-Vdata between the second pixel electrode Ep2 and the common electrode Ec. do.

The main sub-pixel is turned off by turning off the first and second TFTs ST1 and ST2 during the period T2 to which the k + 1th scan pulse SP (k + 1) is input or the period T3 after T2 in the corresponding frame. SP1 continuously maintains the first pixel voltage Vpu at the charge level to display a 2D image as shown in FIG. 14B, and the auxiliary subpixel SP2 continuously maintains the second pixel voltage Vpd at the charge level. 14B, the same 2D image as the main subpixel SP1 is displayed. Here, the 2D image displayed on the auxiliary subpixel SP2 serves to increase the luminance of the 2D image. Accordingly, the present invention can greatly improve the 2D visibility by preventing the moiré phenomenon while preventing a decrease in luminance when implementing the 2D image.

On the other hand, referring to Figure 15, it can be seen that the vertical pitch (P2) of the auxiliary sub-pixel (SP2) is deeply related to the 3D up / down viewing angle. The 3D upper and lower viewing angles become wider as the ratio (P2 * 100) / P1 occupies the vertical pitch P2 of the auxiliary subpixel SP2 in the vertical pitch P1 of the subpixel SP. The lower ((P2 * 100) / P1), the narrower. However, the luminance of the 3D image decreases as the ratio (P2 * 100) / P1 increases, and increases as the ratio (P2 * 100) / P1 decreases. According to the experiment, when the ratio of the vertical pitch P2 of the auxiliary subpixel SP2 and the vertical pitch of the main subpixel SP1 is 1: 2, the 3D up / down viewing angle and the brightness of the 3D image are satisfactory. Close to. However, since this may vary according to the requirements of the 3D characteristic, it is preferable that the vertical pitch P2 of the auxiliary sub-pixel SP2 is designed to an appropriate size in consideration of the relationship between the 3D up / down viewing angle and the brightness of the 3D image.

16 schematically shows an operation state of the image display apparatus in the 3D mode.

Referring to FIG. 16, the left eye RGB image L is displayed on the main subpixels arranged in the odd-numbered horizontal lines of the display panel 10 in the 3D mode Mode_3D, and is disposed on the even-numbered horizontal lines. In the main subpixels, an RGB image R for the right eye is displayed. The left eye RGB image L and the right eye RGB image R are divided into polarization components by the first and second retarders formed in the pattern retarder 18 in units of horizontal lines. Then, the left eye RGB image L transmitted through the first retarder is transmitted to the left eye of the polarizing glasses 20, and the right eye RGB image R through which the second retarder is transmitted is the right eye of the polarizing glasses 20. By transmitting to the 3D image is realized.

A black image is displayed on the auxiliary subpixels of the display panel 10 in the 3D mode Mode_3D. The black image serves to widen the display interval between the vertically adjacent left eye RGB image (L) and the right eye RGB image (R).

17 schematically illustrates the operation of the image display apparatus in the 2D mode.

Referring to FIG. 17, the same RGB image is displayed on the main subpixels and the auxiliary subpixels of the display panel 10 in the 2D mode Mode_2D. The RGB image displayed on the auxiliary subpixels increases the luminance of the 2D image.

18 is a graph illustrating crosstalk values of 3D images according to 3D viewing angles. In FIG. 18, the horizontal axis represents the upper (+) and lower (-) viewing angles [deg] of the 3D image, and the vertical axis represents the 3D crosstalk values [%], respectively.

Image display device that displays 3D image with display panel that displays left eye image and right eye image alternately in horizontal line unit, and corresponding pattern retarder located at a certain distance from display panel and having different polarization characteristics in horizontal line unit In the structure of, the 3D image of good quality can be realized only when the left eye image passes only the left eye retarder and the right eye image passes only the right eye retarder as mentioned above. However, when viewing from an upper / lower viewing angle position rather than from the front, the left eye image can pass not only the left eye retarder but also the right eye retarder, and the right eye image can pass not only the right eye retarder but also the left eye retarder. C / T) is generated. The 3D crosstalk generated at this time may be represented by Equation 1 below.

Here, 'L _Black R _White ' is the luminance value in the pattern displaying black on the left eye pixel and white on the right eye pixel, and 'L _White R _Black ' is the luminance value in the pattern displaying white on the left eye pixel and black on the right eye pixel. Value. Also, 'Black' is a luminance value measured after displaying black on all pixels. In general, the viewing angle when the value of 3D crosstalk (C / T) calculated by Equation 1 is 7% or less is defined as a 3D viewing angle capable of obtaining a 3D image with good image quality. As a result, a 3D crosstalk (C / T) value of 7% becomes a threshold in determining the 3D viewing angle for obtaining a good 3D image. However, this threshold (7%) may vary depending on the model of the image display apparatus.

As can be seen from the graph of FIG. 18, in the viewing angle range VA1 having a 3D crosstalk value [%] below a predetermined critical value (eg, 7%), the user can view a 3D image having good image quality. On the other hand, in the viewing angle range VA2 where the 3D crosstalk value [%] exceeds a predetermined threshold (7%), the user cannot see a 3D image of good quality due to the superposition of the left and right eye images.

19 is a graph comparing the image side angle of view of the 3D image according to an embodiment of the present invention with the prior art. In FIG. 19, the horizontal axis represents the upper side viewing angle (deg) of the 3D image, and the vertical axis represents the crosstalk value (%) of the 3D image.

In Fig. 19, the graph 'A' shows the upper one-side viewing angle of the prior art 1 in which the left eye image and the right eye image have a display interval of 80 mu m and a black stripe is not formed in the pattern retarder by the black matrix. According to this, the upper one-side viewing angle range that satisfies the threshold (eg, 7%) of 3D crosstalk is very narrow, such as 0 ° to 4 °. Graph 'C' shows the upper one-side viewing angle of the prior art 2 in which the left eye image and the right eye image are formed by a black matrix with a black stripe pattern having a display interval of 80 μm and a width of 210 μm on the pattern retarder. According to this, the upper one-side viewing angle range that satisfies the threshold (eg, 7%) of 3D crosstalk is relatively widened to about 0 ° to 10 °. However, this prior art 2, as mentioned above, has the side effect of lowering the visibility and brightness of the 2D image due to the separate black stripe pattern for securing the viewing angle.

Compared to these, the present invention can sufficiently secure the display interval of the left eye image and the right eye image without a separate black stripe pattern when implementing the 3D image, and does not reduce the visibility and luminance of the 2D image. As described above, the upper one-side viewing angle range that satisfies the threshold (eg, 7%) of 3D crosstalk can be widened to about 0 ° to about 7 °.

As described above, the image display device according to the present invention can improve both visibility of 2D and 3D images, and can prevent a decrease in luminance when implementing 2D images.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10 display panel 11 display element
12 controller 14 panel drive circuit
16a, 16b: polarizing film 17: backlight unit
18: pattern retarder 20: polarized glasses

Claims (15)

A display panel for selectively implementing 2D and 3D images, including a plurality of red, green, and blue subpixels; And
A pattern retarder disposed in front of the display panel and dividing light from the display panel into first polarized light and second polarized light when the 3D image is implemented;
Each of the subpixels,
A main sub pixel including a first pixel electrode to which a data voltage is applied from a data line, and a common electrode opposite to the first pixel electrode and to which a common voltage from a common line is applied;
A second sub-pixel including a second pixel electrode to which the data voltage is applied, the common electrode facing the second pixel electrode, and a discharge TFT selectively connecting the second pixel electrode and the common electrode according to an implementation image; Image display device, characterized in that. The method of claim 1,
The discharge TFT,
Turning on the 3D image to electrically connect the second pixel electrode and the common electrode;
And the second pixel electrode and the common electrode are electrically turned off when the 2D image is implemented. The method of claim 2,
And the first pixel electrode is selectively connected to the data line through a first TFT, and the second pixel electrode is selectively connected to the first pixel electrode through a second TFT. The method of claim 2,
And the first pixel electrode is selectively connected to the data line through a first TFT, and the second pixel electrode is selectively connected to the data line through a second TFT. The method according to claim 3 or 4,
The main subpixel and the auxiliary subpixel are disposed at both sides with a kth (k is a positive integer) gate line therebetween;
The first and second TFTs are turned on in response to a k-th scan pulse applied to the k-th gate line;
And the discharge TFT is turned on in response to a k + 1 th scan pulse applied to a k + 1 th gate line adjacent to the k th gate line. The method of claim 5, wherein
A control TFT for selectively connecting the gate electrode of said discharge TFT and said k + 1th gate line;
And the control TFT is continuously turned on when the 3D image is implemented, and is turned off continuously when the 2D image is implemented. The method according to claim 6,
And the control TFT is disposed in a non-display area of the display panel where no image is displayed. The method according to claim 3 or 4,
The main subpixel and the auxiliary subpixel are disposed at both sides with a k-th (k is a positive integer) gate line therebetween;
The first and second TFTs are turned on in response to a k-th scan pulse applied to the k-th gate line;
And the discharge TFT is turned on in response to the control voltage of the first level applied to the first control line and turned off in response to the control voltage of the second level applied to the second control line. The method of claim 8,
When the 3D image is implemented, the control voltage of the first level is applied to the first control line and the control voltage of the second level is applied to the second control line.
And a second level control voltage is applied to the first and second control lines when the 2D image is implemented. The method of claim 9,
A mux switch circuit for selectively connecting said first and second control lines to a gate electrode of said discharge TFT;
The mux switch circuit switches the current path between the first control line and the gate electrode of the discharge TFT in response to a k + 1 th scan pulse, and responds to any one of k + 2 th and subsequent scan pulses. And a current path between the second control line and the gate electrode of the discharge TFT. The method of claim 10,
The mux switch circuit,
A first control in which a gate electrode is connected to a k + 1 gate line to which the k + 1 th scan pulse is applied, a source electrode is connected to the first control line, and a drain electrode is connected to a gate electrode of the discharge TFT. TFT; And
A gate electrode connected to a gate line to which any one of the k + 2th scan pulses is applied, a source electrode connected to the second control line, and a drain electrode connected to the gate electrode of the discharge TFT; A video display device comprising two control TFTs. The method of claim 11,
And the mux switch circuit and the first and second control lines are arranged in a non-display area of the display panel where no image is displayed. The method of claim 1,
The ratio of the vertical pitch of the sub-pixels to the total vertical pitch of the sub-pixels is determined according to the viewing angle of the 3D image and the brightness of the 3D image. The method of claim 13,
And a ratio of the vertical pitch of the auxiliary subpixels to the vertical pitch of the main subpixels is 1: 2. The method of claim 1,
And the first polarization and the second polarization have polarization characteristics perpendicular to each other.

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