KR20110101387A - Liquid Crystal Display and Manufacturing Method Thereof - Google Patents

Abstract

The liquid crystal display according to the exemplary embodiment of the present invention may include a first substrate, a second substrate facing the first substrate, an electric field generating electrode formed on at least one of the first substrate and the second substrate, and the first substrate. And a liquid crystal layer interposed between and the second substrate and having a liquid crystal and a reactive mesogen. Here, the reactive mesogen induces alignment of liquid crystal molecules by ultraviolet irradiation, and the liquid crystal display includes an ultraviolet blocking layer on at least one of the first substrate and the second substrate.

Description

Liquid crystal display device and its manufacturing method {LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method for manufacturing the liquid crystal display device, and more particularly, to a liquid crystal display panel and a method for manufacturing a liquid crystal display panel used for manufacturing a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which electrodes are formed and a liquid crystal layer interposed therebetween to rearrange the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. The display device controls the amount of light transmitted.

Among liquid crystal displays, vertically aligned mode liquid crystal displays have been developed in which liquid crystal molecules are arranged such that their major axes are perpendicular to the display panel without an electric field applied thereto.

The patterned vertical alignment mode (PVA) mode, which is a type of the vertical alignment method, may improve the viewing angle of the liquid crystal display by forming liquid crystal domains by arranging liquid crystal molecules in different directions using a patterned transparent electrode. In order to solve the problem of having a low aperture ratio due to the patterning of the transparent electrode in the liquid crystal display of the PVA mode, recently, the pixel electrode of the display substrate is formed in a micro slit pattern, and the common electrode of the opposite substrate is formed of a plate. A liquid crystal display device having a structure is used.

The problem to be solved by the present invention is to introduce a UV blocking layer that protects the organic film from ultraviolet rays when the liquid crystal layer has a pretilt, and the liquid crystal layer has a pretilt in a liquid crystal display device using a micro slit pattern. The present invention provides a liquid crystal display device and a method of manufacturing the same, which have no abnormality in display quality.

The liquid crystal display according to the embodiment for realizing the object of the present invention is formed on at least one of a first substrate, a second substrate facing the first substrate, the first substrate and the second substrate. A pair of electric field generating electrodes, and a liquid crystal layer interposed between the first substrate and the second substrate, the liquid crystal layer comprising a liquid crystal and a reactive mesogen, and blocking ultraviolet rays on one of the first and second substrates. A layer, wherein the UV blocking layer comprises a UV absorber, the UV absorber being an organic material comprising a chromophore.

The reactive mesogen may be converted into an oriented polymer by an ultraviolet irradiation process.

The UV blocking layer may be positioned on one of the first substrate and the second substrate, instead of a substrate to which ultraviolet rays are applied in the ultraviolet irradiation process.

The ultraviolet blocking layer may be located under the electric field generating electrode.

The UV blocking layer may be positioned on the electric field generating electrode.

The ultraviolet absorber may absorb light of 400 nm or less.

The chromophore may include one of the compounds represented by Chemical Formulas 1 and 2.

[Formula 1]

[Formula 2]

The UV blocking layer may have a thickness of 0.05um or more.

In another embodiment, a method of manufacturing a liquid crystal display includes forming a gate line including a gate electrode on a first substrate, forming a gate insulating layer on the gate line, and including a source electrode on the gate insulating layer. Forming a data line and a drain electrode facing the source electrode, forming a color filter on the gate insulating layer, forming a planarization layer on the color filter, and forming an ultraviolet blocking layer on the planarization layer. Forming a common electrode on the second substrate, introducing a mixture of liquid crystal and reactive mesogen between the first substrate and the second substrate, wherein the UV blocking layer comprises an ultraviolet absorber, Is an organic material comprising a chromophore.

The method may further include forming a pixel electrode on the UV blocking layer of the first substrate.

The method may further include forming a pixel electrode under the UV blocking layer of the first substrate.

Applying a voltage to the pixel electrode and the common electrode, and photopolymerizing the reactive mesogen by irradiating light to the liquid crystal layer in a state where voltage is applied to the pixel electrode and the common electrode. Can be.

Turning off the voltages on the pixel electrode and the common electrode, and photopolymerizing the reactive mesogen by irradiating light onto the liquid crystal layer without applying voltage to the pixel electrode and the common electrode. can do.

The ultraviolet absorber may absorb light of 400 nm or less.

The chromophore may include one of the compounds represented by Chemical Formulas 1 and 2.

[Formula 1]

[Formula 2]

According to an exemplary embodiment of the present invention, in the liquid crystal display device, the liquid crystal layer has a pretilt even by irradiation of ultraviolet rays, and in this case, a UV blocking layer is introduced to protect the organic layer from damage caused by ultraviolet rays. The degradation of quality can be controlled.

1 is an equivalent circuit diagram of a pixel of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention.
3 is a cross-sectional view taken along the line II-II of FIG. 2.
4 is a plan view illustrating a pixel electrode in a liquid crystal display according to an exemplary embodiment of the present invention.
5 is a schematic diagram illustrating a method of forming a pretilt of a liquid crystal by a reactive mesogen according to an embodiment of the present invention.
6 is a cross-sectional view of another embodiment of the present invention.
7 is a graph showing the ultraviolet blocking effect of the ultraviolet blocking layer of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

1 is an equivalent circuit diagram of a pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment includes a thin film transistor array panel 100 and a common electrode panel 200 facing each other, and a liquid crystal layer 3 interposed therebetween. .

The liquid crystal display includes a signal line including a plurality of gate lines GL, a plurality of pairs of data lines DLa and DLb, and a plurality of storage electrode lines SL, and a plurality of pixels PX connected thereto.

Each pixel PX includes a pair of subpixels PXa and PXb, and the subpixels PXa and PXb include switching elements Qa and Qb, liquid crystal capacitors Clca and Clcb, and storage capacitors. (Csta, Cstb).

The switching elements Qa and Qb are three-terminal elements such as thin film transistors provided in the thin film transistor array panel 100, the control terminals of which are connected to the gate line GL, and the input terminals of the data lines DLa and DLb. ) And the output terminals are connected to the liquid crystal capacitors Clca and Clcb and the storage capacitors Csta and Cstb.

The liquid crystal capacitors Clca and Clcb are formed using the subpixel electrodes 191a and 191b and the common electrode 270 as two terminals, and the liquid crystal layer 3 between the two terminals as a dielectric.

In the storage capacitors Csta and Cstb, which serve as an auxiliary role of the liquid crystal capacitors Clca and Clcb, the storage electrode line SL and the subpixel electrodes 191a and 191b of the thin film transistor array panel 100 are interposed between the insulators. Overlapping and a predetermined voltage such as the common voltage Vcom is applied to the storage electrode line SL.

The voltages charged in the two liquid crystal capacitors Clca and Clcb are set to be slightly different from each other. For example, the data voltage applied to the liquid crystal capacitor Clca is set to be always lower or higher than the data voltage applied to the liquid crystal capacitor Clcb. When the voltages of the two liquid crystal capacitors Clca and Clcb are appropriately adjusted, the image viewed from the side may be closer to the image viewed from the front, thereby improving side visibility of the liquid crystal display.

A liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2 to 5.

FIG. 2 is a layout view of a liquid crystal display according to an exemplary embodiment, and FIG. 3 is a cross-sectional view taken along the line II-II of FIG. 2. 4 is a plan view illustrating a basic pixel electrode in a liquid crystal display according to an exemplary embodiment of the present invention. 5 is a schematic diagram showing a method of forming the pretilt of the liquid crystal by the alignment aid according to an embodiment of the present invention.

2 and 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a thin film transistor array panel 100 and a common electrode panel 200 facing each other and between the two display panels 100 and 200. The liquid crystal layer 3 is included.

First, the thin film transistor array panel 100 will be described.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110. The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of protruding first and second gate electrodes 124a and 124b. In addition, a protrusion 125 protruding between the gate electrodes 124a and 124b is included. The storage electrode line 131 extends substantially in parallel with the gate line 121 and includes a plurality of storage electrodes 135 extending therefrom. The shape and arrangement of the storage electrode line 131 and the storage electrode 135 may be modified in various forms.

A gate insulating layer 140 is formed on the gate line 121 and the storage electrode line 131, and a plurality of semiconductors 154a and 154b made of amorphous or crystalline silicon are formed on the gate insulating layer 140.

A plurality of pairs of ohmic contacts 163a, 163b, 165a, and 165b are formed on the semiconductors 154a and 154b, respectively. The ohmic contacts 163a, 163b, 165a, and 165b are formed of silicide or n-type impurities. It can be made of materials such as highly doped n + hydrogenated amorphous silicon.

A plurality of pairs of data lines 171a and 171b and a plurality of pairs of first and second drain electrodes 175a and 175b are formed on the ohmic contacts 163a, 163b, 165a and 165b and the gate insulating layer 140.

The data lines 171a and 171b transmit data signals and mainly extend in the vertical direction to cross the gate lines 121 and the storage electrode lines 131. The data lines 171a and 171b include first and second source electrodes 173a and 173b extending toward the first and second gate electrodes 124a and 124b and bent in a U-shape, and the first and second source electrodes. 173a and 173b face the first and second drain electrodes 175a and 175b around the first and second gate electrodes 124a and 124b, respectively.

The first and second drain electrodes 175a and 175b extend upward from one end partially surrounded by the first and second source electrodes 173a and 173b, respectively, and the other end may have a large area for connection with another layer. have. However, the shape and arrangement of the data lines 171a and 171b including the first and second drain electrodes 175a and 175b may be modified in various forms.

The first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b are formed of the first and second semiconductors 154a and 154b. Together with the first and second thin film transistors (TFTs), the channels of the first and second thin film transistors are the first and second source electrodes 173a and 173b and the first and second thin film transistors. It is formed in the first and second semiconductors 154a and 154b between the drain electrodes 175a and 175b.

The semiconductors 154a and 154b have portions exposed between the source electrodes 173a and 173b and the drain electrodes 175a and 175b and not covered by the data lines 171a and 171b and the drain electrodes 175a and 175b.

A passivation layer 180 made of silicon nitride or silicon oxide is formed on the data lines 171a and 171b, the drain electrodes 175a and 175b, and the exposed semiconductors 154a and 154b.

The color filter 230 is formed on the passivation layer 180.

The planarization film 188 is formed on the color filter to planarize the thin film transistor array panel 100. The planarization film 188 is made of an organic material.

An ultraviolet blocking layer 185 is formed on the planarization film 188.

The UV blocking layer is composed of an organic material including an ultraviolet absorber such as a chromophore. Examples of the chromophore include the following chemical formulas.

[Formula 1]

[Formula 2]

First, Formula 1 may absorb wavelengths of 310 nm or more and 400 nm or less, centering on 365 nm, and Formula 2 may absorb wavelengths of 310 nm or more and 400 nm or less, centering on 388 nm.

The material included in the ultraviolet absorbents other than the formulas (1) and (2) may be one of materials having a chromophore absorbing ultraviolet rays having a wavelength of 400 nm or less. Can be one.

A plurality of contact holes 185a and 185b exposing the first and second drain electrodes 175a and 175b are formed in the planarization film 188, the color filter 230, the UV blocking layer 185, and the passivation layer 180. have.

A plurality of pixel electrodes 191 are formed on the UV blocking layer 185, and each pixel electrode 191 includes first and second subpixel electrodes 191a and 191b separated from each other.

The area occupied by the second subpixel electrode 191b in the entire pixel electrode 191 may be larger than the area occupied by the first subpixel electrode 191a, wherein the second subpixel electrode 191b is the first subpixel. It is formed to be 1.0 to 2.5 times larger than the area of the electrode 191a. However, the shape and area ratio of the first and second subpixel electrodes 191a and 191b may be variously modified.

The second subpixel electrode 191b includes a pair of branches 195 extending along the data lines 171a and 171b. The pair of branches 195 are positioned between the first subpixel electrode 191a and the data lines 171a and 171b and are connected to each other at the lower end of the first subpixel electrode 191a and overlap the gate line 121. do. One of the two branches is extended and is physically and electrically connected to the second drain electrode 175b through the contact hole 185b. The first subpixel electrode 191a is connected to the first drain electrode 175a through the contact hole 185a.

The first and second subpixel electrodes 191a and 191b receive a data voltage from the first and second drain electrodes 175a and 175b.

A light blocking member 220 is formed on a portion of the planarization film 188 corresponding to the gate line 121, the data lines 171a and 171b, and the first and second thin film transistors.

Next, the common electrode display panel 200 will be described.

In the common electrode display panel 200, the common electrode 270 is formed on the front surface of the transparent insulating substrate 210.

The liquid crystal layer 3 is positioned between the common electrode panel 200 and the thin film transistor array panel 100.

Although not shown, a spacer may be formed between the common electrode panel and the thin film transistor array panel to maintain the gap of the liquid crystal layer 3.

Next, the direction in which the liquid crystal operates in the pixel electrode 191 will be described in detail with reference to FIG. 4.

As shown in FIG. 4, the overall shape of the pixel electrode 191 is quadrangular and includes a cross stem portion including a horizontal stem portion 193 and a vertical stem portion 192 orthogonal thereto. In addition, the pixel electrode 191 may include the first subregion Da, the second subregion Db, the third subregion Dc, and the fourth subsection by the horizontal stem portion 193 and the vertical stem portion 192. The sub-regions Da, Db, Dc, and Dd are divided into regions Dd, and include a plurality of first to fourth minute branches 194a, 194b, 194c, and 194d.

The direction in which the liquid crystal 310 is inclined is determined by the fine branches 194a, 194b, 194c, and 194d of the pixel electrode 191, and the liquid crystal 310 is in the longitudinal direction of the fine branches 194a, 194b, 194c, and 194d. Tilt in a direction parallel to Since one pixel electrode 191 includes four subregions Da, Db, Dc, and Dd having different length directions of the minute branches 194a, 194b, 194c, and 194d, the direction in which the liquid crystal 310 is inclined is Four domains having approximately four directions and different alignment directions of the liquid crystal 310 are formed in the liquid crystal layer 3. As described above, the viewing angle of the liquid crystal display may be improved by varying the direction in which the liquid crystal is inclined.

Although not illustrated, the widths of the minute branches 194a, 194b, 194c, and 194d may be wider as they are closer to the horizontal stem 193 or the vertical stem 192.

5 is a schematic diagram illustrating a method of forming a pretilt of a liquid crystal by a reactive mesogen according to an embodiment of the present invention.

First, the thin film transistor array panel 100 and the common electrode panel 200 are manufactured, respectively.

The thin film transistor array panel 100 is manufactured by the following method.

A plurality of thin films are stacked and patterned on the substrate 110 to form the gate line 121 including the gate electrodes 124a and 124b, the gate insulating layer 140, the semiconductors 154a and 154b, and the source electrodes 173a and 173b. The data lines 171a and 171b, the drain electrodes 175a and 175b, and the lower passivation layer 180 are sequentially formed.

Subsequently, the color filter 230 and the planarization film 188 are formed on the lower passivation layer 180.

A UV blocking layer 185 is formed on the planarization film 188, and a conductive layer such as ITO or IZO is stacked and patterned to form a vertical stem 192 and a horizontal stem 193 as shown in FIGS. 4 and 5. ) And a plurality of fine branch portions 194a, 194b, 194c, and 194d extending from them.

Subsequently, an alignment film (not shown) is coated on the pixel electrode 191.

The common electrode panel 200 is manufactured by the following method.

The common electrode 270 is formed on the substrate 210. Subsequently, an alignment layer 21 is coated on the common electrode 270.

Next, the liquid crystal layer 3 is formed by injecting a mixture of the liquid crystal 310 and the reactive mesogen 50 between the thin film transistor array panel 100 and the common electrode panel 200 manufactured by the above method. . The liquid crystal layer 3 may be formed by dropping a mixture of the liquid crystal 310 and the reactive mesogen 50 on the thin film transistor array panel 100 or the common electrode display panel 200.

The alignment polymer 50a formed by the polymerization of the reactive mesogen 50 serves to control pre-tilt, which is the initial alignment direction of the liquid crystal. The reactive mesogen 50 has a shape similar to that of the liquid crystal, and has a core group forming a central axis and a terminal group connected thereto, similarly to the liquid crystal. Reactive mesogen 50 according to the embodiment of the present invention has a mesogen (mesogen) as the center portion and a photo-polymerizable group as the end group.

Next, referring to FIGS. 5A and 4, the pretilt forming process will be described. A voltage is applied to the pixel electrode 191 and the common electrode 270. By applying a voltage, the liquid crystal 310 and the reactive mesogen 50 are inclined in a direction parallel to the length direction of the minute branches 194a to 194d of the pixel electrode 191. The liquid crystal 310 positioned near the alignment film (not shown) maintains the vertical alignment by the alignment film chains 11a and 21a.

As such, the light 1 is irradiated in a state where a voltage is applied between the pixel electrode 191 and the common electrode 270. The light 1 may be one having a wavelength capable of polymerizing the reactive mesogen 50, ultraviolet light, or the like, and a high pressure mercury lamp may be used. As a result, the reactive mesogens 50 collected at adjacent positions are photopolymerized to form the alignment polymer 50a. The alignment polymer 50a may control the pretilt of the liquid crystal 310.

The voltage applied to the pixel electrode 191 and the common electrode 270 may be a DC voltage, and the magnitude thereof may be 5V to 20V, and the energy of the irradiated light 1 may be 3J / cm ² to 10J / cm ^2. have.

Subsequently, as shown in FIG. 5B, the voltage between the pixel electrode 191 and the common electrode 270 is turned off.

Subsequently, in the state where the voltage is turned off to the pixel electrode 191 and the common electrode 270, light may be irradiated to the liquid crystal layer 3 to increase the polymerization rate.

After the process of irradiating light, the liquid crystal layer 3 may include the alignment polymer 50a polymerized by light and the unpolymerized reactive mesogen 50 together, and the unpolymerized reactive mesogen 50 ) Shows deterioration of display quality such as afterimage when the LCD is operated for a long time, and the unpolymerized reactive mesogen is irradiated with energy of 20J / cm ² or more at the step shown in FIG. Minimize the ratio of 50.

At this time, organic materials such as the color filter 230 and the planarization film 188 included in the liquid crystal display are also exposed to ultraviolet rays to decompose chemical bonds of the organic materials, or some of the components of the organic materials are leaked to the liquid crystal layer. Outgassing may occur. This causes defects in which some of the afterimages of the liquid crystal display, the organic film, and the like are not filled (a defective Active Unfilled Area (AUA)), which causes a decrease in display quality.

In the liquid crystal display according to the exemplary embodiment of the present invention, the ultraviolet blocking layer 185 serves to block ultraviolet rays having a short wavelength of 400 nm or less so that the organic film in the substrate is not decomposed, thereby maintaining display quality.

6 is a cross-sectional view of another embodiment of the present invention.

Since the structure of the liquid crystal display according to the present exemplary embodiment is substantially the same as the structure of the liquid crystal display shown in FIGS. 2 to 5, other parts will be described in detail. That is, since the common electrode display panel, the operation principle, and the pretilt forming process are the same, only the thin film transistor array panel will be described.

The thin film transistor array panel 100 of FIG. 6 will be described.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110. The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of protruding first and second gate electrodes 124a and 124b. In addition, a protrusion 125 protruding between the gate electrodes 124a and 124b is included. The storage electrode line 131 extends substantially in parallel with the gate line 121 and includes a plurality of storage electrodes 135 extending therefrom. The shape and arrangement of the storage electrode line 131 and the storage electrode 135 may be modified in various forms.

A gate insulating layer 140 is formed on the gate line 121 and the storage electrode line 131, and a plurality of semiconductors 154a and 154b made of amorphous or crystalline silicon are formed on the gate insulating layer 140.

A plurality of pairs of ohmic contacts 163a, 163b, 165a, and 165b are formed on the semiconductors 154a and 154b, respectively. The ohmic contacts 163a, 163b, 165a, and 165b are formed of silicide or n-type impurities. It can be made of materials such as highly doped n + hydrogenated amorphous silicon.

A plurality of pairs of data lines 171a and 171b and a plurality of pairs of first and second drain electrodes 175a and 175b are formed on the ohmic contacts 163a, 163b, 165a and 165b and the gate insulating layer 140.

The data lines 171a and 171b transmit data signals and mainly extend in the vertical direction to cross the gate lines 121 and the storage electrode lines 131. The data lines 171a and 171b include first and second source electrodes 173a and 173b extending toward the first and second gate electrodes 124a and 124b and bent in a U-shape, and the first and second source electrodes. 173a and 173b face the first and second drain electrodes 175a and 175b around the first and second gate electrodes 124a and 124b, respectively.

The first and second drain electrodes 175a and 175b extend upward from one end partially surrounded by the first and second source electrodes 173a and 173b, respectively, and the other end may have a large area for connection with another layer. have. However, the shape and arrangement of the data lines 171a and 171b including the first and second drain electrodes 175a and 175b may be modified in various forms.

The first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b are formed of the first and second semiconductors 154a and 154b. Together with the first and second thin film transistors (TFTs), the channels of the first and second thin film transistors are the first and second source electrodes 173a and 173b and the first and second thin film transistors. It is formed in the first and second semiconductors 154a and 154b between the drain electrodes 175a and 175b.

The semiconductors 154a and 154b have portions exposed between the source electrodes 173a and 173b and the drain electrodes 175a and 175b and not covered by the data lines 171a and 171b and the drain electrodes 175a and 175b.

A passivation layer 180 made of silicon nitride or silicon oxide is formed on the data lines 171a and 171b, the drain electrodes 175a and 175b, and the exposed semiconductors 154a and 154b.

The color filter 230 is formed on the passivation layer 180.

The planarization film 188 is formed on the color filter to planarize the thin film transistor array panel 100. The planarization film 188 is made of an organic material.

A plurality of contact holes 185a and 185b exposing the first and second drain electrodes 175a and 175b are formed in the planarization film 188, the color filter 230, and the passivation layer 180.

A plurality of pixel electrodes 191 are formed on the planarization film 188, and each pixel electrode 191 includes first and second subpixel electrodes 191a and 191b separated from each other.

The first and second subpixel electrodes 191a and 191b receive a data voltage from the first and second drain electrodes 175a and 175b.

An ultraviolet blocking layer 185 is formed on the first and second subpixel electrodes 191a and 191b and the planarization layer 188.

The UV blocking layer is composed of an organic material including an ultraviolet absorber such as a chromophore. Examples of the chromophore include the following chemical formulas.

[Formula 1]

[Formula 2]

First, Formula 1 may absorb wavelengths of 310 nm or more and 400 nm or less, centering on 365 nm, and Formula 2 may absorb wavelengths of 310 nm or more and 400 nm or less, centering on 388 nm.

The material included in the ultraviolet absorbents other than the formulas (1) and (2) may be one of materials having a chromophore absorbing ultraviolet rays having a wavelength of 400 nm or less. Can be one.

A light blocking member 220 is formed on a portion of the UV blocking layer 185 corresponding to the gate line 121, the data lines 171a and 171b, and the first and second thin film transistors.

7 is a graph showing the ultraviolet blocking effect of the ultraviolet blocking layer 185 according to the embodiment of the present invention.

In order to measure the UV blocking effect, the UV blocking layer was formed on a substrate (wafer) reflecting light, and then the UV absorbing effect was measured by measuring the reflectance. That is, the higher the UV absorbance, the lower the reflectance is displayed on the graph, and the closer the value of the reflectance is to 0, the higher the blocking effect of the UV blocking layer.

The x-axis of the graph represents the thickness of the sunscreen and is in um.

The axis on the left side of the y-axis of the graph represents a value of S as a normalized value for the reflectance, wherein a value used as a reference for the normalization is a reflectance measurement value when there is no UV blocking layer. In the graph, the axis on the right side of the y axis represents the reflectance R value.

FIG. 7A illustrates a case where the material of Chemical Formula 1 is stacked, and reflectance of the UV blocking layer having a refractive index of 1.25 is 0.42% when the thickness is 0.1295 um. According to the graph of (a) of FIG. 7, it can be seen that the UV absorbing layer exhibits sufficient ultraviolet absorption at a thickness of 0.1 μm or more and 0.15 μm or less.

Figure 7 (b) is a case of laminating the material of the formula (2), the reflectivity measurement results for the UV blocking layer having a refractive index of 1.80, showing a minimum S value of 0.56% when the thickness is 0.0698 um. According to the graph of (b) of FIG. 7, it can be seen that the UV absorbing layer exhibits sufficient ultraviolet absorption at a thickness of 0.06 μm or more and 0.095 μm or less.

As such, the blocking effect of the UV blocking layer may be controlled by controlling the film thickness and adjusting the content of the UV absorber.

In the above-described embodiment, the UV blocking layer 185 is described as being positioned on the thin film transistor array panel 100. However, in the case of the liquid crystal display in which the color filter 230 is positioned on the common electrode panel 200, light is emitted from the lower panel 100. The UV blocking layer 185 may be disposed on the common electrode panel 200 to protect the organic material in the common electrode panel 200.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

3: liquid crystal layer 50: reactive mesogen
100: thin film transistor display panel 200: common electrode display panel
121: gate line 171: data line
185: UV blocking layer 188: planarization film
191: pixel electrode 230: color filter
270 common electrode

Claims (18)

First substrate,
A second substrate facing the first substrate,
A pair of field generating electrodes formed on at least one of the first substrate and the second substrate, and
A liquid crystal layer interposed between the first substrate and the second substrate and including a liquid crystal and a reactive mesogen,
Including a UV blocking layer on one of the first substrate and the second substrate,
The UV blocking layer includes a UV absorber,
The ultraviolet absorber is an organic material containing a chromophore
Liquid crystal display. In claim 1,
The reactive mesogen is converted into an alignment polymer by an ultraviolet irradiation process. In claim 2,
The ultraviolet blocking layer is a liquid crystal display device of the first substrate and the second substrate is located on a substrate other than the substrate to which ultraviolet light is applied in the ultraviolet irradiation process. 4. The method of claim 3,
The UV blocking layer is a liquid crystal display device disposed under the electric field generating electrode. In claim 4,
The UV absorber absorbs light of 400 nm or less In paragraph 5
The chromophore is a liquid crystal display comprising one of the compounds represented by Chemical Formulas 1 to 2
[Formula 1]

(2)

In claim 4,
The UV blocking layer has a thickness of 0.05um or more. 4. The method of claim 3,
The UV blocking layer is a liquid crystal display disposed above the field generating electrode. 9. The method of claim 8,
The UV absorber absorbs light of 400 nm or less In claim 9,
The chromophore is a liquid crystal display comprising one of the compounds represented by Chemical Formulas 1 to 2
[Formula 1]

(2)

9. The method of claim 8,
The UV blocking layer has a thickness of 0.05um or more. Forming a gate line including a gate electrode on the first substrate,
Forming a gate insulating film on the gate line;
Forming a data line including a source electrode and a drain electrode facing the source electrode on the gate insulating layer;
Forming a color filter on the gate insulating layer;
Forming a planarization layer on the color filter;
Forming an ultraviolet blocking layer on the planarization layer,
Forming a common electrode on the second substrate,
Introducing a mixture of liquid crystal and reactive mesogen between the first substrate and the second substrate
Including;
The UV blocking layer includes a UV absorber,
The ultraviolet absorber is an organic material containing a chromophore. In claim 12,
And forming a pixel electrode on the UV blocking layer of the first substrate. In claim 12,
And forming a pixel electrode under the UV blocking layer of the first substrate. In claim 12,
Applying a voltage to the pixel electrode and the common electrode, and
Photopolymerizing the reactive mesogen by irradiating light to the liquid crystal layer in a state where voltage is applied to the pixel electrode and the common electrode.
Method of manufacturing a liquid crystal display device further comprising. The method of claim 15,
Turning off a voltage to the pixel electrode and the common electrode, and
Photopolymerizing the reactive mesogen by irradiating light onto the liquid crystal layer without applying a voltage to the pixel electrode and the common electrode
Method of manufacturing a liquid crystal display device further comprising. In claim 12,
The ultraviolet absorber manufacturing method of the liquid crystal display device that absorbs light of 400nm or less In claim 12,
The chromophore is a liquid crystal display comprising one of the compounds represented by Formula 1 to 2.
[Formula 1]

(2)

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