KR20110094989A - Nonvolatile memory device, programming method thereof and memory system including the same - Google Patents

Abstract

PURPOSE: A nonvolatile memory device, a programming method thereof and a memory system including the same are provided to reduce leakage between a channel voltage and a bit line voltage by applying a positive voltage to a selected bit line in programming. CONSTITUTION: In a nonvolatile memory device, a programming method thereof and a memory system including the same, a first voltage is applied to a selection bit line(S110). A second voltage is applied to a non-selection bit line(S120). A third voltage is applied to the string selection line corresponding to a selected memory cell. A fourth voltage is applied to the string selection line corresponding to an unselected memory cell. A program operating voltage is applied to the word lines(S130). The first to third voltage is a positive voltage.

Description

Nonvolatile Memory Device, Its Program Method, and Memory System Containing It {NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME}

The present invention relates to a semiconductor memory, and more particularly to a nonvolatile memory device, a program method thereof, and a memory system including the same.

A semiconductor memory device is a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge, Germanium), gallium arsenide (GaAs, gallium arsenide), or indium phospide (InP). to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

Volatile memory devices lose their stored data when their power supplies are interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory device, a PRAM ), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory devices are largely divided into NOR type and NAND type.

It is an object of the present invention to provide a nonvolatile memory device having improved reliability, a program method thereof, and a memory system including the same.

A program method of a nonvolatile memory device according to an embodiment of the present invention, which includes groups of memory cells sequentially provided in a vertical direction on a substrate, comprising: applying a first voltage to a select bit line; Applying a second voltage to the unselected bit line; Applying a third voltage to the string select line corresponding to the selected memory cells; Applying a fourth voltage to the string select line corresponding to the unselected memory cells; And applying a program operating voltage to word lines, wherein the first to third voltages are positive voltages.

In an embodiment, the first voltage has a level lower than the second voltage, the third voltage has a level higher than the fourth voltage, and the fourth voltage has a level lower than the first voltage.

In an embodiment, the second positive voltage is a power supply voltage.

In an embodiment, each group of memory cells constitutes a NAND string, and applying a program operating voltage to word lines includes: a plurality of NAND strings sharing the selection bit line and a plurality of sharing the non-selection bit line. And applying a program operating voltage to the NAND strings of the.

A nonvolatile memory device according to an embodiment of the present invention may include a memory cell array including groups of memory cells sequentially provided in a vertical direction on a substrate; And read and write circuitry configured to select bit lines coupled to the memory cell array, wherein during a program operation, the read and write circuitry is configured to apply a positive voltage to bit lines corresponding to the memory cells to be programmed. It is composed.

In an embodiment, each group of memory cells constitutes NAND strings, each of the bit lines is connected to a plurality of NAND strings, and during a program operation, a program operation is performed on word lines connected to the plurality of NAND strings. And a decoder configured to deliver a voltage.

In an embodiment, the read and write circuit includes page buffers corresponding to the bit lines, each page buffer comprising: a latch configured to receive and store write data during a program operation; And a bias circuit configured to set up a corresponding bit line to the positive voltage when the write data stored in the latch is program data.

In an embodiment, the bias circuit includes first and second transistors, a gate node of the first transistor is coupled to the latch, a first node of the transistor is provided with a reference voltage, and a first voltage of the transistor Two nodes are connected to a gate node of the second transistor, a first node of the second transistor is supplied with a power supply voltage, and a second node of the second transistor is connected to the corresponding bit line.

In example embodiments, the bias circuit may further include a third transistor coupled between the second node of the second transistor and the corresponding bit line, wherein the third transistor is configured to respond to a program operation signal. Electrically connect the second node and the corresponding bit line.

In an embodiment, a memory system may include a nonvolatile memory device; And a controller configured to control the nonvolatile memory device, wherein the nonvolatile memory device includes a memory cell array including groups of memory cells sequentially provided in a vertical direction on a substrate; And read and write circuitry configured to select bit lines coupled to the memory cell array, wherein during a program operation, the read and write circuitry is configured to apply a positive voltage to bit lines corresponding to the memory cells to be programmed. It is composed.

According to the present invention, a positive voltage is applied to the select bit line during the program operation. Therefore, leakage due to the difference between the channel voltage and the bit line voltage is reduced, and the reliability of the nonvolatile memory device is improved.

1 is a block diagram illustrating a nonvolatile memory device according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a memory cell array of FIG. 1.
FIG. 3 is a perspective view illustrating a first embodiment of one of the memory blocks of FIG. 2.
4 is a cross-sectional view taken along line of the memory block of FIG. 3.
5 is a cross-sectional view illustrating the transistor structure of FIG. 4.
6 is a circuit diagram illustrating an equivalent circuit of the memory block described with reference to FIGS. 3 to 5.
7 and 8 are tables illustrating a first embodiment of a program voltage condition of the memory block of FIG. 6.
9 is a flowchart illustrating a program method of the nonvolatile memory device of FIG. 1.
10 is a timing diagram illustrating a voltage change according to the program method of FIG. 9.
11 and 12 are tables showing program voltage conditions based on the voltage change of FIG. 10, respectively.
FIG. 13 is a block diagram illustrating a read and write circuit of FIG. 1.
FIG. 14 is a circuit diagram illustrating a first embodiment of one of the page buffers of FIG. 13.
FIG. 15 is a circuit diagram illustrating a second embodiment of one of the page buffers of FIG. 13.
FIG. 16 is a circuit diagram illustrating a third embodiment of one of the page buffers of FIG. 13.
FIG. 17 is a circuit diagram illustrating a fourth embodiment of one of the page buffers of FIG. 13.
FIG. 18 is a circuit diagram illustrating a first application example of an equivalent circuit of the memory block described with reference to FIGS. 3 to 5.
19 is a circuit diagram illustrating a second application example of an equivalent circuit of the memory block described with reference to FIGS. 3 to 5.
20 is a circuit diagram illustrating a third application example of an equivalent circuit of the memory block described with reference to FIGS. 3 to 5.
FIG. 21 is a circuit diagram illustrating a fourth application example of an equivalent circuit of the memory block described with reference to FIGS. 3 to 5.
FIG. 22 is a circuit diagram illustrating a fifth application example of an equivalent circuit of the memory block described with reference to FIGS. 3 to 5.
FIG. 23 is a circuit diagram illustrating a sixth application example of an equivalent circuit of the memory block described with reference to FIGS. 3 to 5.
24 is a block diagram illustrating another embodiment of the memory block of FIG. 3.
FIG. 25 is a perspective view illustrating a second embodiment of the memory block of FIG. 2.
FIG. 26 is a cross-sectional view taken along lines of the memory block of FIG. 25.
FIG. 27 is a perspective view illustrating a third embodiment of the memory block of FIG. 2.
FIG. 28 is a cross-sectional view taken along lines of the memory block of FIG. 27.
FIG. 29 is a perspective view illustrating a fourth embodiment of the memory block of FIG. 2.
30 is a cross-sectional view taken along line of the memory block of FIG. 29.
FIG. 31 is a block diagram illustrating a memory system including the nonvolatile memory device of FIG. 1.
32 is a block diagram illustrating an application example of the memory system of FIG. 31.
33 is a block diagram illustrating a computing system 3000 including the memory system described with reference to FIG. 32.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . Identical components will be referred to using the same reference numerals. Similar components will be referred to using similar reference numerals.

1 is a block diagram illustrating a nonvolatile memory device 100 according to a first embodiment of the present invention. Referring to FIG. 1, a nonvolatile memory device 100 according to an exemplary embodiment may include a memory cell array 110, an address decoder 120, a read and write circuit 130, a data input / output circuit 140, and Control logic 150.

The memory cell array 110 is connected to the address decoder 120 through word lines WL and is connected to the read and write circuit 130 through the bit lines BL. The memory cell array 110 includes a plurality of memory cells. In exemplary embodiments, the memory cell array 110 may be configured to store one or more bits per cell.

The address decoder 120 is connected to the memory cell array 110 through word lines WL. The address decoder 120 is configured to operate in response to the control of the control logic 150. The address decoder 120 receives an address ADDR from the outside.

The address decoder 120 decodes a row address of the received address ADDR to select corresponding word lines among the plurality of word lines WL. In addition, the address decoder 120 decodes a column address among the received addresses ADDR and transfers the decoded column address to the read and write circuit 130. In exemplary embodiments, the address decoder 120 includes well-known components, such as a row decoder, a column decoder, an address buffer, and the like.

The read and write circuit 130 is connected to the memory cell array 110 through bit lines BL and to the data input / output circuit 140 through data lines DL. The read and write circuit 130 operates under the control of the control logic 150. Read and write circuit 130 is configured to receive the decoded column address from address decoder 120. Using the decoded column address, the read and write circuit 130 selects the bit lines BL.

In exemplary embodiments, the read and write circuit 130 receives data from the data input / output circuit 140 and writes the received data to the memory cell array 110. The read and write circuit 130 reads data from the memory cell array 110 and transfers the read data to the data input / output circuit 140. The read and write circuit 130 reads data from the first storage area of the memory cell array 110 and writes the read data to the second storage area of the memory cell array 110. For example, read and write circuit 230 is configured to perform a copy-back operation.

Illustratively, read and write circuit 130 includes well known components, such as a page buffer (or page register), column selection circuitry, and the like. As another example, read and write circuit 130 includes well known components, such as sense amplifiers, write drivers, column select circuits, and the like.

The data input / output circuit 140 is connected to the read and write circuit 130 through the data lines DL. The data input / output circuit 140 operates under the control of the control logic 150. The data input / output circuit 140 is configured to exchange data DATA with an external device. The data input / output circuit 140 is configured to transfer data DATA transmitted from the outside to the read and write circuit 130 through the data lines DL. The data input / output circuit 140 is configured to output data DATA transferred from the read and write circuits through the data lines DL to the outside. In exemplary embodiments, the data input / output circuit 140 includes well-known components, such as a data buffer.

The control logic 150 is connected to the address decoder 120, the read and write circuit 130, and the data input / output circuit 140. The control logic 150 is configured to control overall operations of the flash memory device 100. The control logic 150 operates in response to a control signal CTRL transmitted from the outside.

2 is a block diagram illustrating the memory cell array 110 of FIG. 1. Referring to FIG. 2, the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKh. Each memory block BLK has a three-dimensional structure (or a vertical structure). For example, each memory block BLK includes structures extending along first to third directions. For example, each memory block BLK may include a plurality of NAND strings NS that extend in the second direction. For example, a plurality of NAND strings NS may be provided along the first and third directions.

Each NAND string NS is connected to a bit line BL, a string select line SSL, a ground select line GSL, word lines WL, and a common source line CSL. That is, each memory block includes a plurality of bit lines BL and a plurality of string select lines SSL. The ground selection lines GSL, the word lines WL, and the common source lines CSL may be connected to each other. The memory blocks BLK1 to BLKh are described in more detail with reference to FIG. 3.

3 is a perspective view illustrating a first embodiment of one of the memory blocks BLK1 to BLKh of FIG. 2. 4 is a cross-sectional view taken along line II ′ of the memory block BLKi of FIG. 3. 3 and 4, the memory block BLKi includes structures extending along the first to third directions.

First, the substrate 111 is provided. In exemplary embodiments, the substrate 111 may include a silicon material doped with a first type impurity. For example, the substrate 111 may include a silicon material doped with p-type impurities. For example, the substrate 111 may be a p type well (eg, a pocket p well). For example, the substrate 111 may further include an n-type well surrounding the p-type well. Hereinafter, it is assumed that the substrate 111 is p type silicon. However, the substrate 111 is not limited to p-type silicon.

On the substrate 111, a plurality of doped regions 311 ˜ 314 extending along the first direction are provided. For example, the plurality of doped regions 311 to 314 may have a second type different from that of the substrate 111. For example, the plurality of doped regions 311 to 314 may have an n-type. Hereinafter, it is assumed that the first to fourth doped regions 311 to 314 are n-types. However, the first to fourth doped regions 311 to 314 are not limited to being n-types.

In an area on the substrate 111 corresponding between the first and second doped regions 311 and 312, a plurality of insulating materials 112 extending along the first direction are sequentially provided along the second direction. . For example, the plurality of insulating materials 112 and the substrate 111 may be spaced apart by a predetermined distance along the second direction. For example, the plurality of insulating materials 112 may be provided spaced apart from each other by a predetermined distance along the second direction. In exemplary embodiments, the insulating materials 112 may include an insulating material such as silicon oxide.

In a region on the substrate 111 corresponding between the first and second doped regions 311 and 312, a plurality of sequentially disposed along the first direction and penetrating the insulating materials 112 along the second direction. Pillars 113 are provided. In exemplary embodiments, each of the pillars 113 may be connected to the substrate 111 through the insulating materials 112.

For example, each pillar 113 may be composed of a plurality of materials. For example, the surface layer 114 of each pillar 113 may comprise a silicon material doped with a first type. For example, the surface layer 114 of each pillar 113 may comprise a silicon material doped with the same type as the substrate 111. Hereinafter, it is assumed that the surface layer 114 of each pillar 113 includes p-type silicon. However, the surface layer 114 of each pillar 113 is not limited to including p-type silicon.

The inner layer 115 of each pillar 113 is made of an insulating material. For example, the inner layer 115 of each pillar 113 may include an insulating material such as silicon oxide.

In the region between the first and second doped regions 311 and 312, an insulating film 116 is provided along the exposed surfaces of the insulating materials 112, the pillars 113, and the substrate 111. In exemplary embodiments, the thickness of the insulating layer 116 may be less than 1/2 of the distance between the insulating materials 112. That is, between the insulating film 116 provided on the lower surface of the first insulating material among the insulating materials 112, and the insulating film 116 provided on the upper surface of the second insulating material under the first insulating material, the insulating materials ( A region may be provided in which materials other than 112 and the insulating film 116 may be disposed.

In the region between the first and second doped regions 311 and 312, conductive materials 211-291 are provided on the exposed surface of the insulating film 116. For example, a conductive material 211 extending along the first direction is provided between the insulating material 112 adjacent to the substrate 111 and the substrate 111. More specifically, a conductive material 211 extending in the first direction is provided between the insulating film 116 of the lower surface of the insulating material 112 adjacent to the substrate 111 and the substrate 111.

A conductive material extending along the first direction is provided between the insulating film 116 of the upper surface of the specific insulating material among the insulating materials 112 and the insulating film 116 of the lower surface of the insulating material disposed on the specific insulating material. . In exemplary embodiments, a plurality of conductive materials 221 to 281 extending in the first direction are provided between the insulating materials 112. In addition, a conductive material 291 extending along the first direction is provided in a region on the insulating materials 112. In exemplary embodiments, the conductive materials 211 to 291 extending in the first direction may be a metal material. For example, the conductive materials 211 to 291 extending in the first direction may be conductive materials such as polysilicon.

In the region between the second and third doped regions 312 and 313, the same structure as the structure on the first and second doped regions 311 and 312 will be provided. For example, in the region between the second and third doped regions 312 and 313, a plurality of insulating materials 112 extending in the first direction, sequentially disposed along the first direction, and arranged in the third direction. Accordingly, a plurality of pillars 113 penetrating through the plurality of insulating materials 112, a plurality of insulating materials 112, and an insulating layer 116 provided on the exposed surface of the plurality of pillars 113. A plurality of conductive materials 212-292 extending along one direction are provided.

In the region between the third and fourth doped regions 313 and 314, the same structure as the structure on the first and second doped regions 311 and 312 will be provided. For example, in the region between the third and fourth doped regions 312 and 313, a plurality of insulating materials 112 extending in the first direction, sequentially disposed along the first direction, and arranged in the third direction. Accordingly, a plurality of pillars 113 penetrating through the plurality of insulating materials 112, a plurality of insulating materials 112, and an insulating layer 116 provided on the exposed surface of the plurality of pillars 113. A plurality of conductive materials 213 to 293 extending along one direction are provided.

Drains 320 are provided on the plurality of pillars 113, respectively. In exemplary embodiments, the drains 320 may be silicon materials doped with a second type. For example, the drains 320 may be silicon materials doped with n type. In the following, it is assumed that the drains 320 include n-type silicon. However, the drains 320 are not limited to containing n-type silicon. In exemplary embodiments, the width of each drain 320 may be larger than the width of the corresponding pillar 113. For example, each drain 320 may be provided in the form of a pad on the top surface of the corresponding pillar 113.

On the drains 320, conductive materials 331 ˜ 333 extending in the third direction are provided. The conductive materials 331 ˜ 333 are sequentially disposed along the first direction. Each of the conductive materials 331 to 333 is connected to the drains 320 of the corresponding region. In exemplary embodiments, the drains 320 and the conductive material 333 extending in the third direction may be connected through contact plugs, respectively. In exemplary embodiments, the conductive materials 331 ˜ 333 extending in the third direction may be metal materials. For example, the conductive materials 331 ˜ 333 extending in the third direction may be conductive materials such as polysilicon.

3 and 4, each pillar 113 may be adjacent to an adjacent region of the insulating layer 116 and an adjacent region of the plurality of conductor lines 211 to 291, 212 to 292, and 213 to 293 extending along the first direction. Together to form a string. For example, each pillar 113 may include a NAND string together with an adjacent region of the insulating layer 116 and an adjacent region among the plurality of conductor lines 211 to 291, 212 to 292, and 213 to 293 extending along the first direction. (NS) is formed. The NAND string NS includes a plurality of transistor structures TS. Transistor structure TS is described in more detail with reference to FIG. 5.

FIG. 5 is a cross-sectional view illustrating the transistor structure TS of FIG. 4. 3 to 5, the insulating layer 116 includes first to third sub insulating layers 117, 118, and 119.

The p-type silicon 114 of the pillar 113 will act as a body. The first sub insulating layer 117 adjacent to the pillar 113 may act as a tunneling insulating layer. For example, the first sub insulating layer 117 adjacent to the pillar 113 may include a thermal oxide layer.

The second sub insulating layer 118 may operate as a charge storage layer. For example, the second sub insulating film 118 will act as a charge trapping layer. For example, the second sub insulating film 118 may include a nitride film or a metal oxide film (for example, an aluminum oxide film, a hafnium oxide film, or the like).

The third sub insulating layer 119 adjacent to the conductive material 233 may act as a blocking insulating layer. In exemplary embodiments, the third sub insulating layer 119 adjacent to the conductive material 233 extending in the first direction may be formed in a single layer or multiple layers. The third sub insulating film 119 may be a high dielectric film (eg, aluminum oxide film, hafnium oxide film, etc.) having a higher dielectric constant than the first and second sub insulating films 117 and 118.

The conductive material 233 will act as a gate (or control gate). That is, the gate (or control gate) 233, the blocking insulating layer 119, the charge storage layer 118, the tunneling insulating layer 117, and the body 114 may form a transistor (or a memory cell transistor structure). In exemplary embodiments, the first to third sub insulating layers 117 to 119 may constitute an oxide-nitride-oxide (ONO). Hereinafter, the p-type silicon 114 of the pillar 113 will be referred to as a body in the second direction.

The memory block BLKi includes a plurality of pillars 113. That is, the memory block BLKi includes a plurality of NAND strings NS. In more detail, the memory block BLKi includes a plurality of NAND strings NS extended in a second direction (or a direction perpendicular to the substrate).

Each NAND string NS includes a plurality of transistor structures TS disposed along a second direction. At least one of the plurality of transistor structures TS of each NAND string NS operates as a string select transistor SST. At least one of the plurality of transistor structures TS of each NAND strip NS operates as a ground select transistor GST.

The gates (or control gates) correspond to the conductive materials 211 to 291, 212 to 292, and 213 to 293 extending in the first direction. That is, the gates (or control gates) extend in the first direction to form word lines and at least two select lines (eg, at least one string select line SSL and at least one ground select line). GSL)).

The conductive materials 331 ˜ 333 extending in the third direction are connected to one end of the NAND strings NS. In exemplary embodiments, the conductive materials 331 ˜ 333 extending in the third direction operate as bit lines BL. That is, in one memory block BLKi, a plurality of NAND strings are connected to one bit line BL.

Second type doped regions 311 to 314 extending in the first direction are provided at the other end of the NAND strings. The second type doped regions 311 ˜ 314 extending in the first direction operate as common source lines CSL.

In summary, the memory block BLKi includes a plurality of NAND strings extending in a direction perpendicular to the substrate 111 (a second direction), and the plurality of NAND strings NS are disposed on one bit line BL. It acts as a connected NAND flash memory block (eg, charge trapping type).

3 to 5, it is described that the conductor lines 211 to 291, 212 to 292, and 213 to 293 extending in the first direction are provided in nine layers. However, the conductor lines 211 to 291, 212 to 292, and 213 to 293 extending in the first direction are not limited to those provided in nine layers. For example, the conductor lines extending in the first direction may be provided in eight layers, sixteen layers, or a plurality of layers. That is, in one NAND string, there may be eight, sixteen, or a plurality of transistors.

3 to 5, three NAND strings NS are connected to one bit line BL. However, the three NAND strings NS are not limited to one bit line BL. For example, m NAND strings NS may be connected to one bit line BL in the memory block BLKi. At this time, the number of the conductive materials 211 to 291, 212 to 292, and 213 to 293 and the common source line that extend in the first direction by the number of NAND strings NS connected to one bit line BL. The number of fields 311-314 will also be adjusted.

3 to 5, three NAND strings NS are connected to one conductive material extending in the first direction. However, the three NAND strings NS are not limited to one conductive material extending in the first direction. For example, n NAND strings NS may be connected to one conductive material extending in the first direction. In this case, the number of bit lines 331 to 333 may also be adjusted by the number of NAND strings NS connected to one conductive material extending in the first direction.

FIG. 6 is a circuit diagram illustrating an equivalent circuit of the memory block BLKi described with reference to FIGS. 3 to 5. 3 to 6, NAND strings NS11 to NS31 are provided between the first bit line BL1 and the common source line CSL. The first bit line BL1 may correspond to the conductive material 331 extending in the third direction. NAND strings NS12, NS22, and NS32 are provided between the second bit line BL2 and the common source line CSL. The second bit line BL2 may correspond to the conductive material 332 extending in the third direction. NAND strings NS13, NS23, NS33 are provided between the third bit line BL3 and the common source line CSL. The third bit line BL3 may correspond to the conductive material 333 extending in the third direction.

The string select transistor SST of each NAND string NS is connected to the corresponding bit line BL. The ground select transistor GST of each NAND string NS is connected to the common source line CSL. Memory cells MC are provided between the string select transistor SST and the ground select transistor GST of each NAND string NS.

Hereinafter, NAND strings NS are defined in row and column units. The NAND strings NS commonly connected to one bit line form one column. For example, the NAND strings NS11 to NS31 connected to the first bit line BL1 may correspond to the first column. The NAND strings NS12 to NS32 connected to the second bit line BL2 may correspond to the second column. The NAND strings NS13 to NS33 connected to the third bit line BL3 may correspond to the third column.

NAND strings NS connected to one string select line SSL form one row. For example, the NAND strings NS11 to NS13 connected to the first string select line SSL1 form a first row. The NAND strings NS21 to NS23 connected to the second string select line SSL2 form a second row. The NAND strings NS31 to NS33 connected to the third string select line SSL3 form a third row.

In each NAND string NS, a height is defined. For example, in each NAND string NS, the height of the memory cell MC1 adjacent to the ground select transistor GST is one. In each NAND string NS, the height of the memory cell increases as the NAND string NS is adjacent to the string select transistor SST. In each NAND string NS, the height of the memory cell MC7 adjacent to the string select transistor SST is seven.

NAND strings NS of the same row share the string select line SSL. The NAND strings NS of different rows are connected to different string select lines SSL1, SSL2, SSL3, respectively. Memory cells of the same height of the NAND strings NS in the same row share the word line WL. At the same height, the word lines WL of the NAND strings NS of different rows are commonly connected. For example, the word lines WL may be commonly connected in a layer provided with the conductive materials 211 to 291 212 to 292 and 213 to 293 extending in the first direction. In exemplary embodiments, the conductive materials 211 to 291 212 to 292 and 213 to 293 extending in the first direction may be connected to the upper layer through the contact. The conductive materials 211 to 291 212 to 292 and 213 to 293 extending in the first direction from the upper layer may be connected in common.

NAND strings NS in the same row share the ground select line GSL. The NAND strings NS of different rows share the ground select line GSL. That is, the NAND strings NS11 to NS13, NS21 to NS23, and NS31 to NS33 are commonly connected to the ground select line GSL.

The common source line CSL is commonly connected to the NAND strings NS. For example, in the active region on the substrate 111, the first to fourth doped regions 311 to 314 may be connected. For example, the first to fourth doped regions 311 to 314 may be connected to the upper layer through the contact. The first to fourth doped regions 311 to 314 may be commonly connected to the upper layer.

As illustrated in FIG. 6, word lines WL having the same depth are commonly connected. Therefore, when the specific word line WL is selected, all the NAND strings NS connected to the specific word line WL will be selected. The NAND strings NS of different rows are connected to different string select lines SSL. Therefore, by selecting the string selection lines SSL1 to SSL3, the NAND strings NS of the non-selected row among the NAND strings NS connected to the same word line WL are transferred from the bit lines BL1 to BL3. Can be separated. That is, by selecting the string selection lines SSL1 to SSL3, the rows of the NAND strings NS may be selected. The NAND strings NS of the selection row may be selected in column units by selecting the bit lines BL1 to BL3.

In exemplary embodiments, one of the string selection lines SSL1 to SSL2 may be selected during a program and a read operation. That is, the program and read operations may be performed in units of rows of NAND strings NS11 to NS13, NS21 to NS23, and NS31 to NS33.

In exemplary embodiments, during a program and read operation, a select voltage may be applied to a select word line of a select row, and a select voltage may be applied to unselect word lines. For example, the selection voltage may be a program voltage Vpgm or a read voltage Vr. For example, the unselected voltage may be a pass voltage Vpass or an unselected read voltage Vread. That is, the program and read operations may be performed in units of word lines of selected rows of the NAND strings NS11 to NS13, NS21 to NS23, and NS31 to NS33.

In example embodiments, a first voltage may be applied to a bit line corresponding to a memory cell to be programmed. In addition, a second voltage may be applied to the bit line corresponding to the memory cell to be program inhibited. Hereinafter, the bit line corresponding to the memory cell to be programmed will be referred to as a selection bit line. The bit line corresponding to the memory cell to be program inhibited will be referred to as an unselected bit line.

Hereinafter, it is assumed that a first row of NAND strings NS11 to NS13, NS21 to NS23, and NS31 to NS33 is selected during a program operation. In addition, it is assumed that the second bit line BL2 is selected. Further, it is assumed that the first and third bit lines BL1 and BL3 are unselected.

7 and 8 are tables illustrating a first embodiment of a program voltage condition of the memory block of FIG. 6. For example, voltage conditions of the NAND strings NS11 to NS13 of the first row are illustrated in FIG. 7. In addition, voltage conditions of the NAND strings NS21 to NS23 of the second row are illustrated in FIG. 8. For example, the voltage conditions of the NAND strings NS31 to NS33 of the third row may be the same as the voltage conditions of the NAND strings NS21 to NS23 of the second row. Therefore, the voltage condition of the NAND strings NS31 to NS33 in the third row is omitted.

6 and 7, the ground voltage Vss is applied to the select bit line BL2. The power supply voltage Vcc is applied to the unselected bit lines BL1 and BL3.

The string select line voltage VSSL is applied to the string select line SSL1 of the select row. For example, the string select line voltage VSSL may have a level higher than the threshold voltages of the string select transistors SST of the NAND strings NS11 to NS13.

The program voltage Vpgm and the pass voltage Vpass are applied to the word lines WL1 to WL7. For example, the program voltage Vpgm may be applied after the pass voltage Vpass is applied to the selected word line. The pass voltage Vpass may be applied to the unselected word line. For example, the program voltage Vpgm and the pass voltage Vpass may constitute a program operating voltage applied to the word lines WL1 to WL7.

The ground voltage Vss is applied to the ground select line GSL. Since the ground voltage Vss is applied to the magazine selection line GSL, the memory cells MC1 to MC7 of the NAND strings NS11 to NS13 are electrically separated from the common source line CSL.

When the pass voltage Vpass is applied to the word lines WL1 to WL7, a channel may be formed in the memory cells MC1 to MC7 of the NAND strings NS11 to NS13. Since the string select transistors SST of the NAND strings NS11 to NS13 are turned on, the ground voltages set up in the bit lines BL1 to BL3 are the memory cells MC1 of the NAND strings NS11 to NS13. To each of channels of ˜MC7). For example, the ground voltage Vss may be provided to a channel of the memory cells MC1 to MC7 of the NAND string NS12. The power supply voltage Vcc may be provided to the channels of the memory cells MC1 to MC7 of the NAND strings NS11 and NS13, respectively.

Hereinafter, a channel of the memory cells MC1 to MC7 of the NAND string (eg, NS12) of the selection row connected to the selection bit line (eg, BL2) will be referred to as a selection channel. Channels of the memory cells MC1 to MC7 of the NAND strings (eg, NS11 and NS13) of the selected row connected to the unselected bit lines (eg, BL1 and BL3) are referred to as first unselected channels. do.

In example embodiments, a pass voltage Vpass may be applied to the word lines WL1 ˜ WL7 during a program operation. The pass voltage Vpass will be a high voltage. When the pass voltage Vpass is applied to the word lines WL1 to WL7, the voltage of the select channel will be maintained at the ground voltage.

When the pass voltage Vpass is applied to the word lines WL1 ˜ WL7, the voltages of the first non-selected channels will rise due to the coupling effect due to the pass voltage Vpass. For example, the voltages of the first unselected channels will rise from the voltage delivered from the unselected bit lines BL1 and BL3. When the voltages of the first non-selected channels reach a certain level (eg, the difference between the threshold voltage of the string select line voltage VSSL and the string select transistor SST), the string select corresponding to the first non-selected channels is reached. Transistors SST will be turned off. That is, the first unselected channels will be floated. Thereafter, by the influence of the coupling due to the pass voltage Vpass, the voltages of the first unselected channels will rise further.

After the pass voltage Vpass is applied to the word lines WL1 to WL7, the program voltage Vpgm may be applied to the selected word line. In exemplary embodiments, the program voltage Vpgm may be a high voltage. The program voltage Vpgm will have a level higher than the pass voltage Vpass.

When the program voltage Vpass is applied to the select word line, the voltage of the select channel will maintain the ground voltage Vss. That is, the program voltage Vpgm is applied to the control gate of the selected memory cell and the ground voltage Vss is applied to the channel of the selected memory cell. Due to the voltage difference between the program voltage Vpgm and the ground voltage Vss, the selected memory cell air Fowler-Nordheim tunneling will occur. By F-N tunneling, the selected memory cell will be programmed.

When the program voltage Vpgm is applied to the select word line, the voltages of the first unselected channels will rise due to the coupling effect due to the program voltage Vpgm. For example, the voltages of the first unselected channels will reach the first boosting voltage Vboost1. The difference between the program voltage Vpgm and the first boosting voltage Vboost1 will not cause F-N tunneling. That is, in the selection row, the memory cells corresponding to the unselected bit lines BL1 and BL3 will be program inhibited.

6 to 8, the NAND strings NS21 to NS23 of the non-selected row share the NAND strings NS11 to NS13 and the bit lines BL1 to BL3 of the selected row, respectively. Therefore, the bit line voltages provided to the NAND strings NS21 to NS23 of the non-selected row are the same as the bit line voltages provided to the NAND strings NS11 to NS13 of the selected row.

The ground voltage Vss is applied to the string select line SSL2 of the unselected row.

The NAND strings NS11 to NS13 of the selected row and the NAND strings NS21 to NS23 of the non-selected row share the word lines WL1 to WL7. Therefore, the voltages of the word lines WL1 to WL7 of the unselected row are the same as the voltages of the word lines WL1 to WL7 of the selected row.

The NAND strings NS11 to NS13 of the selected row and the NAND strings NS21 to NS23 of the non-selected row share the ground select line GSL. Therefore, the voltage of the ground select line GSL of the unselected row is equal to the voltage of the ground select line GSL of the select row.

Since the ground voltage Vss is applied to the string select line SSL of the unselected row, the NAND strings NS21 to NS23 of the unselected row are electrically separated from the bit lines BL1 to BL3. Since the ground voltage Vss is applied to the ground select line GSL of the unselected row, the NAND strings NS21 to NS23 of the unselected row are electrically separated from the common source line CSL. That is, the memory cells MC1 to MC7 of the NAND strings NS21 to NS23 of the non-selected row are floated.

In the program operation, the pass voltage Vpass may be applied to the word lines WL1 ˜ WL7. When the pass voltage Vpass is applied to the word lines WL1 to WL7, channels (hereinafter, referred to as second unselected channels) are respectively applied to the NAND strings NS21 to NS23 of the unselected row. Will be formed. Since the memory cells MC1 to MC7 of the NAND strings NS21 to NS23 of the non-selected row are floated, the second non-selected channels are also in a floating state. Thus, by the effect of coupling due to the pass voltage Vpass, the voltage of the second unselected channels will rise.

After the pass voltage Vpass is applied, the program voltage Vpgm will be applied to the select word line. By the effect of the coupling due to the program voltage Vpgm, the voltages of the second unselected channels will rise. For example, the voltages of the second unselected channels will rise to the second boosting voltage Vboost2. The difference between the program voltage Vpgm and the second boosting voltage Vboost2 will not cause F-N tunneling. Therefore, the program will be prohibited in the NAND strings NS21 to NS23 of the unselected row.

The program voltage Vpgm and the pass voltage Vpass are high voltages. Therefore, the second boosting voltage Vboost2 generated by the influence of the coupling due to the program voltage Vpgm and the pass voltage Vpass will also be a high voltage. In the NAND strings NS21 to NS23 of the non-selected row, an electric field is formed by the second boosting voltage Vboost2 across the string select transistor SST.

As the magnitude of the electric field formed across the string select transistors SST of each NAND string increases, the probability that leakage occurs from the channel of the NAND string through the string select transistor SST to the bit line increases. When leakage occurs from the channel of the NAND string to the bit line through the string select transistor SST, the channel voltage of the NAND string decreases. When the channel voltage of the NAND string decreases, memory cells of the program inhibited NAND string may be soft programmed. That is, when the magnitude of the electric field formed at both ends of the string select transistor SST of each NAND string increases, the possibility of program disturbance increases.

In exemplary embodiments, a power supply voltage Vcc is applied to the first bit line BL1. The channel voltage of the NAND string NS21 connected to the first bit line BL1 is the second boosting voltage Vboost2. Therefore, an electric field corresponding to the difference between the second boosting voltage Vboost2 and the power supply voltage Vcc will be formed at both ends of the string select transistor SST of the NAND string NS21. Similarly, an electric field corresponding to the difference between the second boosting voltage Vboost2 and the power supply voltage Vcc will be formed at both ends of the string select transistor SST of the NAND string NS23.

The ground voltage Vss is applied to the second bit line BL2. The channel voltage of the NAND string NS22 connected to the second bit line BL2 is the second boosting voltage Vboost2. Therefore, an electric field corresponding to the difference between the second boosting voltage Vboost2 and the ground voltage Vss will be formed at both ends of the string select transistor SST of the NAND string NS22. Hereinafter, an electric field formed at both ends of the string select transistor SST of each NAND string will be referred to as a string electric field.

That is, the string electric field of the NAND string (e.g., NS22) of the unselected row connected to the select bit line (e.g. BL2) is unselected connected to the unselected bit line (e.g. BL1 or BL3). Is greater than the string electric field of the NAND string of the row (e.g., NS21 or NS23). Accordingly, the probability that program disturb occurs in the NAND string NS22 of the non-selected row connected to the selection bit line BL2 is such that the NAND string NS21 or NS23 of the non-selected row connected to the unselected bit line BL1 or BL3. Is greater than the probability of program disturb.

In order to prevent such a problem, the nonvolatile memory device according to the embodiment of the present invention is configured to apply the first positive voltage to the selected bit line and the second positive voltage to the unselected bit line.

9 is a flowchart illustrating a program method of the nonvolatile memory device 100 of FIG. 1. 1 and 9, in step S110, a first positive voltage is applied to a selected bit line. For example, the first bit line voltage VBL1 may be applied to the selected bit line. For example, the first bit line voltage VBL1 may have a level lower than the power supply voltage Vcc. For example, the read and write circuit 130 will set up the first bit line voltage VBL1 at select bit lines.

In step S120, the second positive voltage is applied to the unselected bit line. For example, the second bit line voltage VBL2 may be applied to the unselected bit line. For example, the second bit line voltage VBL2 may be a power supply voltage Vcc. For example, the read and write circuit 130 will set up the second bit line voltage VBL2 on unselected bit lines.

In operation S130, program operating voltages are applied to the word lines. For example, the program voltage Vpgm may be applied to the select word lines, and the pass voltage Vpass may be applied to the unselected word lines. For example, the address decoder 120 may deliver program operating voltages to word lines.

10 is a timing diagram illustrating a voltage change according to the program method of FIG. 9. 9 and 10, bit line setup is performed at a first time t1 to a second time t2. For example, bit line setup will be performed similarly to steps S110 and S120. For example, the first bit line voltage VBL1 may be applied to the selected bit line among the bit lines BL, and the second bit line voltage VBL2 may be applied to the unselected bit line.

In exemplary embodiments, the first bit line voltage VBL1 may have a level lower than the power supply voltage Vcc. For example, the first bit line voltage VBL1 may have a level in the range of 0.1V to 0.5V. For example, the first bit line voltage VBL1 may be 0.3V. For example, the second bit line voltage VBL2 may be a power supply voltage Vcc.

At a second time t2 to a third time t3, channel boosting is performed. For example, the string select line voltage VSSL is applied to the string select line SSL corresponding to the NAND strings of the select row. The string select line voltage VSSL may have a level higher than the threshold voltage of the string select transistor SST. For example, the string select line voltage VSSL may be the power supply voltage Vcc. That is, the NAND strings of the selection row are electrically connected to the bit lines BL.

The ground voltage Vss is applied to the string select line SSL corresponding to the NAND strings of the unselected row. That is, the NAND strings of the non-selected row are electrically separated from the bit lines BL.

A pass voltage Vpass is applied to the selected word line and the unselected word lines. That is, channels are formed in memory cells of the NAND strings, respectively.

The program is performed at the third time t3. For example, a program voltage Vpgm is applied to the select word line.

In the bit line setup period, the channel boosting period, and the program period, the ground voltage Vss is applied to the ground select line GSL. That is, the NAND strings are electrically separated from the common source line CSL.

In FIG. 10, the string select line voltage VSSL and the pass voltage Vpass have been described as being applied at the second time. However, the string select line voltage VSSL and the pass voltage Vpass are not limited to being applied at the second time. For example, after the string select line voltage VSSL is applied to the string select line SSL corresponding to the NAND strings of the selected row, the pass voltage Vpass is applied to the selected word line and the unselected word lines. Can be.

11 and 12 are tables showing program voltage conditions based on the voltage change of FIG. 10, respectively. For example, as described with reference to FIG. 7, voltage conditions of the NAND strings NS11 to NS13 of the selection row are illustrated in FIG. 11. As described with reference to FIG. 8, the voltage conditions of the NAND strings NS21 to NS23 of the non-selected row are shown in FIG. 12.

10 and 11, the first bit line voltage VBL1 is applied to the select bit line BL2, and the second bit line voltage VBL2 is applied to the unselected bit lines BL1 and BL3, respectively. do. The string select line voltage VSSL is applied to the first string select line SSL1. The pass voltage Vpass and the program voltage Vpgm are applied to the word lines WL. The ground voltage Vss is applied to the ground select line GSL.

As described with reference to FIG. 7, the channels of the NAND strings NS11 and NS13 corresponding to the unselected bit lines BL1 and BL3 will be boosted with the first boosting voltage Vboost1. Therefore, the NAND strings NS11 and NS13 corresponding to the unselected bit lines BL1 and BL3 will be program inhibited.

The channel voltage of the NAND string NS22 corresponding to the selection bit line BL2 is the first bit line voltage VBL1. The first bit line voltage VBL1 has a level lower than the power supply voltage Vcc. Therefore, the program will be performed in the NAND string NS12 corresponding to the selection bit line BL2 by the voltage difference between the program voltage Vpgm and the first bit line voltage VBL1.

10 to 12, the first bit line voltage VBL1 is applied to the select bit line BL2, and the second bit line voltage VBL2 is applied to the unselected bit lines BL1 and BL3, respectively. do. The ground voltage Vss is applied to the second string select line SSL2. The pass voltage Vpass and the program voltage Vpgm are applied to the word lines WL. The ground voltage Vss is applied to the ground select line GSL.

As described with reference to FIG. 8, the channel voltages of the NAND strings NS21 to NS23 in the unselected row will rise to the second boosting voltage Vboost2. The first bit line voltage VBL1 is applied to the selection bit line BL2. Therefore, the string electric field of the NAND string NS22 of the unselected row connected to the selection bit line BL2 is formed based on the difference between the second boosting voltage Vboost2 and the first bit line voltage VBL1. Compared with the voltage conditions described with reference to FIGS. 7 and 8, the string electric field of the NAND string NS22 of the unselected row connected to the select bit line BL2 is reduced. Therefore, program disturb is prevented and the reliability of the nonvolatile memory device 100 is improved.

FIG. 13 is a block diagram illustrating the read and write circuit 130 of FIG. 1. Referring to FIG. 13, the read and write circuit 130 includes a plurality of page buffers 131 to 13m. The page buffers 131 to 13m are connected between the bit lines BL1 to BLm and the data lines DL1 to DLm, respectively.

In a write operation, each page buffer is configured to receive write data from a corresponding data line. Each page buffer stores received write data. Based on the stored write data, each page buffer is configured to set up a corresponding bit line. For example, when the received write data is program data, each page buffer will set up the corresponding bit line to the first bit line voltage VBL1. For example, when the received write data is program inhibited data, each page buffer will set up the corresponding bit line to the second bit line voltage VBL2.

FIG. 14 is a circuit diagram illustrating a first embodiment 400 of one of the page buffers 131 to 13m of FIG. 13. Referring to FIG. 14, the page buffer 400 includes a latch 410, a selection circuit 420, a loading circuit 430, a sensing circuit 440, a Y gate circuit 450, and a bias circuit 460. do.

The latch 410 is connected to the bit line selection circuit 420, the sensing circuit 440, the Y gate circuit 450, and the bias circuit 460. In exemplary embodiments, the first node N1 of the latch 410 is connected to the selection circuit 420, the Y gate circuit 450, and the bias circuit 460. The second node N2 of the latch 410 is connected to the sensing circuit 440 and the bias circuit 460. In a write operation, latch 410 is configured to store write data. In a read operation, latch 410 is configured to store the read data.

The selection circuit 420 is connected to the bit line BL, the latch 410, the loading circuit 430, the sensing circuit 440, the Y gate circuit 450, and the bias circuit 460. For example, in a write operation, the selection circuit 420 is configured to electrically connect the latch 410 and the bit line BL in response to the selection signal BLSLT. For example, the selection circuit 420 includes a switch. For example, the selection circuit 420 includes a transistor. The selection circuit 420 operates in response to the selection signal BLSLT.

The loading circuit 430 is connected to the bit line BL, the selection circuit 420, and the sensing circuit 440. For example, in a read operation, the loading circuit 430 is configured to charge the sensing node SO to the power supply voltage Vcc. For example, the loading circuit 430 includes a switch. For example, the loading circuit 430 includes a transistor. The loading circuit 430 is configured to provide the power supply voltage Vcc to the bit line BL in response to the precharge signal PRE.

The sensing circuit 440 is connected to the bit line BL, the latch 410, the selection circuit 420, the loading circuit 430, and the bias circuit 460. For example, in a read operation, the sensing circuit 440 is configured to transmit the voltage level of the sensing node SO to the latch 410 in response to the latch signal LAT. For example, the latch signal LAT will be activated during a read operation. In this case, the first transistor T1 may operate in response to the voltage level of the sensing node SO. That is, when the voltage level of the sensing node SO is high, the sensing circuit 440 transfers the ground voltage Vss to the latch 410. When the voltage level of the sensing node SO is low, the sensing circuit 440 will not transfer the ground voltage Vss to the latch 410. That is, during the read operation, the state of the latch 410 will change in response to the voltage level of the sensing node SO.

For example, sensing circuit 440 includes at least two switches. For example, the sensing circuit 440 includes first and second transistors T1 and T2. The first transistor T1 is connected to the bit line BL, the latch 410, the selection circuit 420, the loading circuit 430, and the bias circuit 460. The second transistor T2 is configured to provide the ground voltage Vss to the first transistor T1 in response to the latch signal T2.

The Y gate circuit 450 is connected to the latch 410, the selection circuit 420, and the bias circuit 460. For example, in read and write operations, the Y gate circuit 450 is configured to connect the data line DL and the latch 410. For example, in a read operation, the Y gate circuit 450 is configured to transfer read data stored in the latch 410 to the data line DL. For example, in a write operation, the Y gate circuit 450 is configured to deliver data received via the data line DL to the latch 410.

For example, the Y gate circuit 450 includes a switch. For example, the Y gate circuit 450 includes a transistor. For example, the Y gate circuit 450 is configured to operate in response to the column address YA.

The bias circuit 460 is connected to the latch 410, the selection circuit 420, the loading circuit 430, the sensing circuit 440, and the Y gate circuit 450. For example, in a program operation, the bias circuit 410 is configured to provide the bit line BL according to the write data stored in the latch 410. For example, the bias circuit 410 is configured to provide the first bit line voltage VBL1 to the bit line BL. For example, when the write data stored in the latch 410 is program data, the bias circuit 460 is configured to provide the first bit line voltage VBL1 to the bit line BL.

For example, bias circuit 460 includes at least three switches. For example, the bias circuit 460 includes third to fifth transistors T3 to T5. The third transistor T3 is configured to transfer the reference voltage Vref to the fourth transistor T4 in response to the voltage level of the second node N2 of the latch 410. The fourth transistor T4 is configured to transfer the power supply voltage Vcc to the fifth transistor T5 in response to the voltage transmitted from the third transistor T3. The fifth transistor T5 is configured to deliver the output of the fourth transistor T4 to the first node N1 of the latch 410 in response to the program signal PGM_S.

In the program operation, an address ADDR and write data will be received. In response to the column address of the address ADDR, the Y gate circuit 450 may be turned on. When the Y gate circuit 450 is turned on, write data will be transferred to the latch 410.

Thereafter, the selection signal BLSLT will be activated. When the select signal BLLST is activated, the select circuit 420 will electrically connect the first node and the bit line BL of the latch 410.

When the write data is program data, the voltage of the first node of the latch 410 will be at the low level. In addition, the voltage of the second node N2 of the latch 410 may be at a high level. If the voltage of the second node N2 of the latch 410 is at a high level, the third transistor T3 will be turned on. Therefore, the reference voltage Vref will be delivered to the gate of the fourth transistor T4.

The fourth transistor T4 is connected between the power supply voltage Vcc node and the fifth transistor T5. In response to the reference voltage Vref received from the third transistor T3, the fourth transistor T4 will transfer the power supply voltage Vcc to the fifth transistor T5. In exemplary embodiments, the level of the voltage transmitted to the fifth transistor T5 through the fourth transistor T4 may be lower than the gate voltage of the fourth transistor T4, that is, the reference voltage Vref. For example, the level of the reference voltage Vref may be set such that the level of the voltage transferred through the fourth transistor T4 to the fifth transistor T5 is adjusted to the first bit line voltage VBL1. In other words, in response to the reference voltage Vref transmitted through the third transistor T3, the fourth transistor T4 adjusts the level of the power supply voltage Vcc to the level of the first bit line voltage VBL1. 5 will be transferred to transistor T5.

In the write operation, the program signal PGM_S will be activated. Thus, during the write operation, the output of the bias circuit 460 will be delivered to the bit line BL. That is, when the write data is program data, the bit line BL will be set up to the first bit line voltage VBL1.

When the write data is program inhibited data, the voltage of the first node N1 of the latch 410 will be at a high level. In addition, the voltage of the second node N2 of the latch 410 may be at a low level. If the voltage of the second node N2 of the latch 410 is at a low level, the third transistor T3 of the bias circuit 460 will be turned off. Therefore, the fourth transistor T4 is also turned off, and the bias circuit 460 and the bit line BL will be electrically disconnected. Since the voltage of the first node N1 of the latch 410 is at a high level, the bit line BL will be set to a high level. For example, the bit line BL may be set up to the second bit line voltage VBL2.

As described above, the page buffer 400 according to an exemplary embodiment of the present invention drives the bit line corresponding to the program data to the first bit line voltage VBL1 and the second bit line corresponding to the program inhibited data. And to drive to the bit line voltage VBL2. Thus, the reliability of the nonvolatile memory device 100 is improved.

FIG. 15 is a circuit diagram illustrating a second embodiment 400 ′ of one of the page buffers 131 to 13m of FIG. 13. Referring to FIG. 15, the page buffer 400 ′ may include a latch 410, a selection circuit 420, a loading circuit 430, a sensing circuit 440, a Y gate circuit 450, and a bias circuit 470. Include. The latch 410, the selection circuit 420, the loading circuit 430, the sensing circuit 440, and the Y gate circuit 450 are configured as described with reference to FIG. 14. Accordingly, detailed descriptions of the latch 410, the selection circuit 420, the loading circuit 430, the sensing circuit 440, and the Y gate circuit 450 are omitted.

The bias circuit 470 is configured in the same manner as the bias circuit 450 described with reference to FIG. 14 except that the fourth transistor T4 is removed. For example, the third transistor T3 is configured to transfer the reference voltage Vref in response to the voltage level of the second node N2 of the latch 410. The reference voltage Vref is transferred to the fifth transistor T5.

The fifth transistor T5 is turned on in response to the program signal PGM_S. That is, the fifth transistor T5 is configured to transfer the output of the third transistor T3 to the bit line BL in response to the program signal PGM_S. In exemplary embodiments, when the write data is program data, the third transistor T3 may be turned on. That is, when the write data is the program data, the bit line BL will be set up to the reference voltage Vref. In exemplary embodiments, the level of the reference voltage Vref may be set to the level of the first bit line voltage VBL1.

FIG. 16 is a circuit diagram illustrating a third embodiment 500 of one of the page buffers 131 to 13m of FIG. 13. Referring to FIG. 16, the page buffer 500 may include a first latch 510, a first selection circuit 520, a loading circuit 530, a sensing circuit 540, a Y gate circuit 550, and a bias circuit 560. ), A second latch 610, a data transfer circuit 620, and a dump circuit 630. The first latch 510, the first selection circuit 520, the loading circuit 530, the sensing circuit 540, the Y gate circuit 550, and the bias circuit 560 may include the latch described with reference to FIG. 14. 410, the selection circuit 420, the loading circuit 430, the sensing circuit 440, the Y gate circuit 450, and the bias circuit 460 are configured in the same manner. Thus, detailed descriptions of the first latch 510, the first selection circuit 520, the loading circuit 530, the sensing circuit 540, the Y gate circuit 550, and the bias circuit 560 are omitted.

The second latch 610 is connected to the data transfer circuit 620 and the dump circuit 630. The second latch 610 is configured to store write data or read data.

The data transfer circuit 620 is connected to the second latch 610, the Y gate circuit 550, and the second select circuit 640. The data transfer circuit 620 is configured to transfer data received through the Y gate circuit 550 to the latch 610. As an example, the data transfer circuit 620 includes at least two switches. For example, the data transfer circuit 620 includes sixth and seventh transistors T6 and T7. The sixth transistor T6 operates in response to the data signal DI. The seventh transistor T7 operates in response to the data inversion signal nDI. The sixth and seventh transistors T6 and T7 are connected between both ends of the second latch 610 and the Y gate circuit 550, respectively.

The dump circuit 630 is connected to the second latch 610, the first selection circuit 520, the loading circuit 530, and the sensing circuit 540. The dump circuit 630 is configured to transfer data stored in the second latch 610 to the first latch 510. For example, the dump circuit 630 includes at least one switch. For example, the dump circuit 630 includes at least one transistor. For example, the dump circuit 630 operates in response to the dump signal DUMP.

When the dump signal DUMP is activated, the data of the second latch 610 is transferred to the sensing node SO. At this time, when the latch signal LAT is activated, the data of the first latch 510 changes according to the voltage level of the sensing node SO. That is, data of the second latch 610 is transferred to the first latch 510.

The second selection circuit 640 is connected to the first latch 510, the first selection circuit 520, the bias circuit 560, and the Y gate circuit 550. For example, in a read operation, the second selection circuit 640 is configured to transfer read data stored in the first latch 510 to the data line DL through the Y gate circuit 550. For example, the second selection circuit 640 includes at least one switch. For example, the second selection circuit 640 includes at least one transistor. For example, the second selection circuit 640 operates in response to the second selection signal PBD0.

FIG. 17 is a circuit diagram illustrating a fourth embodiment 500 ′ of one of the page buffers 131 to 13m of FIG. 13. Referring to FIG. 17, the page buffer 500 may include a first latch 510, a first selection circuit 520, a loading circuit 530, a sensing circuit 540, a Y gate circuit 550, and a bias circuit 570. ), A second latch 610, a data transfer circuit 620, and a dump circuit 630. First latch 510, first selection circuit 520, loading circuit 530, sensing circuit 540, Y gate circuit 550, second latch 610, data transfer circuit 620, and dump Circuit 630 is configured in the same manner as described with reference to FIG. The bias circuit 570 is configured in the same manner as the bias circuit 470 described with reference to FIG. 15.

14 to 17, the components of the page buffer have been described. However, the components of the page buffer are not limited to the components described with reference to FIGS. 14 to 17.

By way of example, page buffer 500 or 500 'is configured to execute a cache program. For example, the first write data will be loaded into the first latch 510. While the first write data is programmed, the second write data will be loaded into the second latch 610. When the program of the first write data is completed, the second write data will be dumped to the first latch 610. Thereafter, the second write data will be programmed. Similarly, while the second write data is programmed, the third write data will be loaded into the second latch 610. When the cache program is executed, the operating speed of the nonvolatile memory device 100 may be improved.

By way of example, page buffer 500 or 500 'is configured to perform a multi-level program. For example, it is assumed that least significant bit (LSB) data is stored in a memory cell. The page buffer 500 or 500 ′ will read the least significant bit data stored in the memory cell and store it in the second latch 610. The page buffer 500 or 500 'will receive most significant bit (MSB) data. For example, the most significant bit data would be write data. The page buffer 500 or 500 ′ will store the received most significant bit data in the first latch 510. Based on the lowest bit data and the write data (or most significant bit data) stored in the first and second latches 510, 610, the page buffer 500 or 500 ′ may perform a multi-level program.

FIG. 18 is a circuit diagram illustrating a first application example BLKi_1 of an equivalent circuit of the memory block BLKi described with reference to FIGS. 3 to 5. Compared to the memory block BLKi of FIG. 6, in each NAND string NS, two ground select transistors GST1 and GST2 may be provided between the memory cells MC1 to MC6 and the common source line CSL. Can be. In addition, the ground select lines GSL1 and GSL2 corresponding to the ground select transistors GST1 or GST2 having the same height may be connected in common. In addition, the ground select lines GSL1 and GSL2 corresponding to the same NAND string NS may be connected in common.

FIG. 19 is a circuit diagram illustrating a second application example BLKi_2 of an equivalent circuit of the memory block BLKi described with reference to FIGS. 3 to 5. Compared to the memory block BLKi_1 of FIG. 18, in each NAND string NS, two string select transistors SST1 and SST2 may be provided between the memory cells MC1 ˜ MC5 and the bit line BL. have.

FIG. 20 is a circuit diagram illustrating a third application example BLKi_3 of an equivalent circuit of the memory block BLKi described with reference to FIGS. 3 to 5. Compared to the memory block BLKi_2 of FIG. 19, the string select lines SSL corresponding to the same NAND string NS are connected in common.

FIG. 21 is a circuit diagram illustrating a fourth application example BLKi_4 of an equivalent circuit of the memory block BLKi described with reference to FIGS. 3 to 5. Compared to the memory block BLKi of FIG. 6, a dummy memory cell DMC is provided between the string select transistor SST and the memory cells MC1 ˜ MC6 in each NAND string. The dummy memory cells DMC are commonly connected to the dummy word line DWL. That is, the dummy word line DWL is provided between the string select lines SSL1 to SSL3 and the word lines WL1 to WL6.

FIG. 22 is a circuit diagram illustrating a fifth application example BLKi_5 of an equivalent circuit of the memory block BLKi described with reference to FIGS. 3 to 5. Compared to the memory block BLKi of FIG. 6, a dummy memory cell DMC is provided between the ground select transistor GST and the memory cells MC1 to MC6 in each NAND string. The dummy memory cells DMC are commonly connected to the dummy word line DWL. That is, the dummy word line DWL is provided between the ground select line GSL and the word lines WL1 to WL6.

FIG. 23 is a circuit diagram illustrating a sixth application example BLKi_6 of an equivalent circuit of the memory block BLKi described with reference to FIGS. 3 to 5. Compared to the memory block BLKi of FIG. 6, a dummy memory cell DMC is provided between the string select transistor SST and the memory cells MC1 to MC5 in each NAND string. The dummy memory cells DMC are commonly connected to the first dummy word line DWL1. That is, the first dummy word line DWL1 is provided between the string select lines SSL1 to SSL3 and the word lines WL1 to WL6.

In each NAND string, a dummy memory cell DMC is provided between the ground select transistor GST and the memory cells MC1 ˜ MC5. The dummy memory cells DMC are commonly connected to the second dummy word line DWL2. That is, the dummy word line DWL2 is provided between the ground select line GSL and the word lines WL1 to WL5.

FIG. 24 is a block diagram illustrating another embodiment of the memory block BLKi of FIG. 3. Compared to the memory block BLKi of FIG. 3, in the memory block BLKi ', the pillars 113' may be provided in the form of a square pillar. In addition, insulating materials 120 are provided between the pillars 113 ′ disposed along the first direction.

In exemplary embodiments, the insulating materials 120 may extend along the second direction and be connected to the substrate 111. In addition, the insulating materials 120 may extend along the first direction in a region other than the region where the pillars 113 ′ are provided. That is, the conductive materials 211 to 291, 212 to 292, and 213 to 293 extending along the first direction described with reference to FIG. 3 are each formed by the insulating materials 120. , 211b-291b, 212a-292a, 212b-292b, 213a-293a, 213b-293b). In other words, the separated portions of the conductive materials 211a to 291a, 211b to 291b, 212a to 292a, 212b to 292b, and 213a to 293a and 213b to 293b will be electrically insulated.

In the region on the first and second doped regions 311 and 312, each pillar 113 ′ has one NAND with one portions 211a to 291a of the conductive materials extending in the first direction and the insulating film 116. The string NS may be formed, and another NAND string NS may be formed from the other portions 211b to 291b of the conductive materials extending in the first direction and the insulating layer 116.

In the region on the second and third doped regions 312 and 313, each pillar 113 ′ has one NAND with one portions 212a to 292a of the conductive materials extending in the first direction and the insulating film 116. The string NS may be formed, and another NAND string NS may be formed from the other portions 212b to 292b of the conductive materials extending in the first direction and the insulating layer 116.

In the region on the third and fourth doped regions 313 and 314, each pillar 113 ′ has one NAND with one portions 213a to 293a of the conductive materials extending in the first direction and the insulating film 116. The string NS may be formed, and another NAND string NS may be formed from the other portions 213b to 293b of the conductive materials extending in the first direction and the insulating layer 116.

That is, the pillars 113 'are electrically insulated by using the insulating layer 120 to electrically insulate the conductive materials 211a to 291a and 211b to 291b extending in the first direction provided on both sides of the pillars 113'. ) May form two NAND strings NS.

FIG. 25 is a perspective view illustrating a second embodiment of the memory block of FIG. 2. FIG. 26 is a cross-sectional view taken along line II-II ′ of the memory block BLKj of FIG. 25. 25 and 26, except that the second type doped region 315 on the substrate 111 is provided in the form of a plate under the pillars 113, the memory block BLKj is illustrated in FIGS. It is configured as described with reference to 23. Accordingly, the equivalent circuit of the memory block BLKj will also appear as described with reference to FIGS. 3 to 23.

FIG. 27 is a perspective view illustrating a third embodiment of the memory block of FIG. 2. FIG. 28 is a cross-sectional view taken along line III-III ′ of the memory block BLKp of FIG. 27. 27 and 28, a second type doped region 315 in the form of a plate is provided on the substrate 111. The conductive materials 221 'to 281' are provided in a plate form. The insulating film 116 ′ is provided to the surface layer 116 ′ of the pillar 113 ′. Interlayer 114 'of pillar 113' includes p-type silicon. The intermediate layer 114 ′ of the pillar 113 ′ acts as the body 114 ′ in the second direction. The inner layer 115 'of the pillar 113' includes an insulating material.

FIG. 29 is a perspective view illustrating a fourth embodiment of the memory block of FIG. 2. FIG. 30 is a cross-sectional view taken along line IV-IV ′ of the memory block BLKq of FIG. 29.

29 and 30, first to fourth upper word lines UW1 to UW4 extending along the first direction are sequentially provided along the second direction on the substrate 111. The first to fourth upper word lines UW1 to UW4 are spaced apart by a predetermined distance along the second direction. First upper pillars UP1 are sequentially disposed along the first direction and penetrate the first to fourth upper word lines UW1 to UW4 along the second direction.

On the substrate 111, first to fourth lower word lines DW1 to DW4 extending along the first direction are sequentially provided along the second direction. The first to fourth lower word lines DW1 to DW4 are spaced apart by a predetermined distance along the second direction. First lower pillars DP1 are sequentially disposed along the first direction and penetrate the first to fourth lower word lines DW1 to DW4 along the second direction. The second lower pillars DP2 are sequentially disposed in the first direction and penetrate the first to fourth lower word lines DW1 to DW4 in the second direction. In exemplary embodiments, the first lower pillars DP1 and the second lower pillars DP2 may be arranged in parallel along the second direction.

On the substrate 111, fifth to eighth upper word lines UW5 to UW8 extending along the first direction are sequentially provided along the second direction. The fifth to eighth upper word lines UW5 to UW8 are spaced apart by a predetermined distance along the second direction. Second upper pillars UP2 are sequentially disposed along the first direction and penetrate the fifth to eighth upper word lines UW5 to UW8 along the second direction.

The common source line CSL extending in the first direction is provided on the first and second lower pillars DP1 and DP2. In exemplary embodiments, the common source line CSL may be n-type silicon. In exemplary embodiments, when the common source line CSL is formed of a conductive material having no polarity such as metal or polysilicon, the common source line CSL may be disposed between the common source line CSL and the first and second lower pillars DP1 and DP2. n-type sources may additionally be provided. In exemplary embodiments, the common source line CSL and the first and second lower pillars DP1 and DP2 may be connected through contact plugs, respectively.

Drains 320 are provided on the first and second upper pillars UP1 and UP2, respectively. By way of example, the drains 320 may be n-type silicon. A plurality of bit lines BL1 to BL3 extending along the third direction are sequentially provided along the first direction on the drains 320. In exemplary embodiments, the bit lines BL1 to BL3 may be made of metal. In exemplary embodiments, the bit lines BL1 to BL3 and the drains 320 may be connected through contact plugs.

Each of the first and second upper pillars UP1 and UP2 includes a surface layer 116 ″ and an inner layer 114 ″. Each of the first and second lower pillars DP1 and DP2 includes a surface layer 116 ″ and an inner layer 114 ″. The surface layers 116 ″ of the first and second upper pillars UP1 and UP2 and the first and second lower pillars DP1 and DP2 may include a blocking insulating layer, a charge storage layer, and a tunneling insulating layer. .

The tunnel insulating film will include a thermal oxide film. The charge storage film 118 may include a nitride film or a metal oxide film (eg, an aluminum oxide film, a hafnium oxide film, or the like). The blocking insulating layer 119 may be formed in a single layer or multiple layers. The blocking insulating film 119 may be a high dielectric film (eg, an aluminum oxide film, a hafnium oxide film, etc.) having a higher dielectric constant than the tunnel insulating film and the charge storage film. In exemplary embodiments, the tunnel insulation layer, the charge storage layer, and the blocking insulation layer may constitute an oxide-nitride-oxide (ONO).

The inner layers 114 ″ of the first and second upper pillars UP1 and UP2 and the first and second lower pillars DP1 and DP2 may be p-type silicon. The first and second upper pillars UP1 and UP2 and the inner layer 114 ″ of the first and second lower pillars DP1 and DP2 operate as a body.

The first upper pillars UP1 and the first lower pillars DP1 are connected through the first pipeline contacts PC1. In exemplary embodiments, the surface layers 116 ″ of the first upper pillars UP1 and the first lower pillars DP1 may be connected through the surface layers of the first pipeline contacts PC1, respectively. The surface layers of the first pipeline contacts PC1 may be made of the same materials as the surface layers 116 ″ of the first upper pillars UP1 and the first lower pillars DP1.

In exemplary embodiments, the inner layers 114 ″ of the first upper pillars UP1 and the first lower pillars DP1 may be connected through the inner layers of the first pipeline contacts PC1, respectively. The inner layers of the first pipeline contacts PC1 may be made of the same materials as the inner layers 114 ″ of the first upper pillars UP1 and the first lower pillars DP1.

That is, the first upper pillars UP1 and the first to fourth upper word lines UW1 to UW4 form first upper strings, and the first lower pillars DP1 and the first to fourth lower words. The lines DW1 to DW4 form first lower strings. The first upper strings and the first lower strings are each connected through first pipeline contacts PC1. The drains 320 and the bit lines BL1 to BL3 are connected to one end of the first upper strings. The common source line CSL is connected to one end of the first lower strings. That is, the first upper strings and the first lower strings form a plurality of strings connected between the bit lines BL1 to BL3 and the common source line CSL.

Similarly, the second upper pillars UP2 and the fifth to eighth upper word lines UW5 to UW8 form second upper strings, and the second lower pillars DP2 and the first to fourth lower words. The lines DW1 to DW4 form second lower strings. The second upper strings and the second lower strings are connected through second pipeline contacts PC2. The drains 320 and the bit lines BL1 to BL3 are connected to one end of the second upper strings. The common source line CSL is connected to one end of the second lower strings. That is, the second upper strings and the second lower strings form a plurality of strings connected between the bit lines BL1 to BL3 and the common source line CSL.

An equivalent circuit of the memory block BLKi_7 is shown in FIG. 3 except that eight transistors are provided in one string, and two strings are connected to each of the first to third bit lines BL1 to BL3. will be. However, the number of word lines, bit lines, and strings of the memory block BLKi_7 is not limited.

By way of example, first and second pipeline contact gates (not shown) are provided respectively to form a channel in the bodies 114 ″ in the first and second pipeline contacts PC1, PC2. Can be. By way of example, first and second pipeline contact gates (not shown) may be provided on the surface of the first and second pipeline contacts PC1, PC2.

For example, the lower word lines DW1 to DW4 are shared in the adjacent lower pillars DP1 and DP2. However, when the upper pillars adjacent to the upper pillars UP1 or UP2 are added, the adjacent upper pillars may be configured to share the upper word lines UW1 to UW4 or UW5 to UW8.

FIG. 31 is a block diagram illustrating a memory system 1000 including the nonvolatile memory device 100 of FIG. 1. Referring to FIG. 31, the memory system 1000 includes a nonvolatile memory device 1100 and a controller 1200.

The nonvolatile memory device 1100 may be configured and operate as described with reference to FIGS. 1 to 30.

The controller 1200 is connected to a host and the nonvolatile memory device 1100. In response to a request from the host, the controller 1200 is configured to access the nonvolatile memory device 1100. For example, the controller 1200 is configured to control read, write, erase, and background operations of the nonvolatile memory device 1100. The controller 1200 is configured to provide an interface between the nonvolatile memory device 1100 and the host. The controller 1200 is configured to drive firmware for controlling the nonvolatile memory device 1200.

For example, as described with reference to FIG. 1, the controller 1200 is configured to provide a control signal CTRL and an address ADDR to the nonvolatile memory device 1100. The controller 1200 is configured to exchange data DATA with the nonvolatile memory device 1200.

In exemplary embodiments, the controller 1200 may further include well-known components, such as random access memory (RAM), a processing unit, a host interface, and a memory interface. The RAM is used as at least one of an operating memory of the processing unit, a cache memory between the nonvolatile memory device 1100 and the host, and a buffer memory between the nonvolatile memory device 1100 and the host. do. The processing unit controls the overall operation of the controller 1200.

The host interface includes a protocol for performing data exchange between the host and the controller 1200. For example, the controller 1200 may include a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-express) protocol, an advanced technology attachment (ATA) protocol, External (host) through at least one of a variety of interface protocols, such as Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol. Are configured to communicate with each other. The memory interface interfaces with the nonvolatile memory device 1100. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system 1000 may be configured to additionally include an error correction block. The error correction block is configured to detect and correct an error of data read from the nonvolatile memory device 1100 using an error correction code (ECC). By way of example, the error correction block is provided as a component of the controller 1200. The error correction block may be provided as a component of the nonvolatile memory device 1100.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to configure a memory card. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device such that a personal computer memory card international association (PCMCIA), a compact flash card (CF), and a smart media card (SM, Memory cards such as SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS) and the like.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to configure a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 10 is used as the semiconductor drive SSD, an operation speed of a host connected to the memory system 10 is significantly improved.

As another example, the memory system 10 may be a computer, an ultra mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless device. Wireless phones, mobile phones, smart phones, e-books, portable multimedia players, portable game consoles, navigation devices, black boxes ), Digital camera, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder video recorder, digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, Any of a variety of electronic devices that make up the informatics network, is provided to one of the various components of the electronic device, such as any of a variety of components that make up the RFID device, or a computing system.

In exemplary embodiments, the nonvolatile memory device 1100 or the memory system 1000 may be mounted in various types of packages. For example, the nonvolatile memory device 1100 or the memory system 1000 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), and plastic dual in. Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) It can be packaged and mounted in the same manner as Wafer-Level Processed Stack Package (WSP).

32 is a block diagram illustrating an application example of the memory system 1000 of FIG. 31. Referring to FIG. 32, the memory system 2000 includes a nonvolatile memory device 2100 and a controller 2200. The nonvolatile memory device 2100 includes a plurality of nonvolatile memory chips. The plurality of nonvolatile memory chips are divided into a plurality of groups. Each group of the plurality of nonvolatile memory chips is configured to communicate with the controller 2200 through one common channel. In FIG. 32, the plurality of nonvolatile memory chips are illustrated to communicate with the controller 2200 through the first through kth channels CH1 through CHk. Each nonvolatile memory chip is configured similarly to the nonvolatile memory device 100 described with reference to FIGS. 1 to 30.

In FIG. 32, a plurality of nonvolatile memory chips are connected to one channel. However, it will be appreciated that the memory system 2000 can be modified such that one nonvolatile memory chip is connected to one channel.

33 is a block diagram illustrating a computing system 3000 including the memory system 2000 described with reference to FIG. 32. Referring to FIG. 33, the computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, and a memory system 2000. .

The memory system 3500 is electrically connected to the CPU 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

In FIG. 33, the nonvolatile memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200. However, the nonvolatile memory device 2100 may be configured to be directly connected to the system bus 3500.

In FIG. 33, the memory system 2000 described with reference to FIG. 32 is provided. However, the memory system 2000 may be replaced with the memory system 1000 described with reference to FIG. 31.

In exemplary embodiments, the computing system 3000 may be configured to include all of the memory systems 1000 and 2000 described with reference to FIGS. 31 and 32.

In the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims of the following.

100: nonvolatile memory device
NS: NAND string
130: read and write circuit
131 ~ 13m: page buffers

Claims (10)

A program method of a nonvolatile memory device comprising groups of memory cells sequentially provided in a direction perpendicular to a substrate:
Applying a first voltage to the select bit line;
Applying a second voltage to the unselected bit line;
Applying a third voltage to the string select line corresponding to the selected memory cells;
Applying a fourth voltage to the string select line corresponding to the unselected memory cells; And
Applying a program operating voltage to the word lines,
And the first to third voltages are positive voltages. The method of claim 1,
The first voltage has a lower level than the second voltage,
The third voltage has a level higher than the fourth voltage, and
And the fourth voltage has a lower level than the first voltage. The method of claim 1,
And said second voltage is a power supply voltage. The method of claim 1,
Each group of memory cells constitute a NAND string,
Applying a program operating voltage to the word lines is
And applying a program operating voltage to the plurality of NAND strings sharing the select bit line and the plurality of NAND strings sharing the unselected bit line. A memory cell array comprising groups of memory cells sequentially provided in a direction perpendicular to the substrate; And
A read and write circuit configured to select bit lines coupled to the memory cell array,
In a program operation, the read and write circuit is configured to apply a positive voltage to bit lines corresponding to the memory cells to be programmed. The method of claim 5, wherein
Each group of memory cells constitutes NAND strings,
Each of the bit lines is connected to at least two of the plurality of NAND strings,
And a decoder configured to transfer a program operating voltage to word lines connected to the at least two NAND strings during a program operation. The method according to claim 6,
The read and write circuits include page buffers corresponding to the bit lines, respectively;
Each page buffer
A latch configured to receive and store write data during a program operation; And
And a bias circuit configured to set up a corresponding bit line to the positive voltage when the write data stored in the latch is program data. The method of claim 7, wherein
The bias circuit comprises first and second transistors,
A gate node of the first transistor is connected to the latch, a first node of the transistor is provided with a reference voltage, and a second node of the transistor is connected to a gate node of the second transistor,
And a first node of the second transistor receives a power supply voltage and a second node of the second transistor is connected to the corresponding bit line. The method of claim 8,
The bias circuit is
A third transistor coupled between the second node of the second transistor and the corresponding bit line;
And the third transistor electrically connects the second node and the corresponding bit line of the second transistor in response to a program operation signal. Nonvolatile memory devices; And
A controller configured to control the nonvolatile memory device,
The nonvolatile memory device
A memory cell array comprising groups of memory cells sequentially provided in a direction perpendicular to the substrate; And
A read and write circuit configured to select bit lines coupled to the memory cell array,
In a program operation, the read and write circuit is configured to apply a positive voltage to bit lines corresponding to the memory cells to be programmed.

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