KR20110091993A - Voltage regulating circuit and semiconductor memory device having the same - Google Patents

Abstract

The voltage generation circuit of the present invention includes a first pumping circuit for outputting a first pumping voltage to an output terminal in response to an oscillation signal and a first control signal of an oscillator; A second pumping circuit outputting a second pumping voltage to an output terminal in response to the oscillation signal and the second control signal; A regulator for outputting a first control signal to operate the first pumping circuit if the potential of the output terminal is lower than a target level; And a pumping circuit controller for outputting a second control signal to operate the second pumping circuit to raise the potential of the output terminal to the target level when a predetermined time elapses with the potential of the output terminal lower than the target level. Therefore, ripple generation of the output voltage can be minimized.

Description

Voltage regulating circuit and semiconductor memory device having same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating an operating voltage of a semiconductor memory device, and more particularly to a voltage generating circuit capable of minimizing ripple of an operating voltage and a semiconductor memory device having the same.

The flash memory device of the semiconductor memory device includes a voltage generation circuit that generates a high voltage in the chip itself. The voltage generation circuit is configured to raise the low voltage in the pumping operation to output the high voltage.

In this high voltage generation circuit, a plurality of charge pump circuits are connected in series, and in response to an input clock, a voltage rising from the previous charge pump circuit is increased to a higher voltage of the next stage charge pump circuit to obtain a high voltage at a target level. Create

A regulator is needed to keep the output voltage of this high voltage generation circuit constant at the target level. Generally, the regulator compares the voltage divided by the resistor with the reference voltage from the output voltage of the charge pump circuit to drive the charge pump circuit if the output voltage is lower than the reference voltage, and pumps the charge pump circuit if the divider voltage is higher than the reference voltage. Stop the operation.

Although the high voltage should be output at the target level, in this driving method, a ripple phenomenon may occur in which the high voltage is momentarily higher than the target level. The greater the ripple, the higher the probability that the chip will malfunction.

Disclosure of Invention Technical Problem The present invention provides a voltage generation circuit and a semiconductor memory device including the same, capable of minimizing ripple generation of an output voltage by adjusting a driving capability of a charge pump circuit according to a difference between an output voltage level and a target level. It is.

In order to solve the above technical problem, the voltage generating circuit according to the embodiment of the present invention,

A first pumping circuit configured to output a first pumping voltage to an output terminal in response to the oscillation signal of the oscillator and the first control signal;

A second pumping circuit outputting a second pumping voltage to an output terminal in response to the oscillation signal and the second control signal;

A regulator for outputting the first control signal to operate the first pumping circuit if the potential of the output terminal is lower than a target level;

A pumping circuit controller configured to output the second control signal so that the second pumping circuit operates to raise the potential of the output terminal to the target level when a predetermined time elapses with the potential of the output terminal lower than the target level. Include.

In one embodiment, the first pumping circuit is

A first clock driving circuit generating a first main clock signal in response to the oscillation signal and the first control signal, and generating first and second clock signals having opposite levels in response to the first main clock signal; And

And a first charge pump circuit group configured to output the first pumping voltage in response to the first and second clock signals.

In an embodiment, the second pumping circuit is

A second clock driving circuit generating a second main clock signal in response to the oscillation signal and the second control signal, and generating first and second clock signals having opposite levels in response to the second main clock signal; And

And a second charge pump circuit group configured to output the second pumping voltage in response to the first and second clock signals.

In an embodiment, the pumping circuit controller is

A delay circuit receiving the first control signal and delaying the input signal for a predetermined time; And

It may include a timing adjustment circuit for outputting the second control signal delayed in the activation time of the first control signal.

In an embodiment, the regulator is

A voltage divider dividing a voltage of the output terminal;

A regulator driver for determining whether to drive the regulator; And

And a comparison unit configured to output the first control signal by comparing the divided voltage of the output terminal with a reference voltage.

In a semiconductor memory device according to an embodiment of the present invention,

A memory cell array in which memory cells for data storage are connected to word lines and bit lines;

Generates an operating voltage for a program or read operation, and controls a pumping circuit of a part of a pumping circuit including a plurality of charge pump circuits, and when the potential of the output terminal is lower than a target level, the pumping circuit of the part is driven to output an output voltage. And a voltage generation circuit which generates all the output voltages by driving all pumping circuits to increase the potential of the output terminal to the target level when a predetermined time elapses with the potential of the output terminal being lower than the target level. A voltage providing unit;

A row decoder which receives the operating voltage from the voltage providing unit and transfers the operating voltage to the memory cell array according to a row address; And

And a control circuit for outputting a control signal for controlling the operation of the voltage providing unit and the row decoder.

In an embodiment, the voltage generation circuit is

A first pumping circuit configured to output a first pumping voltage to an output terminal in response to the oscillation signal of the oscillator and the first control signal;

A second pumping circuit outputting a second pumping voltage to an output terminal in response to the oscillation signal and the second control signal;

A regulator for outputting the first control signal to operate the first pumping circuit if the potential of the output terminal is lower than a target level;

A pumping circuit controller configured to output the second control signal to operate the second pumping circuit to raise the potential of the output terminal to the target level when a predetermined time elapses with the potential of the output terminal lower than the target level;

It may include.

In one embodiment, the first pumping circuit is

A first clock driving circuit generating a first main clock signal in response to the oscillation signal and the first control signal, and generating first and second clock signals having opposite levels in response to the first main clock signal; And

And a first charge pump circuit group configured to output the first pumping voltage in response to the first and second clock signals.

In an embodiment, the second pumping circuit is

A second clock driving circuit generating a second main clock signal in response to the oscillation signal and the second control signal, and generating first and second clock signals having opposite levels in response to the second main clock signal; And

And a second charge pump circuit group configured to output the second pumping voltage in response to the first and second clock signals.

In an embodiment, the pumping circuit controller is

A delay circuit receiving the first control signal and delaying the input signal for a predetermined time; And

It may include a timing adjustment circuit for outputting the second control signal delayed in the activation time of the first control signal.

In an embodiment, the regulator is

A voltage divider dividing a voltage of the output terminal;

A regulator driver for determining whether to drive the regulator; And

And a comparison unit configured to output the first control signal by comparing the divided voltage of the output terminal with a reference voltage.

According to the voltage generation circuit and the semiconductor memory device having the same according to the present invention,

Initially, all the charge pump circuits are driven to increase the output voltage.When the output voltage is slightly lowered after reaching the target level, only some of the charge pump circuits are driven. By driving the charge pump circuits, ripple can be minimized to achieve the desired voltage level accurately. Therefore, malfunction of the chip can be greatly reduced.

1 is a block diagram illustrating a voltage generation circuit according to an embodiment of the present invention.
2 is a block diagram illustrating a voltage generation circuit according to another embodiment of the present invention.
3 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.
FIG. 4A is a block diagram illustrating the first pumping circuit of FIG. 2.
FIG. 4B is a block diagram illustrating the second pumping circuit of FIG. 2.
FIG. 5A is a block diagram illustrating the pumping circuit controller of FIG. 2.
FIG. 5B is a circuit diagram for explaining the detailed configuration of the timing adjustment circuit in FIG. 5A.
FIG. 6 is a circuit diagram illustrating a detailed configuration of the delay circuit of FIG. 5A.
7 is a timing diagram for describing an operation of a voltage generation circuit according to an embodiment of the present invention.
8 is a graph illustrating the ripple control effect of the voltage generation circuit according to the embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. .

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise. In addition, the terms “… unit”, “… unit”, “module”, etc. described in the specification mean a unit that processes at least one function or operation, which may be implemented by hardware or software or a combination of hardware and software. have.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

1 is a block diagram illustrating a voltage generation circuit according to an embodiment of the present invention.

Referring to FIG. 1, the voltage generation circuit 100 according to an embodiment of the present invention may include an oscillator 110, a clock driving circuit group 120, a charge pump circuit group 130, and a regulator 150. Include.

The oscillator 110 generates an oscillation signal OSC of a specific period and transmits it to the clock driver 120.

The clock driving circuit group 120 includes first clock driving circuits 120 <1> to n-th clock driving circuits 120 <n>, and the first to nth clock driving circuits output signals output from the regulator. In response to (Enable), two clock signals CLK and CLKb of opposite levels are output using the oscillation signal OSC.

Charge pump circuit group 130 includes first charge pump circuits 130 <1> to mth charge pump circuits 130 <m>, all charge pump circuits being connected in series. The first charge pump circuit 130 <1> to the i th charge pump circuit 130 <i> may perform a pumping operation in response to a clock signal generated from the first clock driving circuit 120 <1>. The i + 1 th charge pump circuit 130 <i + 1> to the j th charge pump circuit 130 <j> may pump an operation in response to a clock signal generated from the second clock driving circuit 120 <2>. The k th charge pump circuit 130 <k> to the m th charge pump circuit 130 <m> may perform a pumping operation in response to a clock signal generated from the n th clock driving circuit 120 <n>. To perform.

That is, the charge pump circuit group 130 may output the output voltage Pump_Out by performing a pumping operation in response to two clock signals CLK and CLKb having different levels output from the respective clock driving circuits.

The regulator 150 senses the output voltage of the charge pump circuit group 130 and adjusts the level of the output voltage so that the output voltage can be stabilized at the target level.

The regulator 150 compares the voltage divider 154 that divides the output voltage Pump_Out of the charge pump circuit group 130 and outputs the divided voltage Vdiv, the divided voltage Vdiv, and the reference voltage Vref. And a comparator 152 for outputting a signal (Enable) for controlling the operation of the clock driving circuit group 120, and a regulator driver 156 for controlling the operation of the regulator 150.

The voltage divider 154 includes a plurality of first and second resistors R1 and R2 connected between the output voltage node N and the ground terminal, and is input to the comparator 152 according to the ratio of these resistors. The divided voltage Vdiv is outputted.

The regulator driver 156 includes an NMOS transistor N156 connected between the second resistor R2 of the voltage divider 154 and the ground terminal. The regulator driver 156 connects the voltage divider 154 and the ground terminal in response to the enable signal Pump_EN applied to the gate of the NMOS transistor N156 to allow the regulator 150 to operate normally.

The comparator 152 compares the reference voltage Verf and the divided voltage Vdiv, and when the reference voltage Verf is larger, that is, when the output voltage Pump_Out is lower than the target level, the clock enable signal having a high level Outputs (Enable). The clock enable signal Enable is applied to the clock driving circuit group 120. Accordingly, the clock driving circuit group 120 continues to operate. When the reference voltage Verf is smaller by comparing the reference voltage Verf and the divided voltage Vdiv, that is, when the output voltage Pump_Out reaches the target level, the comparator 152 enables the clock of the low level. Output the signal (Enable). Similarly, the clock enable signal Enable is applied to the clock driving circuit group 120. Accordingly, the operation of the clock driving circuit group 120 is stopped.

The first capacitor C1 is connected between the output voltage node N and the ground terminal. The first capacitor C1 temporarily stores the voltage Pump_Out output from the charge pump circuit group 130. acts as a load capacitor.

The peripheral circuit 160 may include a switch block 162 and a memory cell array 164.

The switch block 162 connects the output voltage node N of the voltage generation circuit 100 and the memory cell array 164 according to an enable signal to supply an output voltage to the memory cell array 164. Can be.

In this voltage generation circuit 100, even if the output voltage Pump_Out is slightly lower than the target level, all of the charge pump circuits must be driven at the same time, so that ripple may occur.

2 is a block diagram illustrating a voltage generation circuit according to another embodiment of the present invention, and FIG. 3 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

2 and 3, a semiconductor memory device according to an embodiment of the present invention may include a memory cell array 310, a control circuit 320, a voltage providing unit 330, a row decoder 340, and a page buffer circuit unit ( 350 and column decoder 360.

The memory cell array 310 includes a plurality of memory cell blocks. Each memory cell block includes strings coupled to bit lines. That is, the strings are respectively connected to the bit lines and in parallel to the common source line. More specifically, each string is connected in series between a drain select transistor (not shown) connected to a bit line, a source select transistor (not shown) connected to a common source line, and a drain select transistor and a source select transistor. Memory cells. Gates of the drain select transistors are connected to become a drain select line, and gates of the source select transistors are connected to become a source select line. In addition, the control gates of the memory cells are connected to become word lines. Memory cells connected to one word line may be defined as pages. Further, even-numbered memory cells and odd-numbered memory cells among memory cells connected to one word line may be divided into different pages.

The control circuit 320 outputs one of a program signal PGM, a read signal READ, and an erase signal ERASE for determining the operation of the memory cells in response to the command signal CMD, and the page buffers The control signal PB SIGNALS of the page buffers is output to perform an operation corresponding to the operation of the memory cells determined by the control circuit 320. In addition, the control circuit 320 outputs the row address signal RADD and the column address signal CADD in response to the address signal ADD.

The voltage provider 330 outputs operating voltages required for the operation of the memory cells determined by the control circuit 320. For example, in the case of a program operation, the voltage provider 330 outputs a program voltage, a program pass voltage, and verification voltages. The voltage providing unit 330 includes a voltage generating circuit, which will be described later.

The row decoder 340 transfers the operating voltages output from the voltage providing unit 330 to select lines and word lines of the selected memory cell block in response to the row address signal RADD of the control circuit 330.

The column decoder 360 performs a function of sequentially outputting data read from the memory cells and stored in the page buffer circuit 350 to the outside, or transferring data input from the outside to the page buffer circuit 350. The column decoder 360 may operate in response to the column address signal CADD, and the column address signal CADD may be generated by the control circuit 320.

The page buffer circuit group 350 includes a plurality of page buffers. The page buffers are each connected to bit lines. The page buffers latch data to be stored in memory cells of the selected page in the selected memory cell block.

Hereinafter, the voltage generation circuit 200 included in the voltage providing unit 330 of the semiconductor memory device according to the embodiment of the present invention will be described.

The voltage generation circuit 200 according to the embodiment of the present invention includes an oscillator 210, a first pumping circuit 220, a second pumping circuit 230, a pumping circuit controller 240, and a regulator 250.

The oscillator 210 generates an oscillation signal OSC of a specific period and transmits the oscillation signal OSC to the first pumping circuit 220 and the second pumping circuit 230.

The first pumping circuit 220 performs a pumping operation in response to the oscillation signal OSC and the output signal Enable of the comparator 252 included in the regulator 250 to perform a first pumping voltage at the output terminal N. Outputs (Pump_Out1).

The second pumping circuit 230 performs a pumping operation in response to the oscillation signal OSC and the output signal Stg_L_EN of the pumping circuit controller 240 to output the second pumping voltage Pump_Out2 to the output terminal N.

The regulator 250 senses the output voltage Pump_Out2 of the second pumping circuit 230 or the output voltage Pump_Out1 to the first pumping circuit 220 and the output voltage Pump_Out2 to the second pumping circuit 230. Stabilize the output voltage to the target level. That is, the voltage at the output terminal N is stabilized at the target level.

The regulator 250 divides the voltage of the output terminal N and outputs the divided voltage Vdiv, and compares the divided voltage Vdiv and the reference voltage Vref to the first pumping circuit 220. And a comparator 252 for outputting a signal (Enable) for controlling the operation of the pumping circuit controller 240, and a regulator driver 256 for controlling the operation of the regulator 250.

The voltage divider 254 includes a plurality of first and second resistors R1 and R2 connected between the output voltage node N and the ground terminal, and is input to the comparator 252 according to the ratio of these resistors. The divided voltage Vdiv is outputted.

The regulator driver 256 includes an NMOS transistor N256 connected between the second resistor R2 of the voltage divider 254 and the ground terminal. The regulator driver 256 connects the voltage divider 254 and the ground terminal in response to the enable signal Pump_EN applied to the gate of the NMOS transistor N256 to allow the regulator 250 to operate normally.

The comparator 252 compares the reference voltage Verf and the divided voltage Vdiv to provide a high level enable signal Enable when the reference voltage Verf is larger, that is, when the output voltage is lower than the target level. Output The enable signal Enable is applied to the first pumping circuit 220 and the pumping circuit controller 240. When the reference voltage Verf is smaller by comparing the reference voltage Verf and the divided voltage Vdiv, that is, when the output voltage reaches the target level, the comparator 252 enables the low level enable signal Enable. Outputs Similarly, the enable signal Enable is applied to the first pumping circuit 220 and the pumping circuit controller 240.

The pumping circuit controller 240 receives an output signal (Enable) of the comparator 252 included in the regulator 250. The output signal Stg_L_EN is generated by delaying only the rising edge timing, that is, delaying only the activation time (or enable timing), without delaying the falling edge timing of the output signal Enable. . The output signal Enable is input to the second pumping circuit 230.

The first capacitor C1 is connected between the output voltage node N and the ground terminal. The first capacitor C1 serves as a load capacitor for temporarily storing the output voltage.

The peripheral circuit 260 may include a switch block 262 and a memory cell array 264.

The switch block 262 connects the output voltage node N of the voltage generation circuit 200 and the memory cell array 264 according to an enable signal to supply an output voltage to the memory cell array 264. Can be.

FIG. 4A is a block diagram illustrating the first pumping circuit of FIG. 2.

Referring to FIG. 4A, the first pumping circuit 220 includes a first logic gate NA1, a first clock driving circuit 222, and a first charge pump circuit group 224.

The first logic gate NA1 is a NAND gate, and generates a first main clock signal in response to the oscillation signal OSC of the oscillator and the output signal Enable of the regulator.

The first clock driving circuit 222 outputs two clock signals CLK and CLKb having opposite levels in response to the first main clock signal.

The first charge pump circuit group 224 includes a plurality of charge pump circuits, the charge pump circuits being connected in series. The first charge pump circuit group 224 may perform a pumping operation in response to two clock signals CLK and CLKb having opposite levels to output a first pumping voltage Pump_Out1 to an output terminal.

FIG. 4B is a block diagram illustrating the second pumping circuit of FIG. 2.

Referring to FIG. 4B, the second pumping circuit 230 includes a second logic gate NA2, a second clock driver 232, and a second charge pump circuit group 234.

The second logic gate NA2 is a NAND GATE, and generates a second main clock signal in response to the oscillation signal OSC of the oscillator and the output signal Stg_L_EN of the pumping circuit controller 240. Since the output signal Stg_L_EN of the pumping circuit controller 240 is a signal in which the activation time (enable timing) of the output signal Enable of the regulator is delayed, the second main clock signal is more likely to occur than the first main clock signal. ) Is later.

The second clock driving circuit 232 outputs two clock signals CLK and CLKb having opposite levels in response to the second main clock signal.

The second charge pump circuit group 234 includes a plurality of charge pump circuits, the charge pump circuits being connected in series. The second charge pump circuit group 234 may perform a pumping operation in response to two clock signals CLK and CLKb of opposite levels to output a second pumping voltage Pump_Out2 to an output terminal.

FIG. 5A is a block diagram illustrating the pumping circuit controller of FIG. 2.

Referring to FIG. 5A, the pumping circuit controller 240 includes a delay circuit 242 and a timing adjusting circuit 244.

The delay circuit 242 receives the output signal (Enable) of the regulator and outputs a delayed signal (Enable DLY).

The timing adjusting circuit 244 adjusts the timing of the output signal Enable DLY delayed by the delay circuit 242 and outputs a signal Stg_L_EN for controlling the second pumping circuit 230.

FIG. 5B is a circuit diagram for explaining the detailed configuration of the timing adjustment circuit in FIG. 5A.

Referring to FIG. 5B, the timing adjusting circuit 244 includes the first to fifth inverters INV1 to INV5, the first PMOS transistor P1 and the second PMOS transistor P2, the first NMOS transistor N1, and the first to fifth inverters INV1 to INV5. 2 NMOS transistor N2, and logic gate NA3.

The first PMOS transistor P1 and the second PMOS transistor P2 are connected in series between a power supply terminal and a ground terminal. The inversion signal / Pump_EN of the enable signal is applied to the gate of the first PMOS transistor P1 through the first inverter INV1 and the second inverter INV2. The output signal (Enable) of the regulator is applied to the gate of the second PMOS transistor P2.

The latch 245 includes a third inverter INV3 and a fourth inverter INV4. The node A of the latch 245 is connected to the second PMOS transistor P2, the node / A of the latch 245 is connected to the input terminal of the third logic gate NA3, and the other of the third logic gate NA3 is connected. The enable signal Pump_EN is applied to the input terminal. In addition, an output terminal of the third logic gate NA3 is connected to the fifth inverter INV5.

The first NMOS transistor N1 and the second NMOS transistor N2 are connected in parallel between the node A of the latch 245 and the ground terminal. The output signal Enable_DLY of the delay circuit 242 is applied to the gate of the first NMOS transistor N1. The inversion signal / Pump_EN of the enable signal is applied to the gate of the second NMOS transistor N2.

The operation of the timing adjustment circuit 244 having the above configuration will be described below.

When the output signal (Enable) of the regulator is applied to the delay circuit 242 at a high level, the delay circuit 242 delays for a predetermined time (for example, 3T, where T may be one period of the applied signal). Therefore, the output signal Stg_L_EN of the timing adjustment circuit 244 maintains a low level for a predetermined time.

When the output signal Enable_DLY of the delay circuit 242 reaches a high level after a predetermined time, the output signal Stg_L_EN of the timing adjustment circuit 244 is changed to a high level.

That is, when the output signal Enable_DLY of the delay circuit 242 is applied to the gate of the first NMOS transistor N1 at a high level, the first NMOS transistor N1 is turned on. Thus, node A of latch 245 goes low and node / A of latch 245 goes high. Since the enable signal Pump_EN is applied at a high level, a low level signal is output from the third logic gate NA3, and a high level output signal Stg_L_EN is output through the fifth inverter INV5.

Since the enable signal Pump_EN is applied at the high level while the output signal Enable_DLY of the delay circuit 242 is applied at the high level, the first PMOS transistor P1 is turned on, but the output signal of the regulator is enabled. Is applied at a high level, the second PMOS transistor P2 is turned off, and a power supply voltage (eg, Vcc) is not applied to the node A. In addition, the second NMOS transistor N2 is also turned off because the enable signal Pump_EN is applied at a high level.

Thereafter, when the regulator output signal Enable input to the delay circuit 242 becomes low, the output signal Stg_L_EN of the timing adjustment circuit 244 is immediately changed to low level without delay.

That is, when the output signal Enable_DLY of the delay circuit 242 is applied to the gate of the first NMOS transistor N1 at a low level, the first NMOS transistor N1 is turned off. Since the enable signal Pump_EN is applied at a high level, the first PMOS transistor P1 is turned on. When the output signal Enable_DLY of the delay circuit 242 is applied at the low level, the output signal Enable of the regulator is also applied at the low level, so the second PMOS transistor P2 is also turned on. Therefore, a power supply voltage (eg, Vcc) is applied to node A so that node A maintains a high level. As a result, node / A remains low. Since the enable signal Pump_EN is applied at a high level, a high level signal is output from the third logic gate NA3, and a low level output signal Stg_L_EN is output through the fifth inverter INV5.

The second NMOS transistor N2 is turned off because the enable signal Pump_EN is applied at a high level.

As a result, when the output signal (Enable) of the regulator is applied to the delay circuit 242 at a high level, after a predetermined time (for example, 3T), the output signal Stg_L_EN of the timing adjustment circuit 244 is also output at a high level. When the output signal Enable of the regulator is applied to the delay circuit 242 at the low level, the output signal Stg_L_EN of the timing adjustment circuit 244 is immediately output at the low level without delay.

As such, the timing adjustment circuit 244 also outputs the delay signal Stg_L_EN of the timing adjustment circuit 244 when the input signal (Enable) of the delay circuit 242 is at a high level, that is, at the rising edge timing. Delay for a predetermined time by the output signal (Enable_DLY) of (42), but when the input signal (Enable) of the delay circuit 42 falls to a low level, that is, the timing adjustment circuit 244 at the falling edge timing Output signal Stg_L_EN drops to low level immediately without delay.

FIG. 6 is a circuit diagram illustrating a detailed configuration of the delay circuit of FIG. 5A.

Referring to FIG. 6, the delay circuit 242 includes sixth to ninth inverters INV6 to INV9, a third PMOS transistor P3 and a third NMOS transistor N3, a plurality of resistors R3 to Rn, Capacitor C2 and fourth logic gate NA4 are included.

The third PMOS transistor P3 and the third NMOS transistor N3 are connected in series between the power supply terminal and the ground terminal. A plurality of resistors R3 to Rn are connected in series between the third PMOS transistor P3 and the third NMOS transistor N3. The gate of the third PMOS transistor P3 and the gate of the third NMOS transistor N3 are connected to each other, and these gates are connected to each other through a sixth inverter INV6 and a seventh inverter INV7 connected in series. The output signal Enable is applied as an input signal.

The capacitor C2 and the eighth inverter INV8 are connected in parallel between the third PMOS transistor P3 and the resistors R3 to Rn. The other end of the capacitor C2 is connected to the ground terminal.

The output signal of the eighth inverter INV8 and the input signal Enable of the delay circuit 242 are applied to the input terminal of the fourth logic gate NA4. When the ninth inverter INV9 passes, the delayed input signal Enable_DLY is applied. Is output.

The operation of the delay circuit 242 having the above configuration will be described below.

First, when the input signal Enable is applied at a low level, the input signal Enable is inverted while passing through the sixth inverter INV6 and the seventh inverter INV7, respectively, and is low to the gates of the third PMOS transistor P3 and the third NMOS transistor N3. A level signal is applied. Accordingly, the third PMOS transistor P3 is turned on and the third NMOS transistor N3 is turned off. Therefore, the power supply voltage (for example, Vcc) is charged to the capacitor C2. Since the input signal Enable is applied at the low level, the output of the fourth logic gate NA4 is output at the high level regardless of the signal of the other input terminal (that is, without delay) and is output by the ninth inverter INV9. Inverted to output the low level output signal Enable_DLY.

Subsequently, when the input signal Enable is applied at a high level, the input signal Enable is inverted to pass through the sixth inverter INV6 and the seventh inverter INV7, respectively, to the gates of the third PMOS transistor P3 and the third NMOS transistor N3. The high level signal is applied. Accordingly, the third PMOS transistor P3 is turned off and the third NMOS transistor N3 is turned on. As a result, a current path is formed between the capacitor C2 and the resistors R3 to Rn and the third NMOS transistor N3. Accordingly, the charge charged in the capacitor C2 is discharged, and when a sufficient level passes after a predetermined time, the charge is inverted by the eighth inverter INV8, and a high level signal is applied to the fourth logic gate NA4. Here, the plurality of resistors R3 to Rn connected in series determine the time delayed by the delay circuit 242. The delay time may be adjusted by adjusting the size of the resistors R3 to Rn. In the present invention, a delay time of 3T (T: pulse period) will be described as an example. When the high level input signal Enable and the high level signal inverted by the eighth inverter INV8 are applied to the fourth logic gate NA4, a low level signal is output and inverted by the ninth inverter INV9. The high level output signal Enable_DLY is output. The output signal Enable_DLY at this time is a signal delayed by the delay circuit 242.

7 is a timing diagram for describing an operation of a voltage generation circuit according to an embodiment of the present invention.

The operation of the voltage generation circuit according to the embodiment of the present invention will be described with reference to FIGS. 2 and 7.

(1) T1 section

A high level enable signal Pump_EN is applied to the regulator driver 256 to operate the regulator.

Regardless of whether the regulator is driven or not, the oscillator 210 continuously outputs an oscillation signal OSC having a specific frequency.

In a section in which the output voltage of the voltage generation circuit increases, the divider voltage Vdiv of the comparator 252 of the regulator determined by the resistance ratio is smaller than the reference voltage Vref, so that the comparator 252 has a high level enable signal. Outputs (Enable).

When a high level enable signal (Enable) is input to the first pumping circuit 220, the first clock driving circuit of the first pumping circuit 220 starts driving and two clock signals CLK and CLKb of opposite levels are generated. Is output. These clock signals CLK and CLKb are input to the first charge pump circuit group to continuously increase the output voltage.

In addition, the high level enable signal Enable is input to the pumping circuit controller 240. A delayed (for example, 3T) signal (Enable_DLY) is output from the delay circuit of the pumping circuit controller 240 and timing adjustment is performed. The high level output signal Stg_L_EN is output through the circuit. When the high level output signal Stg_L_EN is input to the second pumping circuit 230, the second clock driving circuit of the second pumping circuit 220 starts driving and two clock signals CLK and CLKb of opposite levels are output. do. These clock signals CLK and CLKb are input to the second charge pump circuit group to raise the output voltage.

When the output voltage continues to rise rapidly by the first pumping circuit 220 and the second pumping circuit 230 to reach a target level, the distribution voltage Vdiv of the comparator 252 is the reference voltage Vref. As it becomes larger, the comparator 252 outputs a low level enable signal Enable. Accordingly, the first clock driving circuit of the first pumping circuit 220 and the second clock driving circuit of the second pumping circuit 230 stop driving and the output of the clock signals CLK and CLKb is also stopped. As the input of the clock signals CLK and CLKb is stopped, the pumping operation of the first charge pump circuit group and the second charge pump circuit group is also stopped. The output voltage can then be lowered by leakage current or current consumption in the peripheral circuit.

(2) T2 section

When the regulating operation for maintaining the target voltage level starts, the enable signal (Enable) output from the comparator 252 is input in the form of a pulse.

In other words, when the output voltage (potential of the output terminal) is lower than the target level, the divided voltage Vdiv becomes smaller than the reference voltage Vref, thereby outputting the enable signal of the high level again, and accordingly, the charge pump circuit The output voltage rises again. In addition, when the output voltage is higher than the target level, the divider voltage Vdiv of the comparator 252 becomes greater than the reference voltage Vref, and the comparator 252 outputs a low level enable signal (Enable) again. Therefore, the driving of the charge pump circuit is stopped to repeat the operation of decreasing the output voltage to perform the regulating operation.

When the output voltage is significantly lower than the target level as in the T1 section due to sudden power consumption, both the first pumping circuit 220 and the second pumping circuit 230 are driven. However, even when driving both the first pumping circuit 220 and the second pumping circuit 230 in order to increase the output voltage fast in the T2 section, since only ripple (Ripple) can occur severely at this time only driving the first pumping circuit 220 Let's do it. The signal delayed in the delay circuit (Enable_DLY) because the enable signal (Enable) output from the comparator 252 is generated with a narrower pulse width than the time required for the output signal Stg_L_EN of the pumping circuit controller 240 to occur. ) Maintains a low level.

In more detail, the enable signal Enable and the output signal of the RC delay circuit are input to the input terminal of the fourth logic gate NA4. The fourth logic gate NA4 is a NAND GATE. When a high level enable signal (Enable) is input to one input terminal, the output signal varies according to the input signal of the other terminal. The signal is a signal that is delayed in the RC delay circuit. Therefore, when the enable signal (Enable) is input in the form of a pulse, the enable signal (Enable) falls from the high level to the low level before the signal is input to the other terminal, so that the output of the fourth logic gate NA4 is connected to the other terminal. High level is reached regardless of the signal. Therefore, the signal delayed by the delay circuit (Enable_DLY) through the inverter becomes a low level. That is, the signal delayed by the delay circuit Enable_DLY should also be output in the form of a pulse, but the low level is maintained because the pulse width of the enable signal is small.

As the delayed signal Enable_DLY of the delay circuit maintains the low level, the output signal Stg_L_EN of the timing adjustment circuit also maintains the low level. Therefore, only the first pumping circuit 220 may be driven without driving the second pumping circuit 230 to minimize occurrence of ripple.

(3) T3 section

If the output voltage drops significantly below the target level, for example during power regulation, the output voltage needs to rise quickly. In addition, during the regulating operation, only the first pumping circuit is driven to increase the output voltage. When the output voltage is lower than the target level even after a predetermined time (for example, 3T), the output voltage needs to be quickly increased again. At this time, the pulse width of the enable signal (Enable) output from the regulator becomes wider.

Therefore, the output signal Enable_DLY delayed by the delay circuit (for example, 3T) becomes a high level, and accordingly, the output signal Stg_L_EN of the pumping circuit controller is output at a high level so that the first pumping circuit 220 and the second pumping circuit are output. All of the 230 may be driven to quickly increase the output voltage.

8 is a graph illustrating the ripple control effect of the voltage generation circuit according to the embodiment of the present invention.

Referring to FIG. 8, in the case of a general voltage generation circuit, the width of the voltage change is large and the output voltage Pump_Out differs by 0.022V, whereas in the case of using the voltage generation circuit according to the embodiment of the present invention, the output voltage You can see that (Pump_Out) is only 0.003V difference.

Therefore, the ripple generation can be minimized by using the voltage generation circuit according to the embodiment of the present invention.

The embodiments of the present invention described above are not only implemented by the apparatus and method but may be implemented through a program for realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded, The embodiments can be easily implemented by those skilled in the art from the description of the embodiments described above.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

110210-oscillator 120-clock drive circuit group
130-Charge Pump Circuit Group 150,250-Regulator
152,252-comparison 154,254-voltage distribution
156,256-regulator drive 160,260-peripheral circuit
162,262-Switch Block 164,264,310-Memory Cell Array
220-first pumping circuit 222-first clock driving circuit
224-First Charge Pump Circuit Group 230-Second Pumping Circuit
232-second clock drive circuit 234-second charge pump circuit group
240-pumping circuit control unit 242-delay circuit
244-Timing Regulation Circuit 320-Control Circuit
330-voltage provider 340-low decoder
350-page buffer circuit group 360-column decoder

Claims (11)

A first pumping circuit configured to output a first pumping voltage to an output terminal in response to the oscillation signal of the oscillator and the first control signal;
A second pumping circuit outputting a second pumping voltage to an output terminal in response to the oscillation signal and the second control signal;
A regulator for outputting the first control signal to operate the first pumping circuit if the potential of the output terminal is lower than a target level;
A pumping circuit controller configured to output the second control signal to operate the second pumping circuit to raise the potential of the output terminal to the target level when a predetermined time elapses with the potential of the output terminal lower than the target level;
Voltage generation circuit comprising a.
The method of claim 1,
The first pumping circuit is
A first clock driving circuit generating a first main clock signal in response to the oscillation signal and the first control signal, and generating first and second clock signals having opposite levels in response to the first main clock signal; And
And a first charge pump circuit group outputting the first pumping voltage in response to the first and second clock signals.
The method of claim 1,
The second pumping circuit is
A second clock driving circuit generating a second main clock signal in response to the oscillation signal and the second control signal, and generating first and second clock signals having opposite levels in response to the second main clock signal; And
And a second charge pump circuit group outputting the second pumping voltage in response to the first and second clock signals.
The method of claim 1,
The pumping circuit control unit
A delay circuit receiving the first control signal and delaying the input signal for a predetermined time; And
And a timing adjusting circuit configured to output the second control signal delayed in activating the first control signal.
The method of claim 1,
The regulator
A voltage divider dividing a voltage of the output terminal;
A regulator driver for determining whether to drive the regulator; And
And a comparator for comparing the divided voltage of the output terminal with a reference voltage to output the first control signal.
A memory cell array in which memory cells for data storage are connected to word lines and bit lines;
Generates an operating voltage for a program or read operation, and controls a pumping circuit of a part of a pumping circuit including a plurality of charge pump circuits, and when the potential of the output terminal is lower than a target level, the pumping circuit of the part is driven to output an output voltage. And a voltage generation circuit which generates all the output voltages by driving all pumping circuits to increase the potential of the output terminal to the target level when a predetermined time elapses with the potential of the output terminal being lower than the target level. A voltage providing unit;
A row decoder which receives the operating voltage from the voltage providing unit and transfers the operating voltage to the memory cell array according to a row address; And
And a control circuit outputting a control signal for controlling the operation of the voltage providing unit and the row decoder.
The method of claim 6,
The voltage generation circuit
A first pumping circuit configured to output a first pumping voltage to an output terminal in response to the oscillation signal of the oscillator and the first control signal;
A second pumping circuit outputting a second pumping voltage to an output terminal in response to the oscillation signal and the second control signal;
A regulator for outputting the first control signal to operate the first pumping circuit if the potential of the output terminal is lower than a target level;
A pumping circuit controller configured to output the second control signal to operate the second pumping circuit to raise the potential of the output terminal to the target level when a predetermined time elapses with the potential of the output terminal lower than the target level;
And a semiconductor memory device.
The method of claim 7, wherein
The first pumping circuit is
A first clock driving circuit generating a first main clock signal in response to the oscillation signal and the first control signal, and generating first and second clock signals having opposite levels in response to the first main clock signal; And
And a first charge pump circuit group configured to output the first pumping voltage in response to the first and second clock signals.
The method of claim 7, wherein
The second pumping circuit is
A second clock driving circuit generating a second main clock signal in response to the oscillation signal and the second control signal, and generating first and second clock signals having opposite levels in response to the second main clock signal; And
And a second charge pump circuit group configured to output the second pumping voltage in response to the first and second clock signals.
The method of claim 7, wherein
The pumping circuit control unit
A delay circuit receiving the first control signal and delaying the input signal for a predetermined time; And
And a timing adjusting circuit configured to output the second control signal delayed in activating the first control signal.
The method of claim 7, wherein
The regulator
A voltage divider dividing a voltage of the output terminal;
A regulator driver for determining whether to drive the regulator; And
And a comparator for comparing the divided voltage of the output terminal with a reference voltage to output the first control signal.

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