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KR20110077561A - Electrostatic discharge pretection device - Google Patents

Electrostatic discharge pretection device Download PDF

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Publication number
KR20110077561A
KR20110077561A KR1020090134180A KR20090134180A KR20110077561A KR 20110077561 A KR20110077561 A KR 20110077561A KR 1020090134180 A KR1020090134180 A KR 1020090134180A KR 20090134180 A KR20090134180 A KR 20090134180A KR 20110077561 A KR20110077561 A KR 20110077561A
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KR
South Korea
Prior art keywords
type
diffusion layer
conductivity type
region
voltage
Prior art date
Application number
KR1020090134180A
Other languages
Korean (ko)
Inventor
송종규
Original Assignee
주식회사 동부하이텍
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Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020090134180A priority Critical patent/KR20110077561A/en
Publication of KR20110077561A publication Critical patent/KR20110077561A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A static electricity discharge protecting device is provided to adjust a trigger voltage in consideration of the operating voltage and a breakdown voltage of an internal circuit device. CONSTITUTION: A first conductive area(140) and a second conductive area are formed on a substrate(110). A diffusion layer is formed on the first conductive area and electrically connected to an anode. The diffusion layer is formed on second conductive areas(120,130) and electrically connected to a cathode. A second conductive doped area is located in the lower part of the second conductive area.

Description

Electrostatic Discharge Protection Device {Electrostatic discharge pretection device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an electrostatic discharge protection device that protects a semiconductor device from abnormal electrostatic discharge and overload.

Semiconductor integrated circuits are susceptible to high voltages and high currents introduced by electrostatic discharge (ESD) and electrical overstress (EOS) generated by human contact or equipment abnormalities. Static or overloading can cause high voltage or high current to flow into the integrated circuit at once, causing breakdown of the insulating film formed in the integrated circuit, destruction of the junction, and / or disconnection of the metal wiring, resulting in permanent destruction of the semiconductor integrated circuit. do.

The electrostatic discharge protection device functions to discharge a high current or a high current flowing into the semiconductor integrated circuit so as not to flow into the semiconductor integrated circuit. Means for performing the electrostatic discharge protection function include a GGNMOS, a PN junction diode, a bipolar junction transistor, and a silicon controlled rectifier (SCR).

GGNMOS and bipolar junction transistors are devices that discharge charge by positive feedback breakdown of drain and collector junctions and positive feedback caused by charge injection of source and emitter junctions, respectively, and concentrate the electric field on the drain or collector junction. It is vulnerable to effectively destroying and emitting EOS surges.

In comparison, silicon-controlled rectifiers can discharge static electricity by double injection between the wide junctions of different conductive wells to prevent concentration of the electric field. Silicon-controlled rectifiers are effective as an electrostatic discharge protection device for I / O pads due to their strong snapback characteristics, allowing them to instantaneously discharge static electricity, but when applied to power pads, latch-up and EOS surges due to low hold voltage This can cause destruction of the ESD device itself.

1 is a view showing an electrostatic discharge protection device using a general silicon controlled rectifier.

Referring to FIG. 1, a silicon controlled rectifier is formed by bonding an N-well 10 and a P-well 20 to a semiconductor substrate, and having a high concentration of p-type first diffusion layer (N-well 10). 12) is formed, and a high concentration n-type second diffusion layer 22 is formed in the P-well 20.

The N-well 10 and the first diffusion layer 12 are connected to an anode, and the P-well 20 and the second diffusion layer 22 are connected to a cathode. The N-well 10 is connected to the anode through a high concentration n-type third diffusion layer 14 formed in the N-well 10, and the P-well 20 is connected to the P-well 20. It is connected to the cathode through a high concentration p-type fourth diffusion layer 24 formed in the.

In the silicon controlled rectifier, the first diffusion layer 12 is formed in the N-well 10 between the third diffusion layer 14 and the P-well 20 and the second diffusion layer 22 is formed in the fourth. It is formed in the P-well 20 between the diffusion layer 24 and the N-well 10.

The silicon controlled rectifier is composed of an NPN bipolar transistor Q2 having the first diffusion layer 12, the N-well 10 and the P-well 20 as emitter region, base region and collector region, respectively.

When an ESD current flows into the anode ANODE due to electrostatic discharge, NP junctions of the N-well 10 and the P-well 20 which are reverse-biased are broken down so that the PNP bipolar transistor Q1 and the NPN bipolar transistor Q2. ) Is turned on. At this time, the ESD current is discharged through the cathode (CATHODE) by the positive feedback (positive feedback) that the reverse biased NP junction acts like a forward biased junction. The voltage at which the reverse biased NP junction breaks down becomes the trigger voltage of the silicon controlled rectifier, and when the silicon controlled rectifier is triggered, the ESD current is instantaneously discharged by a strong snapback operation in which the voltage across the NP junction is rapidly lowered.

2 is a current-voltage graph showing the operation of a typical silicon controlled rectifier.

Referring to FIG. 2, when a voltage higher than the trigger voltage of the silicon controlled rectifier is applied to the anode by ESD, the silicon controlled rectifier is triggered and the voltage is drastically lowered by the snapback operation (section a). At this time, when the voltage drops to the hold voltage V H by the snapback operation, and a large amount of current larger than the hold current I H is supplied to the silicon controlled rectifier, the silicon controlled rectifier operates in a latch-up operation (section b). ), It can discharge large amount of ESD current in low impedance state. This low impedance state lasts until the voltage drops below hold (V H ) or decreases below hold current (I H ). Due to this characteristic, the silicon controlled rectifier is effective to act as an antistatic discharge device for the input / output pad to which a low voltage or pulse voltage is applied, but due to the low hold voltage (V H ) when applied to a power pad to which a constant voltage is applied. The ESD device itself can be destroyed.

The present invention is proposed to solve the above-mentioned problems, electrostatic discharge protection to ensure that the silicon controlled rectifier can be operated stably so that the trigger voltage of the silicon controlled rectifier is lower than the trigger voltage of the device constituting the internal circuit Suggest a device.

An electrostatic discharge protection device according to an embodiment of the present invention includes a first conductivity type region and a second conductivity type region formed on the substrate; A diffusion layer formed in the first conductivity type region and electrically connected to an anode; A diffusion layer formed in the second conductivity type region and electrically connected to the cathode; And a second conductivity type doped region positioned below the second conductivity type region.

The trigger voltage is adjusted by adjusting the distance between the second conductivity type doped region and the first conductivity type region.

By the electrostatic discharge protection device as proposed, there is an advantage that the trigger voltage can be adjusted in consideration of the operating voltage or the breakdown voltage of the internal circuit element.

And, by increasing the deep N-type doping region in the P-type well direction, there is an advantage that the distance between the anode and the cathode can be adjusted.

In addition, while controlling the distance between the P-type well and the deep N-type doped region, it is possible to adjust the trigger voltage of the electrostatic device.

Hereinafter, with reference to the accompanying drawings for the present embodiment will be described in detail. However, the scope of the idea of the present invention may be determined from the matters disclosed by the present embodiment, and the idea of the invention of the present embodiment may be performed by adding, deleting, or modifying components to the proposed embodiment. It will be said to include variations.

In the following description, the word 'comprising' does not exclude the presence of other elements or steps than those listed. In addition, in the accompanying drawings, the thickness thereof is enlarged in order to clearly express various layers and regions. In addition, the same reference numerals are used for similar parts throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only being another part "on top" but also having another part in the middle.

3 is a view showing the configuration of the electrostatic discharge protection device according to an embodiment of the present invention, Figure 4 is a current-voltage graph showing the operation of the silicon controlled rectifier according to the present embodiment.

Referring to FIG. 3, the silicon-controlled rectifier in the electrostatic discharge protection device of the present embodiment has a deep N-type well region formed in the semiconductor substrate 110, and a P-type well which is a first conductivity type region in the semiconductor substrate 110. 140 and N type wells 120 and 130 which are second conductivity type regions are formed.

A plurality of diffusion layers formed in the P-type well 140 are electrically connected to an anode, and a plurality of diffusion layers formed in the N-type wells 120 and 130 are electrically connected to a cathode. Hereinafter, the first conductivity type will be exemplified by P type, and the second conductivity type will be described by exemplifying N type.

In the N type wells 120 and 130 of the cathode region, a high concentration P-type first diffusion layer 121 and 131, a high concentration N-type second diffusion layer 122 and 132, and a high concentration P-type third diffusion layer 123 and 133 are formed near the substrate surface.

In the P-type well 140 of the anode region, a high concentration N-type fourth diffusion layer 141, a high concentration P-type fifth diffusion layer 142, and a high concentration N-type sixth diffusion layer 143 are formed near the substrate surface. do.

In addition, an isolation layer 150 for device isolation is formed on the semiconductor substrate 110, and a gate 160 is insulated from the substrate by a gate oxide film (not shown).

Meanwhile, according to the present exemplary embodiment, deep N-type doped regions 170 and 180 are formed in the N-type wells 120 and 130 of the cathode region. In particular, the deep N-type doped regions 170 and 180 have a deeper junction depth and a higher doping concentration than the N-type wells 120 and 130.

Because forming the deep N-type doped regions 170 and 180 can lower the junction breakdown voltage by adjusting the distance between the N-type wells 120 and 130 and the deep N-type doped regions 170 and 180. Because. Being able to adjust the junction breakdown voltage means that the trigger voltage can be adjusted in a silicon controlled rectifier.

In addition, by extending the deep N-type doped regions 170 and 180 in the direction of the P-type well 140 of the anode region, it is possible to control between the anode and the cathode. As such, by controlling the distance between the P-type well 140 and the deep N-type doped regions 170 and 180, the trigger voltage of the electrostatic device may be adjusted. As for the adjustment of such a trigger voltage, as shown in FIG. 4, the trigger voltage can be adjusted to the portion indicated by the arrow.

Since this method adds the deep N-type doped regions 170 and 180 in the structure of the existing electrostatic device, there is no need to perform additional mask fabrication or additional processes, so that additional costs for developing the electrostatic device are not excessive. Do not.

1 is a diagram showing an electrostatic discharge protection device using a general silicon controlled rectifier.

2 is a current-voltage graph showing the operation of a typical silicon controlled rectifier.

3 is a view showing the configuration of an electrostatic discharge protection device according to an embodiment of the present invention.

4 is a current-voltage graph showing the operation of the silicon controlled rectifier according to the present embodiment.

Claims (4)

A first conductivity type region and a second conductivity type region formed in the substrate; A diffusion layer formed in the first conductivity type region and electrically connected to an anode; A diffusion layer formed in the second conductivity type region and electrically connected to the cathode; And And a second conductivity type doped region located below the second conductivity type region. The method of claim 1, And a trigger voltage is adjusted by adjusting a distance between the second conductivity type doped region and the first conductivity type region. The method of claim 1, The first conductivity type is P type, the second conductivity type is N type, And wherein the second conductivity type doped region has a relatively higher doping concentration than the N type impurity of the second conductivity type region. The method of claim 1, The diffusion layer formed in the second conductivity type region includes a high concentration P-type first diffusion layer, a high concentration N-type second diffusion layer, and a high concentration P-type third diffusion layer.
KR1020090134180A 2009-12-30 2009-12-30 Electrostatic discharge pretection device KR20110077561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090134180A KR20110077561A (en) 2009-12-30 2009-12-30 Electrostatic discharge pretection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090134180A KR20110077561A (en) 2009-12-30 2009-12-30 Electrostatic discharge pretection device

Publications (1)

Publication Number Publication Date
KR20110077561A true KR20110077561A (en) 2011-07-07

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