KR20110076507A - Method for manufacturing buried gate electrode in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming the buried gate electrode of a semiconductor device is provided to reduce the value of a cell capacitance securing a bit-line sensing margin by forming a buried gate electrode without a parasitic capacitor. CONSTITUTION: A trench(115) is formed in the active region of a semiconductor substrate(100). The trench is buried with a gate electrode material. The gate electrode material is recessed to form a buried gate electrode which buries a part of the trench. An annealing process is implemented with respect to the semiconductor substrate under deuterium atmosphere in order to compensate damages generated on the upper side of the trench in the gate electrode material recessing process.

Description

Method for manufacturing buried gate electrode in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device manufacturing, and more particularly, to a buried gate electrode forming method of a semiconductor device.

As the degree of integration of semiconductor devices increases, design rules decrease, so that the size of gates of transistors constituting semiconductor devices decreases. As a result, the intensity of the electric field between the source region and the drain region is also increasing. As a result of the increased electric field strength, electrons are accelerated between the source region and the drain region to generate a large number of hot carriers that attack the gate insulating layer near the drain region. And such hot carriers are known to degrade the electrical properties of the device. In particular, in the case of semiconductor memory devices such as DRAMs, leakage currents occur as the strength of the electric field between the source region and the drain region increases, which adversely affects the refresh characteristic, which is one of the important characteristics of DRAM. Is interfering. In addition to these structural problems, as the distance between the source and drain regions narrows, the margin for punch-through also decreases, increasing the short channel effect and leakage current of the transistor. The problem is appearing.

In order to solve the problem caused by the reduction of the gate size of the transistor as described above, a recess gate for forming a gate overlapping with a trench formed in a semiconductor substrate has been proposed and applied. The recess gate may increase the effective channel length in comparison with a conventional planar type gate to reduce short channel effects and leakage current. However, the recess gate has a structure in which word lines and bit lines overlap, and word lines and bit lines are separated by word line spacers. Accordingly, there is a problem in that the parasitic capacitance value increases due to overlap of word lines and bit lines. If the parasitic capacitance value is increased, the cell capacitance value for securing the bit line sensing margin is decreased, thereby reducing the refresh characteristics of the semiconductor device. Accordingly, there is a need for a method capable of improving refresh characteristics of a semiconductor device while improving a problem caused by applying a recess gate.

An object of the present invention is to provide a method for forming a buried gate electrode of a semiconductor device capable of compensating for damage caused by plasma generated in the process of forming the buried gate electrode.

A buried gate electrode forming method of a semiconductor device according to the present invention includes forming a trench in an active region of a semiconductor substrate; Filling the trench with a gate electrode material; Recessing the gate electrode material to form a buried gate electrode partially filling the trench; And recovering damage generated on the trench in the process of recessing the gate electrode material by performing an annealing process on a semiconductor substrate in a deuterium (D2) atmosphere.

In the present invention, the filling of the gate electrode material may include a titanium nitride (TiN) single layer or a structure in which a tungsten film and titanium nitride are stacked (W / TiN).

Recessing the gate electrode material may include polishing the surface of the gate electrode material by a planarization process; And recessing the polished gate electrode material by an etch back process using plasma.

In the annealing process, the semiconductor substrate is disposed in the annealing equipment, and the decantation process is performed at a temperature of 400 ° C. to 500 ° C. while supplying deuterium (D2).

According to the present invention, a cell capacitance value for securing a bit line sensing margin can be reduced by forming a buried gate electrode in which parasitic capacitors are not formed as compared with the recess gate and the gate of the FIN structure.

In addition, by reducing the damage caused by the plasma generated in the process of forming the buried gate electrode using deuterium (D2) it can be improved to reduce the refresh time. In addition, by performing an annealing process at a low temperature, it is possible to prevent the characteristics of the device such as changing the threshold voltage.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

1 to 6 are cross-sectional views illustrating a method of forming a buried gate electrode of a semiconductor device.

Referring to FIG. 1, an isolation region 105 is formed in a semiconductor substrate 100 to define an active region 107. To this end, a device isolation trench is formed in the semiconductor substrate 100, and a device isolation layer 105 is formed by filling the device isolation trench with an insulating material. The device isolation layer 105 has a structure surrounding the active region 107. Next, a mask layer pattern 110 defining a region in which a gate is to be formed is formed on the semiconductor substrate 100. The mask layer pattern 110 is formed by applying a resist material on the semiconductor substrate 100, and performs a lithography process consisting of an exposure and development process. Then, a mask layer pattern 110 having an opening to selectively expose the surface of the semiconductor substrate 100 in the region where the gate is to be formed is formed. The mask film pattern 110 is formed in a line shape.

Referring to FIG. 2, the exposed portion of the semiconductor substrate 100 is etched using the mask layer pattern 110 (see FIG. 1) as an etch mask to form a trench 115 in the active region 107 (see FIG. 1) of the semiconductor substrate 100. ). Since the buried gate structure is applied to manufacturing a semiconductor device of 30 nm or less, the trench 115 is also formed in the device isolation layer 105 by etching the portion exposed by the mask layer pattern 110 formed in a line shape.

Referring to FIG. 3, the gate insulating layer 120 is formed on the exposed surface of the trench 115. The gate insulating layer 120 may be formed as an oxide film by performing an oxidation process including a thermal oxidation process or a radical oxidation process. Next, the gate electrode material 125 is deposited on the semiconductor substrate 100. The gate electrode material 125 is deposited to a thickness to fill all the trenches 115. The gate electrode material 125 has a metal material, for example, a titanium nitride (TiN) single layer or a structure in which a tungsten film and titanium nitride are stacked (W / TiN) instead of the polysilicon material that has been applied as a conventional electrode material. It is preferable to form.

Referring to FIG. 4, the gate electrode material 125 is recessed to form a buried gate electrode 125a that partially fills the trench 115. To this end, first, a planarization process is performed on the semiconductor substrate 100 on which the gate electrode material 125 is formed. The planarization process is a process of polishing the surface of the gate electrode material 125a to recess the gate electrode material 125a to a uniform thickness. Next, in the planarization process, the buried gate electrode 125a is recessed by a predetermined depth to form the buried gate electrode 125a. The recess process may proceed to an etch back process using plasma.

In the meantime, the plasma insulating damage (PID) of the gate insulating layer 120 of the upper portion A of the trench 115 is attacked by the plasma during the etchback process using the plasma. Occurs. The upper portion of the trench 115 is not a portion in which a channel is directly formed, but is a portion that can identify damage by plasma (PID). In addition, as the gate insulating layer 120 in the upper portion of the trench 115 remains less, the damage caused by plasma (PID) is more severe. When the gate insulating layer 120 is attacked by the plasma, the silicon (Si) lattice in the upper portion of the trench 115 is damaged and a dangling bond 122 is generated, resulting in an electron trap and a leakage current. The refresh time of the semiconductor device is reduced by causing a phenomenon such as the path of.

Damage due to plasma (PID) is caused as the charge density progresses unevenly on the surface of the gate insulating layer 120. In order to solve the non-uniform charge density on the surface of the gate insulating film 120, a current is generated from the higher charge density to the lower charge density. This current flows through the gate insulating layer 120 to apply electrical stress to the semiconductor device, causing a phenomenon such as a path of an electron trap and a leakage current. Therefore, the refresh time can be secured by reducing the damage caused by plasma (PID), but it occurs as the etch back process proceeds. In order to improve the damage caused by plasma (PID) generated on the gate insulating layer 120 of the upper portion of the trench 115, a method of performing an annealing process at a high temperature, for example, 700 ° C to 800 ° C has been proposed. . However, when the annealing process is performed at a high temperature of 700 ° C. or higher, the threshold voltage of the transistor is changed.

Referring to FIG. 5, an annealing process is performed on a semiconductor substrate 100 in a deuterium / heavy hydrogen (D2) atmosphere to recover a portion of the plasma generated damage (PID). Specifically, the semiconductor substrate 100 is disposed in the anneal equipment, and deuterium D2 is supplied into the anneal equipment. The annealing process is performed for 2 hours while supplying deuterium (D2) and maintaining the temperature inside the anneal equipment at a temperature of 400 ° C to 500 ° C, preferably 450 ° C. When the annealing process is performed, the silicon (Si) lattice of the upper portion of the trench 115 is damaged by the attack by plasma, and hydrogen is bonded to the dangling bond to form a Si-H bond structure, thereby recovering the damaged portion. do.

On the other hand, the annealing process using hard hydrogen (H ₂ ) is generally carried out at a temperature of 700 ℃ to 800 ℃. In this case, even if hydrogen bonds to the unbonded portion of silicon to form a Si-H bond structure, it is dissociated during subsequent heat treatment and the bond is broken again. This is because dissociation is easier than deuterium during heat treatment due to the characteristic of light hydrogen having a mass number smaller than deuterium. Therefore, it is preferable to perform annealing process using deuterium rather than hard hydrogen. In addition, deuterium (D2) can recover the damage by the plasma at a low temperature, such as 400 ℃ to 500 ℃ compared to the conventional light hydrogen (H ₂ ). Accordingly, the annealing process may be performed at a high temperature, for example, 700 ° C. or higher, thereby preventing the problem of changing the threshold voltage of the transistor.

Referring to FIG. 6, an interlayer insulating layer 130 filling the exposed portion of the buried gate electrode 125a and the trench 115 is formed. On the other hand, although not shown in the figure, source and drain regions formed by implanting impurity ions are disposed to the left and right of the buried gate electrode 125a.

In the case of the buried gate electrode 125a, the entire gate line is formed inside the semiconductor substrate 100 as compared with the recess gate formed overlapping the trench and the gate of the FIN structure having the protrusion formed on the bottom surface of the trench. Accordingly, since parasitic capacitors are not formed in comparison with the gates of the recess gate and the FIN structure, there is an advantage that the cell capacitance value for securing the bit line sensing margin can be reduced. By reducing the damage caused by plasma generated in forming the buried gate electrode 125a by performing an annealing process in a deuterium (D2) atmosphere, the refresh time can be reduced. In addition, by performing the annealing process at a low temperature, it is possible to prevent the characteristics of the device such as the threshold voltage is changed.

1 to 6 are cross-sectional views illustrating a method of forming a buried gate electrode of a semiconductor device.

Claims (4)

Forming a trench in an active region of the semiconductor substrate; Filling the trench with a gate electrode material; Recessing the gate electrode material to form a buried gate electrode partially filling the trench; And And recovering damage generated on the trench in the process of recessing the gate electrode material by performing an annealing process on the semiconductor substrate in a deuterium (D2) atmosphere. The method of claim 1, The embedding of the gate electrode material may include a titanium nitride (TiN) single layer or a tungsten film and a titanium nitride stacked structure (W / TiN). The method of claim 1, wherein the recessing of the gate electrode material comprises: Polishing the surface of the gate electrode material by a planarization process; And And recessing the polished gate electrode material by an etch back process using a plasma. The method of claim 1, In the annealing process, the semiconductor substrate is disposed in an annealing equipment, and the buried gate electrode forming method of the semiconductor device proceeds at a temperature of 400 ℃ to 500 ℃ supplying deuterium (D2) to the annealing equipment.

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