KR20110068653A - Display panel device - Google Patents

Abstract

PURPOSE: A display device is provided to form first and second metal layers on a gate line to realize a plurality of parallel resistors, thereby lowering the resistance of the gate line. CONSTITUTION: A substrate includes a pixel area and a non pixel area. A gate line(120a) and a data line are formed on the non pixel area and cross each other. A gate insulating film is formed on a substrate on which the gate line is formed. A first metal layer(140b) is formed in a part of the gate insulating film where the first metal layer is overlapped with the gate line. A passivation film(150) is formed on the frontal surface of a substrate on which at least one first metal layer is formed. A second metal layer is formed on a part of the passivation film to overlap the gate line with the first metal layer.

Description

Display device {Display Panel Device}

The present invention relates to a display device, and more particularly, to a display device capable of lowering a resistance of a gate line.

Recently, the importance of the flat panel display (FPD) has increased with the development of multimedia. In response, Liquid Crystal Display (LCD), Plasma Display Panel (PDP), Field Emission Display (FED), Organic Light Emitting Diode Display Device Various displays such as and the like have been put to practical use.

Among them, the liquid crystal display device has a tendency that its application range is gradually widening due to features such as light weight, thinness, low power consumption driving, and the like. In addition, the organic light emitting display device has a high response time with a response speed of 1 ms or less, low power consumption, and self-illumination.

The liquid crystal display and the organic light emitting display are driven by a passive matrix method and an active matrix method using a thin film transistor. The active matrix method is a method in which a thin film transistor is connected to each pixel electrode and driven according to a voltage maintained by a capacitor capacitance connected to a gate electrode of the thin film transistor.

In a conventional active matrix display using a thin film transistor, a signal is supplied by a gate line and a data line for supplying a scan signal and a data signal to each pixel, and can emit light by a power supply line for supplying power to each pixel.

In such an active matrix display device, in order to improve electrical characteristics, the semiconductor layer is crystallized by using an indirect thermal crystallization (ITC) process. However, the high temperature heat generated during the ITC process induces thermal deformation during the expansion / contraction of the gate metal, which causes the gate insulating layer to crack. The cracks in the gate insulating layer usually occur at the gate metal edges so that the source / drain is shorted and prevents the driving of the thin film transistor. In order to solve this problem, there is a method of resolving cracks in the gate insulating layer by thinly depositing a gate metal and relieving thermal deformation, but according to this method, another problem of increasing resistance of the gate line occurs. In addition, in order to solve the problem of increasing the resistance of the gate line, a wiring pattern is deposited using the metal of the source / drain layer on the gate line, and the gate pattern formed of ITO and the wiring pattern formed of the source / drain metal contact each other. It is possible to consider using a parallel resistance method in which the resistance of the gate line is lowered by forming the parallel resistance.

However, when designing each pixel constituting the active matrix display device, since the vertical direction is designed to be longer than the horizontal direction, the space for forming the source / drain pattern on the gate line is limited. In other words, when the plurality of parallel gate structures are used, the effect of lowering the wiring resistance is great. However, in the conventional active matrix display device, it is difficult to form the plurality of parallel gate structures due to space limitations.

Accordingly, an object of the present invention is to solve the above-described problems, and to provide a display device capable of preventing damage to the gate insulating film and lowering wiring resistance by using a plurality of parallel gate structures.

In order to achieve the above object, in the display device according to the exemplary embodiment, subpixels of the same color are arranged along a horizontal direction, and subpixels of different colors are constant along a vertical direction crossing the horizontal direction. A display device comprising a pixel array repeatedly arranged in sequence, comprising: a substrate having a pixel area and a non-pixel area; A gate line and a data line formed in the non-pixel area on the substrate and disposed to cross each other; A gate insulating film formed on the substrate on which the gate line is formed; At least one first metal layer formed in a region overlapping with the gate line on a portion of the gate insulating layer; A passivation film formed on an entire surface of the substrate on which the at least one first metal layer is formed; And at least one second metal layer formed on a portion of the passivation film so as to overlap the gate line and the first metal layer, and in contact with the gate line and the at least one first metal layer. do.

In the above configuration, the second metal layer is configured to contact the gate line through a first contact hole and a second contact hole penetrating the gate insulating film and the passivation film.

In addition, the first metal layer contacts the second metal layer through third and fourth contact holes penetrating the first contact hole, the second contact hole, and the passivation layer.

The third contact hole and the fourth contact hole are configured to be positioned between the first contact hole and the second contact hole.

In addition, the gate line is electrically connected to the first metal layer through the second metal layer.

In addition, the pixel area on the substrate may include a gate electrode formed on the same layer as the gate line; A semiconductor layer formed on the gate insulating film; A source electrode and a drain electrode formed on the semiconductor layer; And a pixel electrode connected to the drain electrode.

In addition, the source electrode and the drain electrode are made of the same material as the first metal layer, and the pixel electrode is made of the same material as the second metal layer.

In addition, a buffer layer formed between the substrate and the gate line may be further included.

According to the display device according to the exemplary embodiment of the present invention, the first and second metal layers may be formed on the gate line to implement a plurality of parallel resistors, thereby reducing the overall resistance of the gate line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 1 to 4. 1 is an equivalent circuit diagram illustrating a pixel array of a display device according to an exemplary embodiment of the present invention. FIG. 2 is a plan view showing a structure of one pixel of the display device shown in FIG. 1, and FIG. 4A to 4E are cross-sectional views illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a pixel array of a display device according to an exemplary embodiment of the present invention is defined by the intersection of gate lines D1 to D6 and gate lines G1 to G6. In this pixel array, each of the red subpixel R, the green subpixel G, and the blue subpixel B are disposed along the line direction. In the pixel array illustrated in FIG. 1, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels G in a column direction. Each TFT includes a pixel electrode of a liquid crystal cell in which data voltages from the data lines D1 to D6 are disposed on the right side of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G6. To feed. In a pixel array according to an exemplary embodiment of the present invention, when the resolution is m × n, m data lines and 3n gate lines are required, and each of the gate lines of the pixel array has 1/3 horizontal level synchronized with the data voltage. The gate pulses of the period are supplied sequentially. Accordingly, the pixel array structure according to the embodiment of the present invention is compared with the conventional pixel array structure in which each of the red subpixel R, the green subpixel G, and the blue subpixel B are disposed along the column direction. The number of gate lines increases and the number of data lines decreases. As a result, sufficient space for forming a source / drain pattern on the gate line is secured.

Hereinafter, a display device according to an exemplary embodiment of the present invention having a parallel gate structure will be described in detail with reference to FIGS. 2 and 3. 2 is a plan view illustrating a 1 pixel structure of the display device according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along the line II ′ of FIG. 2.

2 and 3, a display device according to an exemplary embodiment of the present invention includes a substrate 110 including a pixel area PA and a non-pixel area NPA, and a non-pixel area on the substrate 110. The gate line 120a and the data line 140a arranged in a matrix form on the NPA, the switching thin film transistor T1, the driving thin film transistor T2, and the capacitor (T1) formed in the pixel area PA on the substrate 110. Cst) and the pixel electrode 162. The driving thin film transistor T2 includes a gate electrode 120b, a semiconductor layer 130, a source electrode 140d, and a drain electrode 140e, and the pixel electrode 162 is electrically connected to the drain electrode 140e. have.

In addition to the gate line 120a and the data line 140a, the power line 140c is formed in the non-pixel area NPA. In particular, on the gate line 120a, the first resistor R1 includes the first metal layer 140b and the second metal layer 160a, and the third metal layer 141b and the fourth metal layer 161a. A second resistor R2 is formed, and these first and second resistors R1 and R2 are configured to be connected in parallel with the gate line 120a, respectively.

The structure of the present invention will be described in more detail with reference to FIGS. 2 and 3. First, the buffer layer 115 is formed on the entire surface of the substrate 110. The gate line 120a is formed on the buffer layer 115 of the non-pixel region NPA, and the gate electrode is formed on the buffer layer 115 of the pixel region PA. 120b are formed respectively.

The gate insulating layer 125 is formed on the entire surface of the substrate 110 on which the gate line 120a and the gate electrode 120b are formed. The data line 140a, the first-first metal layer 140b, the first-second metal layer 141b, and the power line 140c are spaced apart from each other on the same layer on the gate insulating layer 125 of the non-pixel region NPA. The semiconductor layer 130, the etch stopper 135, the ohmic layer 137, the source electrode 140d and the drain electrode 140e are sequentially formed on the gate insulating layer 125 of the pixel area PA. Configure the transistor.

Next, a passivation film 150 is formed on the entire surface of the substrate 110. In addition, the passivation layer 150 may expose the first contact hole 155a, the second contact hole 155b, the third contact hole 156a, and the fourth contact to expose the gate line 120a of the non-pixel region NPA. The hole 156b is formed, the fifth contact hole 155c and the sixth contact hole 155d are formed to expose the first-first metal layer 140b, and the second metal layer 141b is exposed. The seventh contact hole 156c and the eighth contact hole 156d are formed. In addition, a ninth contact hole 157 is formed to expose the drain electrode 140e of the pixel area PA.

The first contact hole 155a of the non-pixel region NPA is formed on the passivation layer 150 on which the first to ninth contact holes 155a, 155b, 156a, 156b, 155c, 155d, 156c, 156d, and 157 are formed. Contacting the gate line 120a through the second contact hole 155b, and contacting the first-first metal layer 140b through the fifth contact hole 155c and the sixth contact hole 155d. The metal layer 160a is formed, contacts the gate line 120a through the third contact hole 156a and the fourth contact hole 156b, and opens the seventh contact hole 156c and the eighth contact hole 156d. The second-second metal layer 161a is formed to contact the first-second metal layer 141b through the pixel electrode, and the second-second metal layer 161a contacts the drain electrode 140e through the ninth contact hole 157 of the pixel area PA. 162 is formed.

According to the structure of the display device according to the exemplary embodiment as described above, the first-first metal layer 140b, the second-first metal layer 160a, and the first-second metal layer 141b in the non-pixel area NPA. And since the second-2 metal layer 16xa is formed to achieve a plurality of parallel resistance structures with the gate line 120a, the resistance of the gate line 120a may be lowered.

Next, a method of manufacturing a display device according to an exemplary embodiment of the present invention having the above-described structure will be described with reference to FIGS. 4A to 4E.

4A through 4E are cross-sectional views illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention.

First, referring to FIG. 4A, a buffer layer 215 is formed on a substrate 210 made of glass, plastic, or metal. The buffer layer 215 is formed to protect the thin film transistor formed in a subsequent process from impurities such as alkali ions flowing out of the substrate 210, and selectively using silicon oxide (SiO 2), silicon nitride (SiN x), or the like. Can be formed.

Next, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) on the substrate 210 including the buffer layer 215. The gate line 220a is formed in the non-pixel region NPA, and the gate electrode 220b is formed in the pixel region PA by stacking and patterning any one selected from the group consisting of these alloys.

In this case, the gate line 220a and the gate electrode 220b may have a thickness of 100 μs to 1000 μs. If the thickness of the gate line 220a and the gate electrode 220b is 100 kPa or more, the resistance of the gate line 220a can be prevented from increasing, and if the thickness of the gate line 220a and the gate electrode 220b is 1000 kPa or less, In the crystallization process of the semiconductor layer, thermal deformation between the gate electrode 220b and the gate insulating layer may be prevented.

Next, a silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is stacked on the substrate 210 including the gate line 220a and the gate electrode 220b to form a gate insulating film 225. The gate insulating layer 225 may be formed of a single layer of silicon oxide (SiO ₂ ) or silicon nitride (SiNx) or a mixed layer thereof.

Referring to FIG. 4B, an amorphous silicon film 231, an etch stopper film 232, and a thermal transition film 233 are sequentially stacked on the pixel area PA on which the gate electrode 220b and the gate insulating film 225 are formed. do.

The etch stopper layer 232 may be formed of silicon oxide (SiO 2) or silicon nitride (SiN x). In addition, the thermal transition film 233 is a transition metal, for example, in the group consisting of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh and Pt. Any one selected may be laminated.

Next, the amorphous silicon film 231 is crystallized into a polycrystalline silicon film by irradiating a laser onto the heat transfer film 233 using the infrared laser device 240. In this case, in the thermal transition film 233 to which the laser is irradiated, the above-described transition metal may be transferred to the amorphous silicon film 231 through the lower etch stopper film 232. The transition metal transferred to the amorphous silicon film 231 serves as a seed of the amorphous silicon film 231 to crystallize the amorphous silicon film 231 into a polycrystalline silicon film at high heat. Particularly, in the conventional crystallization process of irradiating a laser, damage of the gate insulating film occurs due to a difference in thermal expansion rate between the gate insulating film and the gate electrode due to the high heat of the laser. Thus, damage to the gate insulating film can be prevented.

Referring to FIG. 4C, after the crystallization process is finished, the heat transfer film 233 is removed, and the polycrystalline silicon film and the etch stopper film 232 are patterned to form the semiconductor layer 250 and the etch stopper 255.

Referring to FIG. 4D, an ohmic layer 257 is formed in the pixel area PA in which the etch stopper 255 and the semiconductor layer 250 are formed. The ohmic layer 257 is for ohmic contact between the source electrode, the drain electrode, and the semiconductor layer 250, and may be formed by doping n + impurities to amorphous silicon.

Next, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) on the substrate 210 on which the ohmic layer 257 is formed. After stacking any one or an alloy thereof selected from the group consisting of: and patterning, the data line 260a, the first-first metal layer 260b, the first-second metal layer 261b, and the power source in the non-pixel region NPA. A line 260c is formed, and a source electrode 260d and a drain electrode 260e are formed in the pixel area PA. In this process, a thin film transistor including a gate electrode 220b, a semiconductor layer 250, a source electrode 260d, and a drain electrode 260e is formed in the pixel area PA.

Referring to FIG. 4E, polyimide may be formed on the substrate 210 on which the data line 260a, the first metal layer 260b, the power line 260c, the source electrode 260d, and the drain electrode 260e are formed. A passivation film 270 is formed by coating an inorganic material such as spin on glass (SOG), which is coated with an organic material such as benzocyclobutene series resin, acrylate, or silicon oxide in a liquid form and then cured. do.

Next, the passivation layer 270 and the gate insulating layer 225 are etched to expose the gate line 220a of the non-pixel region NPA, so as to expose the first contact hole 275a, the second contact hole 275b, and the third. The contact hole 276a and the fourth contact hole 276b are formed, and the passivation film 270 is etched to expose the first-first metal layer 260b to form the fifth contact hole 275c and the sixth contact hole 275d. ) And the passivation film 270 is etched to expose the 1-2 metal layer 261b to form a seventh contact hole 276c and an eighth contact hole 276d. In addition, the passivation layer 270 is etched to expose the drain electrode 260e of the pixel area PA to form a ninth contact hole 277. Such first to ninth contact holes 275a, 275b, 276a, 276b, 275c, 275d, 276c, 276d, and 277 may be simultaneously formed using one mask.

Subsequently, a transparent conductive film, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is laminated and patterned on the substrate 210 on which the passivation film 270 is formed, thereby forming the 2-1 metal layer in the non-pixel region NPA. 280a and the second-second metal layer 281a are formed, and the pixel electrode 282 is formed in the pixel area PA.

In the pixel area PA, the pixel electrode 282 is in contact with the drain electrode 260e through the ninth contact hole 277 penetrating the passivation layer 270. Also, in the non-pixel region NPA, the second-first metal layer 280a is formed through the first contact hole 275a and the second contact hole 275b that pass through the passivation layer 270 and the gate insulating layer 225. Contacting the gate line 220a, the second-second metal layer 281a contacts the gate line 220a through the third contact hole 276a and the fourth contact hole 276b, and the passivation layer 270. Through the fifth contact hole 275c and the sixth contact hole 275d penetrating through, the second-first metal layer 280a contacts the first-first metal layer 260b, and the seventh contact hole 276c and The second-second metal layer 281a contacts the first-second metal layer 261b through the eighth contact hole 276d.

In particular, the 2-1 metal layer 280a contacts the gate line 220a while simultaneously contacting the 1-1 metal layer 260b in the first contact hole 275a and the second contact hole 275b. The −2 metal layer 281a is in contact with the first and second metal layers 261b in the third and fourth contact holes 276a and 276b and simultaneously with the gate line 220a. Accordingly, the first-first metal layer 260b and the gate line 220a are electrically connected to each other through the second-first metal layer 280a, and the first-second metal layer 261b through the second-second metal layer 281a. And gate line 220a are electrically connected to each other. As a result, the gate line 220a and the first-first metal layer 260b form a parallel resistor R1 through the second-first metal layer 280a, and the gate line 220a and the first-second metal layer 261b. Since the parallel resistor R2 is formed through the second-2-2 metal layer 281a, a plurality of parallel resistors are formed.

In the embodiment of the present invention, the fifth contact hole 275c and the sixth contact hole 275d are located between the first contact hole 275a and the second contact hole 275b, and the seventh contact hole 276c and The eighth contact hole 276d has been described as being located between the third contact hole 276a and the second contact hole 276b. Although the first contact hole 275a and the second contact hole 275b may be located between the fifth contact hole 275c and the fifth contact hole 275d, the first-first metal layer 260b may be formed of the first contact hole 275c and the second contact hole 275b. The first contact hole 275a and the second contact hole 275b are patterned to shorten the length of the first-first metal layer 260b. Therefore, since the length of the parallel resistor is shortened, the effect of lowering the resistance is reduced, so that the fifth contact hole 275c and the sixth contact hole 275d are disposed between the first contact hole 275a and the second contact hole 275b. Preferably located. For the same reason, it is preferable that the seventh contact hole 276c and the fourth contact hole 276d are located between the third contact hole 276a and the fourth contact hole 276b.

The display device according to the exemplary embodiment of the present invention manufactured as described above has an advantage of preventing the gate insulating layer from being damaged during the crystallization process of the semiconductor layer by reducing the thickness of the gate electrode. In addition, since the thickness of the gate electrode and the gate line is reduced, the resistance of the gate line is increased by forming the first metal layer and the second metal layer in the gate line to implement a plurality of parallel resistors, thereby reducing the resistance of the gate line.

Hereinafter, the resistance reduction effect of the gate line obtained by the display device manufactured according to the embodiment of the present invention will be described.

Table 1 shows the resistance value for each pixel (unit pixel) when the parallel gate structure is formed in each pixel of the display device according to the embodiment of the present invention, and the resistance value in the gate structure in the conventional pixel structure. Tables comparing these. For convenience of description, the embodiment has been described taking the case of one parallel resistor as an example, but this is only to illustrate one example and the present invention is not limited thereto.

domain Mo resistivity ρ (Ω / ㎛) Gate line thickness H (µm) Thickness H of the 1-1st metal layer (μm) Line width W (㎛) Length L (㎛) Resistance (Ω) = ρL / (HW) Parallel integrated resistor (Ω) Sub pixel resistance (Ω) Unit pixel resistance (Ω) Conventional example Serial 0.15 0.1 - 5 240 72 - 72 72 Example 1

Series resistance 0.15 0.1 - 5 120 15 -
38.25
38.25 Parallel resistance 0.15 - 0.1 5 30 9 2.25 0.15 - 0.1 5 30 9 0.15 - 0.1 5 30 9 0.15 - 0.1 5 30 9

As can be seen from Table 1, in the pixel structure according to the conventional display device, the series resistance is calculated according to the following equation.

Resistance (Ω) = ρL / (HW)

In Equation 1, ρ represents a specific resistance value (Ω / μm) of a material used as a gate line, and in the case of molybdenum, the value is 0.15Ω / μm. L represents the length of the gate line (占 퐉), H represents the thickness of the gate line (占 퐉), and W represents the line width (占 퐉) of the gate line.

When the resistance value is calculated according to Table 1, the resistance (Ω) is calculated as 0.15 × 240 / (0.1 × 5) = 72Ω.

Next, in the pixel structure according to the exemplary embodiment of the present invention, the resistance value is obtained by the sum of the series resistance of the gate line 220a and the resistance of the first metal layer. In the present invention, the gate line length of the series resistance component is 120 mu m, and the parallel resistance component is composed of four 30 mu m lengths. First, calculating the series resistance component calculates 0.15 x 120 / (0.1 x 5) = 36 Ω. Next, when the parallel resistance components are calculated, the same values of 9Ω are obtained by calculating the four parallel resistance components R1, R2, R3, and R4 according to the above equation (1). In addition, these parallel resistance values are calculated | required by following formula (2).

1 / R = 1 / R1 + 1 / R2 + 1 / R3 + 1 / R4

Substituting the value of 9Ω of each parallel resistance component into the above Equation 2 yields the total parallel resistance R = 1 / (1/9 + 1/9 + 1/9 + 1/9) = 9/4 = 2.25Ω.

Therefore, the total resistance of the pixel structure according to the exemplary embodiment of the present invention is 38.25Ω, which is the sum of the series resistance component 36Ω and the parallel resistance component 2.25Ω.

As can be seen from the above calculation result, according to the parallel gate structure according to the embodiment of the present invention, since the resistance value of the gate line at the same line width and length is reduced from 72Ω to 38.25Ω, the resistance value is about 46.9%. An improved effect can be obtained. In the above description, the case where one parallel resistance is one example, but when two or more parallel resistances are formed, it can be seen that the resistance value can be further improved through the above description.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. For example, in the description of the embodiment of the present invention, the first-first and second-second metal layers (ie, two first metal layers) and the second-first and second-second metal layers (ie, two second layers) are disposed on the gate lines. Forming two parallel resistors by forming a metal layer) is described. However, three or more first metal layers and two second metal layers may be formed to further lower the overall resistance of the gate line. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

1 is an equivalent circuit diagram illustrating a pixel array of a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a plan view illustrating a structure of one pixel of the display device illustrated in FIG. 1. FIG.

3 is a cross-sectional view taken along the line II ′ of 2.

4A to 4E are diagrams illustrating processes for manufacturing a display device according to an exemplary embodiment of the present invention.

Description of the Related Art

110 substrate 115 buffer layer

120a: gate line 125: gate insulating film

130: semiconductor layer 140a: data line

140b: first metal layer 140c: power line

150: passivation film

155a, 155b, 155c, 155d, 155e: contact hole

160a: second metal layer 162: pixel electrode

Claims (8)

A display device comprising a pixel array in which subpixels of the same color are arranged along a horizontal direction, and subpixels of different colors are repeatedly arranged in a predetermined order in a vertical direction crossing the horizontal direction. A substrate having a pixel region and a nonpixel region; A gate line and a data line formed in the non-pixel area on the substrate and disposed to cross each other; A gate insulating film formed on the substrate on which the gate line is formed; At least one first metal layer formed in a region overlapping with the gate line on a portion of the gate insulating layer; A passivation film formed on an entire surface of the substrate on which the at least one first metal layer is formed; And And at least one second metal layer formed on a portion of the passivation layer to overlap the gate line and the first metal layer and in contact with the gate line and the at least one first metal layer. The method of claim 1, And the second metal layer is in contact with the gate line through a first contact hole and a second contact hole penetrating the gate insulating layer and the passivation layer. The method of claim 2, And the first metal layer is in contact with the second metal layer through a third contact hole and a fourth contact hole penetrating through the first contact hole, the second contact hole, and the passivation layer. The method of claim 3, wherein And the third contact hole and the fourth contact hole are located between the first contact hole and the second contact hole. The method of claim 1, And the gate line is electrically connected to the first metal layer through the second metal layer. The method of claim 1, In the pixel region on the substrate, A gate electrode formed on the same layer as the gate line; A semiconductor layer formed on the gate insulating film; A source electrode and a drain electrode formed on the semiconductor layer; And And a pixel electrode connected to the drain electrode. The method of claim 6, And the source electrode and the drain electrode are made of the same material as the first metal layer, and the pixel electrode is made of the same material as the second metal layer. The method of claim 1, And a buffer layer formed between the substrate and the gate line.

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