KR20110057062A - Middle and small sized liquid crystal display device and fabrication method of the same - Google Patents

Abstract

PURPOSE: A medium-sized liquid crystal display device and manufacturing method thereof are provided to increase aperture ratio and electrostatic capacity and to increase the reliability of a manufacturing process. CONSTITUTION: A thin film transistor is formed in a first area of a first substrate(10). A storage capacitor is formed in a second area of the first substrate. A first electrode and a second electrode of the storage capacitor are formed into a transparent conductive material. A pixel electrode is formed on the second area that is overlapped with the first electrode and the second electrode.

Description

Small and small sized liquid crystal display device and fabrication method of the same}

Embodiments of the present invention relate to a small and medium-sized liquid crystal display device and a manufacturing method thereof. More specifically, embodiments of the present invention relate to a small to medium sized liquid crystal display device capable of realizing an image and having a size smaller than a notebook size and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. Such a liquid crystal display device drives a liquid crystal by controlling an electric field between a pixel electrode and a common electrode disposed to face each other on a lower substrate having a thin film transistor and an upper substrate having a color filter.

To this end, the liquid crystal display includes a lower substrate and an upper substrate bonded to each other, a spacer for maintaining a constant cell gap between the lower substrate and the upper substrate, and a liquid crystal filled in the cell gap.

The upper substrate includes a color filter for color implementation, a black matrix for preventing light leakage, a common electrode for controlling an electric field, and an alignment layer coated for liquid crystal alignment. The lower substrate is composed of a plurality of signal wirings and a thin film transistor, a pixel electrode connected to the thin film transistor, and an alignment film coated for liquid crystal alignment. In addition, the lower substrate further includes a storage capacitor such that the pixel voltage signal charged in the pixel electrode is stably maintained until the next voltage signal is charged.

The storage capacitor is formed by overlapping the storage lower electrode and the storage upper electrode with an insulating layer therebetween. Here, the storage capacitor requires a large capacitance value so that the pixel capacitor can stably maintain the pixel voltage signal and can be applied to high resolution. However, when the overlapping area of the storage upper / lower electrodes is increased to increase the capacity of the storage capacitor, the opening ratio may be reduced by the area occupied by the upper / lower electrodes.

Meanwhile, the PVA mode (Patterned Vertical Alignment mode), which is a kind of VA mode liquid crystal display device, among the operating modes of the liquid crystal display device, forms liquid crystal domains by arranging liquid crystal molecules in different directions using patterned transparent electrodes. The viewing angle of the display device can be improved. In this case, in order to manufacture the liquid crystal display of the PVA mode, a process of forming the patterned transparent electrode must be accompanied.

In another embodiment of the PVA mode, a projection may be formed on an opposing substrate, and a liquid crystal domain may be formed by forming a common electrode layer on the substrate on which the projection is formed, thereby improving a viewing angle of the liquid crystal display. In this case, however, a separate process for forming the protrusions must also be involved.

As described above, in order to form the liquid crystal domain of the liquid crystal display, the process of patterning the transparent electrode and / or the process of forming the protrusions must be further performed, thus increasing the number of manufacturing processes of the liquid crystal display. In addition, the misalignment of the display substrate and the opposing substrate in the assembly process of the display substrate and the opposing substrate leads to misalignment of patterns of the pixel electrode of the display substrate and the common electrode of the opposing substrate to form a normal liquid crystal domain. can not do. In addition, the patterning of the transparent electrode and the formation of the projections are factors that lower the aperture ratio of the liquid crystal display device.

Embodiments of the present invention provide a small and medium size liquid crystal display device which improves the aperture ratio and the capacitance.

Embodiments of the present invention provide a method for manufacturing the small and medium liquid crystal display device.

According to embodiments of the present invention, a small and medium sized liquid crystal display device may include a first substrate; A thin film transistor formed in a first region of the first substrate; A storage capacitor is formed in the second region of the first substrate, and the first electrode and the second electrode of the storage capacitor are formed of a transparent conductive material.

In addition, a pixel electrode is further formed on a second region overlapping the first and second electrodes of the storage capacitor, and includes a domain including an embedding pattern for forming a liquid crystal domain between the second electrode and the pixel electrode of the storage capacitor. Formation layer is formed.

In addition, a second substrate including a common electrode formed on the front surface facing the first substrate; A liquid crystal layer is disposed between the first substrate and the second substrate and has a reactive mesogen (RM) that fixes liquid crystal molecules forming a liquid crystal domain.

The thin film transistor includes a gate electrode, a source electrode and a drain electrode formed with the gate electrode and the insulating layer interposed therebetween, and the gate electrode is formed on the same layer as the first electrode. The gate electrode is implemented with a laminated structure of a transparent conductive material and a low resistance metal.

 In addition, the drain electrode is formed to overlap a portion of the second electrode so that the second electrode and the drain electrode are electrically connected, and a contact electrode is further formed on an area of the second electrode exposed by the embedding pattern. Is formed.

In addition, the contact electrode is formed of the same material as the source electrode and the drain electrode of the thin film transistor, the transparent conductive material is Indium Tin Oxide (ITO), Tin Oxide (TO), Indium Zinc Oxide (Indium Zinc Oxide; IZO) and Indium Tin Zinc Oxide (ITZO).

In addition, a method of manufacturing a liquid crystal display according to an embodiment of the present invention includes forming a gate electrode of a thin film transistor and a first electrode of a storage capacitor on a first substrate; Forming a second electrode of a storage capacitor on a first insulating layer overlapping the first electrode; Forming a second insulating layer and a domain forming layer on which a recessed pattern exposing a portion of the second electrode is formed; And forming a pixel electrode on the domain forming layer overlapping the second electrode, wherein the first electrode and the second electrode of the storage capacitor are formed of a transparent conductive material.

The method may further include: positioning a second substrate including a common electrode on a front surface facing the first substrate; The method may further include forming a liquid crystal layer having a reactive mesogen (RM) positioned between the first substrate and the second substrate and fixing liquid crystal molecules implementing the liquid crystal domain.

In addition, the gate electrode and the first electrode are implemented on the same layer using a halftone mask process, and the gate electrode is formed of a laminated structure of a transparent conductive material and a low resistance metal.

The method may further include forming a semiconductor layer on or below the gate electrode; The method may further include forming source and drain electrodes electrically connected to the semiconductor layer, and forming a contact electrode on an area of the second electrode exposed by the embedding pattern.

Here, the contact electrode is formed of the same material as the source electrode and the drain electrode of the thin film transistor.

In accordance with another aspect of the present invention, a small to medium size liquid crystal display device includes a thin film transistor positioned in a non-transmissive region, a storage capacitor including a transparent first electrode, a dielectric layer, and a transparent second electrode sequentially disposed in a transmissive region. A first substrate; A second substrate facing the second substrate and including a common electrode; And a liquid crystal layer positioned between the first substrate and the second substrate, wherein the transmission region is defined as a region where the pixel electrode and the common electrode overlap.

In addition, the pixel electrode includes a transparent conductive material, and overlaps at least one of the first electrode and the second electrode to form a capacitance with the storage capacitor.

The display apparatus may further include a backlight disposed below the first substrate, and the transmittance of light incident from the backlight and passing through the first substrate, the liquid crystal layer, and the second substrate in the transmission region may be 80% to 99.5. %, And the dielectric film is composed of a film including at least one selected from the group consisting of silicon nitride and silicon oxide.

In addition, the thickness of the first electrode is 150 kPa to 1500 kPa, the thickness of the insulating film is 400 kPa to 6000 kPa, and the thickness of the second electrode is 150 kPa to 1500 kPa.

The liquid crystal display device of claim 21, wherein at least one of the first electrode and the second electrode extends outside the transmission area, and the liquid crystal display device is a medium-sized liquid crystal display device that is 11 inches or less.

According to embodiments of the present invention, the lower electrode and the upper electrode of the storage capacitor may be formed of a transparent conductive material so as to have a width corresponding to the entire transmissive region P of the pixel. Can be secured.

In addition, the liquid crystal domain may be formed without a separate pattern on the common electrode, thereby improving reliability of the manufacturing process by eliminating the cause of the misalignment of the upper and lower plates of the liquid crystal display. Furthermore, the manufacturing process may be simplified by omitting a separate patterning process for forming a pattern on the common electrode. Accordingly, productivity and display quality of the display device can be improved.

1 is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is a plan view of a liquid crystal display according to another exemplary embodiment of the present invention.
3A is a cross-sectional view taken along the line II ′ of FIG. 2.
3B is a cross-sectional view taken along the line II-II 'of FIG. 2.
3C is a cross-sectional view of a state where a voltage is applied to the display device shown in FIG. 3B.
4A to 4E are cross-sectional views illustrating a manufacturing process of the liquid crystal display according to the exemplary embodiment shown in FIG. 1.
5A through 5E are cross-sectional views illustrating a manufacturing process of a liquid crystal display device according to an exemplary embodiment of the present invention shown in FIGS. 2 and 3.
6A through 6F are cross-sectional views illustrating a manufacturing process of a liquid crystal display according to another exemplary embodiment of the present invention illustrated in FIGS. 2 and 3.

Hereinafter, a small and medium liquid crystal display and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the accompanying drawings. I) The shape, size, ratio, angle, number, etc. shown in the accompanying drawings may be changed to be rough. ii) Since the drawings are shown with the eyes of the observer, the direction or position for describing the drawings may be variously changed according to the positions of the observers. iii) The same reference numerals may be used for the same parts even if the reference numbers are different. iv) When 'include', 'have', 'consist', etc. are used, other parts may be added unless 'only' is used. v) When described in the singular, the plural can also be interpreted. vi) Even if the shape, size comparison, positional relationship, etc. are not described as 'about' or 'substantial', they are interpreted to include a normal error range. vii) The terms 'after', 'before', 'following', 'and', 'here', 'following' and 'when' are not used to limit the temporal position. . viii) The terms 'first', 'second', 'third', etc. are merely used selectively, interchangeably or repeatedly, for convenience of distinction and are not to be interpreted in a limiting sense. ix) If the positional relationship between two parts is described as 'upper', 'upper', 'lower' or 'next', etc., one or more Other parts may be located. x) When parts are connected with '~', they are interpreted to include not only parts but also combinations, but only when parts are connected with 'or'.

Small and Medium Liquid Crystal Display

1 is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.

The embodiment shown in FIG. 1 is an example of a liquid crystal display device implemented in TN, VA mode, and the like, and a lower substrate including a thin film transistor and a storage capacitor will be illustrated for convenience of description.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a lower substrate 10, a thin film transistor TFT formed in a first region of the lower substrate 10, and a storage formed in a second region. Capacitor Cst is provided.

The thin film transistor TFT includes a gate electrode 12 formed on the lower substrate 10, a gate insulating film 18 formed on the gate electrode 12, and a semiconductor layer 23 formed on the gate insulating film 18. ) And a source electrode 26 and a drain electrode 28 formed on the semiconductor layer 23.

The gate electrode 12 is electrically connected to a gate line (not shown), and receives a gate signal from the gate line. The gate insulating layer 18 is formed on the gate electrode 12 to electrically insulate the gate electrode 12 from the source / drain electrodes 26 and 28.

The semiconductor layer 23 forms a conductive channel between the source electrode 26 and the drain electrode 28. To this end, the semiconductor layer 23 includes an active layer 20 and an ohmic contact layer 22 formed between the active layer 20, the source electrode 26, and the drain electrode 28. The active layer 20 is formed of amorphous silicon not doped with impurities, and the ohmic contact layer 22 is formed of amorphous silicon doped with N-type or P-type impurities. The semiconductor layer 23 supplies the voltage supplied to the source electrode 26 to the drain electrode 28 when the gate signal is supplied to the gate electrode 12.

The storage capacitor Cst is formed by overlapping the storage lower electrode 30 and the storage upper electrode 25 with the gate insulating layer 18 therebetween. The storage lower electrode 30 is formed of a transparent conductive material on the same layer as the gate electrode 12. For example, the storage lower electrode 30 may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO).

The storage upper electrode 25 is positioned to overlap the storage lower electrode 30 and is electrically connected to the drain electrode 28. The storage upper electrode 25 is formed of the same transparent conductive material as the storage lower electrode 30. The storage upper electrode 25 is electrically connected to the pixel electrode 42 through the contact hole 40. To this end, the contact electrode 32 is further formed on the storage upper electrode 25 to be exposed by the contact hole 40.

The contact electrode 32 is formed of a material having a lower resistance than the transparent conductive material. For example, the contact electrode 32 is formed of the same material as the drain electrode 28 to lower the resistance of the storage upper electrode 25. The contact electrode 32 is electrically connected to the pixel electrode 42.

The passivation layer 38 is formed between the storage upper electrode 25 and the pixel electrode 42. In practice, the protective film 38 is formed to cover the source electrode 26, the drain electrode 28, the storage upper electrode 25, and the contact electrode 32.

That is, the embodiment illustrated in FIG. 1 is characterized in that the electrodes 25 and 30 constituting the storage capacitor are implemented with a transparent conductive material.

In general, a liquid crystal display device is classified into a large liquid crystal display device if it is larger than this, based on 11 inches with respect to the size of the screen, and a small and medium-sized liquid crystal display device.

In this case, the small- and medium-sized liquid crystal display device has a smaller pixel size than a large liquid crystal display device used in a TV and the like, so that the storage capacitor is located in the transmission region of the pixel. Here, the transmission region refers to a region where the pixel electrode 42 formed on the lower substrate 10 and the common electrode (not shown) formed on the upper substrate (not shown) overlap.

That is, when the electrodes constituting the storage capacitor are formed of an opaque metal, the transmissive area of the small and medium-sized liquid crystal display is reduced, and the aperture ratio is remarkably lowered.

Thus, in the embodiment of the present invention, the electrodes 25 and 30 constituting the storage capacitor are implemented with a transparent conductive material, thereby overcoming the problem of decreasing the aperture ratio.

2 is a plan view of a small and medium liquid crystal display according to another exemplary embodiment of the present invention. 3A is a cross-sectional view taken along the line II ′ of FIG. 2. 3B is a cross-sectional view taken along the line II-II 'of FIG. 1.

2 and 3 illustrate an example of a high vertical alignment mode (HVA) mode in which a liquid crystal domain is formed to improve a viewing angle.

3A and 3B show a state where no voltage is applied between the pixel electrode and the common electrode. For convenience of description, FIGS. 3A and 3B illustrate a thin film transistor having a semiconductor layer including amorphous silicon and having a bottom gate structure. However, embodiments of the present invention are not limited to the thin film transistor.

2, 3A and 3B, the display device includes a first substrate 100, a second substrate 200, and a liquid crystal layer 300.

The first substrate 100 includes the first base member 110, the first gate line GL1, the second gate line GL2, the storage line STL, the first insulating layer 120, and the first data line ( DL1, a second data line DL2, a thin film transistor SW as a switching element, a second insulating layer 140, a domain forming layer 150, a pixel electrode PE, and a first alignment layer AL1.

The storage line STL may be connected to the first electrode 160 of the storage capacitor overlapping the pixel electrode PE. The second electrode 170 of the storage capacitor may be positioned to overlap at least a portion of the first electrode 160 between the first electrode 160 and the pixel electrode PE. The storage capacitance Cst of each pixel may be implemented by the first electrode 160 and the second electrode 170 included in the storage capacitor.

As mentioned above, the liquid crystal display of the small and medium size (11 inches or less) has a smaller pixel size than the large liquid crystal display of the TV size or more. In addition, the storage capacitor is located in the transmission region P of the pixel. As a result, when the first electrode 160 and the second electrode 170 of the storage capacitor include an opaque conductive material, the transmittance is significantly reduced.

Unlike the organic light emitting display, the liquid crystal display adopts a backlight unit (not shown) positioned under the first substrate 100 to provide light. Therefore, unlike the organic light emitting device in which light is directly emitted from the organic light emitting material, the transmittance through which the light provided from the backlight unit is transmitted is relatively important in the liquid crystal display device.

Therefore, in order to maintain a desired transmittance, the widths of the first electrode 160 and the second electrode 170 including the opaque conductive material may not be sufficiently expanded or limited only. Due to the limited expansion of the first electrode 160 and the second electrode 170 including such an opaque conductive material, it is difficult to sufficiently secure the capacitance of the storage capacitor.

According to embodiments of the present invention, at least one of the first electrode 160 and the second electrode 170 of the storage capacitor may include a transparent conductive material. For example, the first electrode 160 and the second electrode 170 may each include a transparent conductive material and an opaque conductive material. As another example, the first electrode 160 and the second electrode 170 may each include an opaque conductive material and a transparent conductive material. As another example, both the first electrode 160 and the second electrode 170 may include a transparent conductive material.

In this case, even if the width of at least one of the first electrode 160 and the second electrode 170 is increased, the decrease in transmittance is relatively small. Accordingly, the width of the first electrode 160 and the second electrode 170 may be increased to increase the capacitance between the first electrode 160 and the second electrode 170 while considering the problems caused by the decrease in transmittance. have.

The pixel electrode PE may substantially correspond to the transmission area P. FIG. Here, at least one of the first electrode 160 and the second electrode 170 may extend to substantially correspond to the pixel electrode PE. Alternatively, at least one of the first electrode 160 and the second electrode 170 may be formed wider than the pixel electrode PE. In this case, at least one of the first electrode 160 and the second electrode 170 may overlap the black matrix pattern 220 positioned in the non-transmissive region.

Although at least one of the first electrode 160 and the second electrode 170 is formed to have an area corresponding to the entire transmission region P so as to overlap the pixel electrode PE substantially corresponding to the transmission region P of the pixel. The decrease in transmittance is relatively small.

Therefore, there is an advantage that the design can be changed in consideration of the problems caused by the decrease in transmittance. In addition, the capacitance may be increased by extending one of the first electrode 160 and the second electrode 170 to the non-transmissive region.

Examples of the transparent conductive material include indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). And the like. These may be used alone or in combination.

The first and second gate lines GL1 and GL2 may extend along the first direction D1 on the first base member 110. The first and second data lines DL1 and DL2 may be arranged substantially parallel to each other in a second direction D2 different from the first direction D1. The second direction D2 may be, for example, a direction perpendicular to the first direction D1. The storage line STL may be disposed between the first and second gate lines GL1 and GL2 and may extend along the first direction D1. The first insulating layer 120 may be formed on the first base member 110 to cover the first and second gate lines GL1 and GL2, the storage line STL, and the first electrode 160.

The first and second data lines DL1 and DL2 extend along the second direction D2 on the first insulating layer 120, and the first and second data lines DL1 and DL2 respectively correspond to the first and second data lines DL1 and DL2. The second gate lines GL1 and GL2 may cross the storage lines STL. In the first substrate 100, a pixel area may be divided by the first and second gate lines GL1 and GL2 and the first and second data lines DL1 and DL2. The pixel electrode PE may be formed in the transmission area P of the pixel area. As described above, a pixel region may be partitioned on the first and second gate lines GL1 and GL2 and the first and second data lines DL1 and DL2, but embodiments of the present invention are not limited thereto.

The pixel region may be divided into a transparent region P in which the pixel electrode PE and the first and second electrodes 160 and 17 are formed, and a thin film transistor region in which the thin film transistor SW is formed.

The thin film transistor SW may include a gate electrode GE connected to the first gate line GL1 and a semiconductor layer 130 and a first data line formed on the first insulating layer 120 to correspond to the gate electrode GE. A source electrode SE connected to the DL1 and overlapping the semiconductor layer 130 and a drain electrode DE spaced apart from the source electrode SE1 and overlapping the semiconductor layer 130 may be included.

The semiconductor layer 130 may include an active layer 130a and an ohmic contact layer 130b sequentially formed on the first insulating layer 120.

In an exemplary embodiment of the present invention, the end of the drain electrode DE may be electrically connected to the second electrode 170 which is an upper electrode of the storage capacitor.

The second insulating layer 140 may be formed on the first insulating layer 120 to cover the first and second data lines DL1 and DL2, the source electrode SE, and the drain electrode DE.

The domain forming layer 150 serves to planarize the first substrate 100 and may be formed on the second insulating layer 140.

The domain forming layer 150 may include a recess pattern 152 formed to be recessed downward from the surface. The recessed pattern 152 may be formed in the transmission region P, and form a liquid crystal domain of the transmission region P. FIG. The recessed pattern 152 may be implemented in a dot type, and the domain forming layer 150 and the second insulating layer 140 corresponding to the region where the recessed pattern 152 is located are opened to open the second electrode ( 170) may be exposed.

However, in the exemplary embodiment of the present invention, the contact electrode CNT may be formed under the region of the recessed pattern 152 having the opening shape. The contact electrode CNT may be formed in an island form on the second electrode 170. The contact electrode CNT corresponds to an area having an opening shape by the recessed pattern 152. In addition, the contact electrode CNT may include the same material as the source electrode SE and the drain electrode DE of the thin film transistor. That is, the contact electrode CNT may include a low resistance metal.

The embedded pattern 152 may be formed as a dot-shaped hole exposing a part of the contact electrode CNT. The embedding pattern 152 may include an organic material or an inorganic material. In other embodiments, the domain forming layer 150 may include an organic layer formed of the organic material and an inorganic layer formed of the inorganic material, and the embedding pattern 152 may be formed in the organic layer or the inorganic layer.

The pixel electrode PE is formed on the domain forming layer 150 of the transmission region P. The pixel electrode PE may include a transparent conductive material. The pixel electrode PE may be formed to entirely cover the recessed pattern 152. The pixel electrode PE may be electrically connected to the thin film transistor SW by contacting the contact electrode CNT through the recess pattern 152.

In addition, the contact electrode CNT may include a low-resistance metal to overcome a problem caused by high resistance values of the first and second electrodes 160 and 170 including the transparent conductive material.

In an area having the same area in plan view, the area of the pixel electrode PE on the embedding pattern 152 is relatively wider than the area of the pixel electrode PE formed on the flat area of the domain formation layer 150. Accordingly, when an electric field is formed between the first substrate 100 and the second substrate 200, the intensity of the electric field in a region close to the embedding pattern 152 may correspond to that of the flat region where the embedding pattern 152 is not formed. It can be relatively large compared to the strength of the electric field.

The first alignment layer AL1 may be formed on the entire surface of the first base member 110 including the pixel electrode PE.

The second substrate 200 may include a second base member 210, a black matrix pattern 220, first, second and third color filters 232, 234, and 236 facing the first substrate 100. The overcoat layer 240, the common electrode layer 250, and the second alignment layer AL2 may be included. The second substrate 200 may not include the overcoat layer 240.

The black matrix pattern 220 may include a second base member 210 corresponding to a region where the first and second gate lines GL1 and GL2, the first and second data lines DL1 and DL2, and the thin film transistor SW are formed. It can be formed on). The first, second and third color filters 232, 234, and 236 may be formed in regions of the second base member 210 defined by the black matrix pattern 220. For example, the first color filter 232 may be formed on the second base member 210 in a region corresponding to the transparent region P in which the pixel electrode PE is formed. A second color filter 234 may be formed in the first direction D1 of the first color filter 232, and a third color filter in a direction opposite to the first direction D1 of the first color filter 232. 236 may be formed. The overcoat layer 240 is formed on the second base member 210 on which the black matrix pattern 220 and the first, second and third color filters 232, 234, and 236 are formed, and the second substrate 200. ) Can be flattened.

The common electrode 250 may be formed on the overcoat layer 240. The common electrode 250 may include a transparent conductive material.

In an exemplary embodiment of the present invention, the common electrode 250 may be formed on the entire surface of the second substrate 200 without a separate pattern. That is, the liquid crystal domain of the liquid crystal layer 300 may be formed by the pixel electrode PE and the patternless common electrode 250 which may change the intensity of the electric field by the embedding pattern 152.

The second alignment layer AL2 may be formed on the second base member 210 on which the common electrode 250 is formed. The second alignment layer AL2 may be formed on the entire surface of the second substrate 200.

The liquid crystal layer 300 may be positioned between the first substrate 100 and the second substrate 200. The liquid crystal layer 300 may include liquid crystal molecules 310 and a reactive mesogen cured product (reactive mesogen 320, hereinafter referred to as an “RM cured product”).

The arrangement of the liquid crystal molecules 310 is changed by an electric field formed between the pixel electrode PE and the common electrode 250, so that light transmittance may be adjusted. The liquid crystal molecules 310 may have, for example, negative dielectric anisotropy.

In a state in which no voltage is applied between the pixel electrode PE and the common electrode 250, the liquid crystal molecules 310 close to the first substrate 100 and / or the second substrate 200 may be formed of liquid crystal molecules 310. ) May be arranged in a vertical state with respect to the surfaces of the first base member 110 and / or the second base member 210. The long axis of the liquid crystal molecules 310 close to the embedded pattern 152 may be arranged in a direction perpendicular to the surface of the sidewall with respect to the surface of the sidewall of the domain forming layer 150 forming the combined pattern 152.

The RM cured material 320 may be located between the liquid crystal molecules 310. The RM cured material 320 may be positioned between the liquid crystal molecules 310 that are close to the pixel electrode PE and / or the common electrode 250. In detail, the RM cured material 320 may be located between the liquid crystal molecules 310 that are close to the first alignment layer AL1. In addition, the RM cured material 320 may be located between the liquid crystal molecules 310 close to the second alignment layer AL2.

The RM cured material 320 includes liquid crystal molecules 310 close to the first substrate 100 and / or the second substrate 200 even when an electric field is not applied between the pixel electrode PE and the common electrode 250. ) May be maintained in a pretilted state based on the surfaces of the first base member 110 and / or the second base member 210. The RM 320 may be formed by polymerizing RM monomers by external light in a process of manufacturing the display device.

The external light may be, for example, ultra violet ray (UV). The RM monomers are photoreacted by the external light and the RM monomers are polymerized to form an RM cured product 320 positioned between the liquid crystal molecules 310.

More specifically, in the state where a voltage is applied to the pixel electrode PE and the common electrode 250, ultraviolet rays of about 10 to 15 joules [J] are irradiated for about 6 to 7 minutes, and the pixel electrode PE is applied. RM monitors are attached to the pixel electrode PE and the common electrode 250 by irradiating strong ultraviolet rays of about 15 Joules for about 50 minutes to about 60 minutes without applying a voltage to the common electrode 250. The cured product 320 is changed.

If both of the first electrode 160 and the second electrode 170 include a reflective or opaque conductive material that is not a transparent conductive material, the RM cured product 320 may not be formed intact even after the second ultraviolet irradiation. In the region overlapping the first electrode 160 and the second electrode 170, a problem may occur that the RM cured material 320 is not attached. Therefore, according to embodiments of the present invention, at least one of the first electrode 160 and the second electrode 170 includes a transparent conductive material, thereby integrating or forming the RM cured product.

In this structure, the liquid crystal domain may be formed by the recess pattern 152 of the domain forming layer 150 without forming a separate pattern on the common electrode 250. In addition, since there is no separate pattern on the common electrode 250, the cause of misalignment between the first substrate 100 and the second substrate 200 may be eliminated.

In addition, the manufacturing process may be simplified by omitting a separate patterning process for patterning the common electrode 250. Accordingly, productivity and display quality of the display device can be improved.

2 and 3, the thickness of the first electrode 160 and the second electrode 170 is preferably 150 to 1500Å, the first insulating film formed between the first and second electrodes The thickness of 120 is preferably implemented in 400 ~ 6000 Å.

That is, when the thickness of the first and second electrodes 160 and 170 is 150 Å or less, the thickness is too thin, which is disadvantageous in terms of reliability.

In addition, when the thickness of the first insulating film 120 is 400 Å or less, the thickness may be too thin, which may cause the first and second electrodes to be short-circuited when static electricity is introduced. There is a disadvantage that the capacitance by the first and second electrodes is lowered.

As described above, when the liquid crystal display is implemented with the thicknesses of the first and second electrodes 160 and 170 and the first insulating layer 120 being optimized, the backlight (not shown) positioned below the first substrate 100 may be located. The light transmittance measured through the first and second substrates ranges from 80% to 99.5%.

3C is a cross-sectional view of a state where a voltage is applied to the display device shown in FIG. 3B.

Referring to FIG. 3C, when an electric field is formed between the pixel electrode PE and the common electrode 250, the direction of the electric field inside the pixel area is the first substrate 100 and / or the second substrate 200. The direction is perpendicular to the surface of.

The direction of the electric field may be bent between the end of the pixel electrode PE and the common electrode 250. The direction of the electric field may also be bent between the pixel electrode PE and an end of another pixel electrode adjacent to the common electrode 250. Accordingly, the liquid crystal molecules 310 are arranged to diverge toward different points of the common electrode 250 between the pixel electrodes PE that are adjacent to each other, thereby splitting the liquid crystal domains between the pixel areas that are adjacent to each other. .

The electric field shape of the region close to the recess pattern 152 is common to one point of the common electrode 250, for example, the region corresponding to the recess pattern 152 due to pretilt by the sidewalls of the recess pattern 152. It may have a shape that converges toward the electrode 250.

That is, according to the embodiment of the present invention as described above, in the implementation of the HVA mode liquid crystal display device to improve the viewing angle by forming the liquid crystal domain, the first electrode 160 used as an electrode of the storage capacitor of each pixel And the second electrode 170 is formed of a transparent conductive material to form an area corresponding to the entire pixel region so as to overlap the pixel electrode corresponding to the pixel region P, thereby reducing transmittance and reducing sufficient capacitance. Can be secured.

Manufacturing method of liquid crystal display device

Hereinafter, a method of manufacturing a liquid crystal display device according to embodiments of the present invention will be described with reference to FIGS. 4 to 6.

First, FIG. 4A is a cross-sectional view illustrating a manufacturing process of a liquid crystal display according to the embodiment shown in FIG. 1.

Referring to FIG. 4A, a gate electrode 12 is first formed in a thin film transistor (TFT) forming region on a lower substrate 10. The gate electrode 12 is stacked on the lower substrate 10 through a deposition method such as a sputtering method. The gate electrode 12 is formed of aluminum (Al), molybdenum (Mo), chromium (Cr), copper (Cu), or the like.

After the gate electrode 12 is formed, the storage lower electrode 30 is formed in the storage capacitor Cst formation region on the lower substrate through a deposition method. The storage lower electrode 30 is formed of a transparent conductive material. For example, the storage lower electrode 30 may be formed of any one of ITO, TO, IZO, and ITZO.

After the storage lower electrode 30 is formed, a gate insulating layer 18 is formed on the lower substrate 10 as shown in FIG. 4B, and includes an active layer 20 and an ohmic contact layer 22 in the TFT formation region. The semiconductor layer 23 is formed.

The gate insulating layer 18 is formed by depositing an inorganic insulating material such as silicon nitride (SiOx) and silicon oxide (SiNx) on the lower substrate 10 by a deposition method such as plasma enhanced chemical vapor deposition (PECVD). After the gate insulating layer 18 is formed, an amorphous silicon layer and an amorphous silicon layer doped with impurities are sequentially formed. Subsequently, the semiconductor layer 23 including the active layer 20 and the ohmic contact layer 22 is formed by patterning the amorphous silicon layer and the amorphous silicon layer doped with impurities by a photolithography process and an etching process.

After the semiconductor layer 23 is formed, the storage upper electrode 25 is formed in the storage capacitor Cst formation region as shown in FIG. 4C through the deposition method. The storage upper electrode 25 is formed of a transparent conductive material. For example, the storage upper electrode 25 may be formed of any one of ITO, TO, IZO, and ITZO.

After the storage upper electrode 25 is formed, the source electrode 26, the drain electrode 28, and the contact electrode 32 are formed. The source electrode 26, the drain electrode 28 and the contact electrode 32 are formed by a deposition method such as sputtering. Subsequently, the source electrode 26, the drain electrode 28, and the contact electrode 32 are deposited with a metal material (for example, molybdenum (Mo), molybdenum tungsten (MoW)) and the like by a photolithography process and an etching process. It is formed by patterning. Here, the active layer 20 is exposed by removing the ohmic contact layer 22 exposed between the two electrodes 26 and 28 using the source electrode 26 and the drain electrode 28 as a mask. The drain electrode 28 is formed to partially overlap the storage upper electrode 25 to be in electrical contact with the storage upper electrode 25. In other words, the drain electrode 28 and the storage upper electrode 25 are electrically connected so that the pixel voltage supplied to the drain electrode 28 via the source electrode 26 can be charged in the storage capacitor Cst. .

In addition, the contact electrode 32 is formed in a portion of the storage upper electrode 25. In practice, the contact electrode 32 is located in an area overlapping with the contact hole 40 of the protective film 38 to be formed later.

After the source electrode 26 and the drain electrode 28 are formed, a protective film 38 is formed to cover the source electrode 26, the drain electrode 28, and the storage upper electrode 25 as shown in FIG. 4D. The protective film is formed by PECVD, spin coating, spinless coating, or the like. In addition, the protective layer 38 is patterned by a photolithography process and an etching process to form a contact hole 40. Here, the contact hole 40 is located in an area overlapping with the contact electrode 32. The protective film 38 is formed of an inorganic insulating material such as the gate insulating film 18 or an organic insulating material such as acrylic.

After the passivation layer 38 is formed, the pixel electrode 42 is formed on the passivation layer 38 as shown in FIG. 4E. The pixel electrode 42 is formed by a deposition method such as sputtering or the like. The pixel electrode 42 is in electrical contact with the contact electrode 32 via the contact hole 40. That is, the pixel electrode 42 is in electrical contact with the storage upper electrode 25 via the contact electrode 32, and controls the electric field of the liquid crystal corresponding to the voltage charged in the storage capacitor Cst. On the other hand, the pixel electrode 42 is formed of a transparent conductive material such as ITO, TO, IZO and ITZO.

As described above, when the storage upper electrode 25 and the storage lower electrode 30 are formed of a transparent conductive material, the overlapping area of the storage upper electrode 25 and the storage lower electrode 30 can be set wide regardless of the aperture ratio. have. Therefore, a high capacity storage coffee sheet Cst can be formed, thereby improving driving reliability. In addition, when the storage upper electrode 25 and the storage lower electrode 30 are formed of a transparent conductive material, there is an advantage of ensuring a high aperture ratio. In addition, the present invention further minimizes an increase in resistance due to the transparent conductive material by further forming a contact electrode 32 formed of a metal material at a portion where the storage upper electrode 25 and the pixel electrode 42 contact each other.

5A to 5E are cross-sectional views illustrating a manufacturing process of the first substrate in the cross-sectional area shown in FIG. 3A.

Referring to FIG. 5A, a transparent conductive material 162 and a low resistance metal 164 are sequentially deposited on the substrate 110. Subsequently, the patterning process is performed to form the gate line GL, the gate electrode GE, and the first electrode 160 of the storage capacitor.

As described above, in the exemplary embodiment of the present invention, the first electrode 160 is integrally formed with the storage line STL and includes a transparent conductive material.

When the first electrode 160 is disposed on the same layer as the gate line GL and the gate electrode GE and is formed of a material different from the gate line GL and the gate electrode GE, the first electrode 160 is formed. In addition to the mask process used when forming the gate line GL and the gate electrode GE when forming the other mask process is added.

For example, the gate line GL and the gate electrode GE include a low resistance opaque metal such as molybdenum Mo, and the first electrode 160 includes a transparent conductive material such as indium tin oxide (ITO). In this case, it is difficult to form the first electrode 160 using a mask for forming the gate line GL and the gate electrode GE. Therefore, in this case, since a mask process must be added to form the first electrode 160, manufacturing cost may increase or process time may increase.

Accordingly, in the embodiment of the present invention, in forming the gate line GL / gate electrode GE and the first electrode 160, the gate line GL / gate electrode GE is not added by using a halftone mask process. ) And the first electrode are formed at the same time.

However, when using the halftone mask process as described above, the gate line GL / gate electrode GE is implemented as a stacked structure of the transparent conductive material 162 and the low resistance metal 164 as shown.

Specifically, after the transparent conductive material and the low resistance metal are sequentially deposited on the substrate, the thickness of the photoresist PR positioned on the region where the first electrode 160 is to be formed during the photo process is determined by the gate line. The gate line GL / gate electrode GE may be formed of the transparent conductive material 162 and the low resistance metal 164 by being thinner than the thickness of the photoresist positioned on the region where the gate electrode is to be formed. Although the first electrode 160 is formed of a stacked structure, all of the low-resistance metals disposed thereon are removed. As a result, only the first electrode 160 including only the transparent conductive material remains as shown.

As a result, the gate line GL / gate electrode GE and the first electrode 160 may be simultaneously formed without a separate mask process.

Examples of the transparent conductive material may include indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (indium tin zinc oxide); ITZO) and the like. These may be used alone or in combination.

In addition, examples of the low resistance metal may include molybdenum (Mo), aluminum (Al), aluminum niobium (AlNd), titanium (Ti), and the like, which may be used alone or in combination, or may be used in a laminated structure.

Next, as illustrated in FIG. 5B, the first insulating layer 120 is formed on the substrate 110 on which the gate line GL / gate electrode GE and the first electrode 160 are formed, and the active layer ( The semiconductor layer 130 including the 130a) and the ohmic contact layer 130b is formed.

The first insulating layer 120 is formed by depositing an inorganic insulating material such as silicon nitride (SiOx) and silicon oxide (SiNx) on the substrate 110 through a deposition method such as plasma enhanced chemical vapor deposition (PECVD). After the first insulating layer 120 is formed, an amorphous silicon layer and an amorphous silicon layer doped with impurities are sequentially formed. Subsequently, an amorphous silicon layer and an amorphous silicon layer doped with impurities are patterned by a photolithography process to form a semiconductor layer 130 including an active layer 130a and an ohmic contact layer 130b.

After the semiconductor layer 130 is formed, the second electrode 170 of the storage capacitor is formed in the transmission region P, that is, the region overlapping with the first electrode 160, as shown in FIG. 3C through the deposition method. The second electrode 170 may be formed of a transparent conductive material. Examples of the transparent conductive material may include ITO, TO, IZO, ITZO, and the like. These may be used alone or in combination.

As described above, in the embodiment of the present invention, since the first electrode 160 and the second electrode 170 used as the electrodes of the storage capacitor include a transparent conductive material, the first electrode 160 and the second electrode 170 may be replaced with each other. The substrate may be formed to have an area corresponding to the entire transmission region so as to overlap the pixel electrode PE corresponding to the transmission region P of the pixel. Therefore, sufficient capacitance can be ensured while reducing the transmittance.

In addition, after the second electrode 170 is formed, the data line DL, the source electrode SE, the drain electrode DE, and the contact electrode CNT may be formed. The source electrode SE, the drain electrode DE, and the contact electrode CNT may be formed by a deposition method such as sputtering. The source electrode SE, the drain electrode DE, and the contact electrode CNT may be formed by depositing a metal material (for example, molybdenum (Mo) or molybdenum tungsten (MoW)) and then performing a photolithography process. have. Here, the active layer 130a may be exposed by removing the ohmic contact layer 130b exposed between the two electrodes using the source electrode SE and the drain electrode DE as a mask. The drain electrode DE may be formed to partially overlap the second electrode 170 to be in electrical contact with the second electrode 170.

That is, the drain electrode DE and the second electrode 170 may be electrically connected to each other so that the pixel voltage supplied to the drain electrode DE via the source electrode SE may be charged in the storage capacitor Cst. .

In addition, the contact electrode CNT may be formed in a portion of the second electrode 170. The contact electrode CNT may be positioned to overlap the region exposed by the recess pattern 152 of the second insulating layer 140 and the domain forming layer 150 to be formed later.

After the source electrode SE and the drain electrode DE are formed, as illustrated in FIG. 5D, the second insulating layer 140 and the domain forming layer may be formed to cover the source electrode SE, the drain electrode DE, and the second electrode 170. 150 may be formed. The second insulating layer 140 and the domain forming layer 150 may be formed by PECVD, spin coating, spinless coating, or the like. In addition, the second insulating layer and the domain forming layer may be patterned by a photolithography process and an etching process to form the indentation pattern 152. The indentation pattern 152 may be positioned in an area overlapping the contact electrode CNT.

Examples of the material forming the second insulating layer 140 may include silicon oxide, silicon nitride, or the like. Examples of the material included in the domain forming layer 150 may include an organic material such as a positive photoresist composition or a negative photoresist composition. Alternatively, examples of the material included in the domain forming layer 150 may include an inorganic material such as silicon oxide or silicon nitride.

Referring to FIG. 5E, a transparent electrode layer (not shown) is formed on the domain forming layer 150 on which the embedding pattern 152 is formed. The transparent electrode layer is patterned to form the pixel electrode PE.

The pixel electrode PE may be electrically connected to the thin film transistor SW by contacting the contact electrode CNT through the recess pattern 152.

Examples of the material included in the transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), or the like.

In addition, the first alignment layer AL1 may be formed on the pixel electrode PE. In this case, the first alignment layer AL1 may include a vertical alignment material capable of vertically aligning the liquid crystal molecules 310.

5 illustrates that the thin film transistor has a bottom gate structure in which a semiconductor layer is formed of amorphous silicon, but the embodiment of the present invention is not limited thereto.

That is, the thin film transistor may be implemented as a top gate structure in which a semiconductor layer is implemented of polysilicon, and embodiments of the structure will be described in detail below.

6A through 6F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to another exemplary embodiment of the present invention.

However, this is a cross-sectional view showing the manufacturing process of the first substrate of the cross-sectional area shown in FIG. 3A and will be described as being limited to the pixel area partitioned by the gate line and the data line for convenience of description. In this case, the pixel region is divided into a thin film transistor region and a transmissive region.

First, referring to FIG. 6A, a semiconductor layer 430 formed of poly-Si may be formed on the thin film transistor region SW on the substrate 110.

The polysilicon semiconductor layer 430 is formed by depositing an amorphous silicon layer, followed by an Excimer Laser Annealing (ELA) method, a sequential lateral solidification (SLS) crystallization method, a heat treatment method, or a metal induced lateral crystallization (MIL) method. By performing a crystallization process, such as, the amorphous silicon layer may be crystallized into a polysilicon layer.

In addition, the semiconductor layer 430 may have an active region 430a including pure polysilicon in the center and a source / drain region 430b doped to both sides of the active region.

Referring to FIG. 6B, a first insulating layer 420 may be formed on the entire surface of the substrate 110 on which the semiconductor layer 430 is formed. The gate electrode GE and the first electrode 160 of the storage capacitor may be formed in the region overlapping the semiconductor layer 430 and the transmission region P, respectively.

However, this is formed by sequentially depositing a transparent conductive material and a low resistance metal, and then patterning the transparent conductive material and the low resistance metal, and using the halftone mask process as described above with reference to FIG. 5A, the gate electrode and the first electrode are not added. This can be formed at the same time.

However, when using the halftone mask process as described above, the gate electrode may have a stacked structure of a transparent conductive material 462 and a low resistance metal 464 as shown.

Specifically, after sequentially depositing the transparent conductive material 462 and the low resistance metal 464 on the substrate 110, the photoresist PR is positioned on the region where the first electrode is to be formed in the photo process. ) Is made thinner than the thickness of the photoresist positioned on the region where the gate electrode is to be formed, so that the gate electrode GE is laminated with the transparent conductive material 462 and the low resistance metal 464 during the subsequent exposure and etching process. Although the first electrode 460 is formed of a structure, all of the low resistance metals disposed thereon are removed, and as a result, the first electrode 460 is formed of only a transparent conductive material.

As a result, the gate electrode GE and the first electrode 460 may be simultaneously formed without the addition of a mask process.

Examples of the transparent conductive material may include indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), and indium tin zinc oxide (indium tin zinc oxide); ITZO) and the like. These may be used alone or in combination.

In addition, examples of the low resistance metal may include molybdenum (Mo), aluminum (Al), aluminum niobium (AlNd), titanium (Ti), and the like. These may be alone or mixed. In addition, they may be used in a single structure or a laminated structure.

As shown in FIG. 6C, the second insulating layer 422 is formed on the substrate including the gate electrode GE and the first electrode 460, and is stored in an area on the second insulating layer overlapping the first electrode 460. The second electrode 470 of the capacitor is formed.

In this case, the second electrode 470 may be formed of a transparent conductive material such as the first electrode 460.

That is, in the exemplary embodiment of the present invention, since the first electrode and the second electrode used as the electrodes of the storage capacitor are both made of a transparent conductive material, it is overlapped with the pixel electrode corresponding to the transparent region P of the pixel. It can be formed in an area corresponding to the whole, through which it is possible to secure a sufficient capacitance while reducing the transmittance.

In addition, after the second electrode 470 is formed, as shown in FIG. 6D, the source electrode SE, the drain electrode DE, and the contact electrode CNT may be formed. The source electrode SE, the drain electrode DE, and the contact electrode CNT may be formed by a deposition method such as sputtering. Subsequently, the source electrode, the drain electrode, and the contact electrode may be formed by depositing a metal material (eg, molybdenum (Mo), molybdenum tungsten (MoW)) and the like and patterning the photolithography process and the etching process.

In this case, the source electrode SE and the drain electrode DE are electrically connected to the source / drain regions 430b of the semiconductor layer 430, respectively, and the second insulating layer may be formed on the source and drain regions. The contact hole may be formed at 422.

The drain electrode DE may be formed to partially overlap the second electrode 470 so as to be in electrical contact with the second electrode 470.

In other words, the drain electrode DE and the second electrode 470 may be electrically connected to each other so that the pixel voltage supplied to the drain electrode DE via the source electrode SE may be charged in the storage capacitor Cst. Can be.

In addition, the contact electrode CNT may be formed in a partial region of the second electrode 470. In fact, the contact electrode CNT may be positioned to overlap the region exposed by the recess pattern 452 of the third insulating layer 440 and the domain forming layer 450 to be formed later.

After the source electrode SE and the drain electrode DE are formed, as illustrated in FIG. 6E, the third insulating layer 440 and the domain forming layer 450 may be formed to cover the source electrode, the drain electrode, and the second electrode 470. have. The third insulating layer 440 and the domain formation layer 450 may be formed by PECVD, spin coating, spinless coating, or the like. In addition, the indentation pattern 452 may be formed by patterning the third insulating layer 440 and the domain forming layer 450 by a photolithography process and an etching process. The indentation pattern 452 may be located in an area overlapping the contact electrode CNT.

Examples of the material for forming the third insulating layer 440 include silicon oxide, silicon nitride, and the like. Examples of the material for forming the domain forming layer 450 include an organic material such as a positive photoresist composition or a negative photoresist composition, and an inorganic material such as silicon oxide and silicon nitride.

6F, a transparent electrode layer (not shown) is formed on the domain forming layer 450 on which the embedding pattern 452 is formed, and the transparent electrode layer is patterned to form the pixel electrode PE.

The pixel electrode PE may be electrically connected to the thin film transistor SW by contacting the contact electrode CNT through the recess pattern 452.

Examples of the material for forming the transparent electrode layer include indium tin oxide (ITO), indium zinc oxide (IZO), and the like.

In addition, the first alignment layer AL1 is formed on the pixel electrode PE, and in this case, the first alignment layer AL1 may include a vertical alignment material capable of vertically aligning the liquid crystal molecules 310.

130 and 430: semiconductor layers 160 and 460: first electrode
170 and 470: second electrode 150 and 450: domain forming layer
152, 452: intrusion pattern

Claims (27)

A first substrate;
A thin film transistor formed in a first region of the first substrate;
A storage capacitor formed in a second region of the first substrate,
A small and medium liquid crystal display device, wherein the first electrode and the second electrode of the storage capacitor are formed of a transparent conductive material. The small and medium size liquid crystal display of claim 1, wherein a pixel electrode is further formed on a second region overlapping the first and second electrodes of the storage capacitor. The small and medium sized liquid crystal display of claim 2, wherein a domain forming layer including an embedding pattern for forming a liquid crystal domain is formed between the second electrode and the pixel electrode of the storage capacitor. The semiconductor device of claim 1, further comprising: a second substrate including a common electrode formed on a front surface of the first substrate;
And a liquid crystal layer disposed between the first substrate and the second substrate, the liquid crystal layer having a reactive mesogen (RM) for fixing liquid crystal molecules forming a liquid crystal domain. The small and medium liquid crystal display of claim 1, wherein the thin film transistor includes a gate electrode, a source electrode, and a drain electrode formed with the gate electrode and the insulating layer interposed therebetween. The small and medium liquid crystal display of claim 5, wherein the gate electrode is formed on the same layer as the first electrode. The small and medium liquid crystal display of claim 5, wherein the gate electrode is formed of a stacked structure of a transparent conductive material and a low resistance metal. 6. The small and medium liquid crystal display of claim 5, wherein the drain electrode is formed to overlap a portion of the second electrode so that the second electrode and the drain electrode are electrically connected. The small and medium liquid crystal display device of claim 3, wherein a contact electrode is further formed on an area of the second electrode exposed by the embedding pattern. The small and medium liquid crystal display device of claim 1, wherein the contact electrode is formed of the same material as the source electrode and the drain electrode of the thin film transistor. The medium and small size liquid crystal display of claim 1, wherein the transparent conductive material is formed of any one of indium tin oxide, tin oxide, indium zinc oxide, and indium tin zinc oxide. The small and medium liquid crystal display of claim 1, wherein the first region is a non-transmissive region, and the second region is a transmissive region. Forming a gate electrode of the thin film transistor and a first electrode of the storage capacitor on the first substrate;
Forming a second electrode of a storage capacitor on a first insulating layer overlapping the first electrode;
Forming a second insulating layer and a domain forming layer on which a recessed pattern exposing a portion of the second electrode is formed;
Forming a pixel electrode on the domain forming layer overlapping the second electrode,
The method of claim 1, wherein the first electrode and the second electrode of the storage capacitor are formed of a transparent conductive material. 14. The method of claim 13, further comprising: positioning a second substrate including a common electrode on a front surface of the first substrate;
And forming a liquid crystal layer between the first substrate and the second substrate, the liquid crystal layer having a reactive mesogen for fixing liquid crystal molecules embodying a liquid crystal domain. The method of claim 13, wherein the gate electrode and the first electrode are implemented on the same layer using a halftone mask process. 16. The method of claim 15, wherein the gate electrode is formed of a laminated structure of a transparent conductive material and a low resistance metal. 15. The method of claim 13, further comprising: forming a semiconductor layer above or below the gate electrode;
And forming source and drain electrodes electrically connected to the semiconductor layer. The method of claim 13, further comprising forming a contact electrode on a region of the second electrode exposed by the embedding pattern. 19. The method of claim 18, wherein the contact electrode is formed of the same material as the source electrode and the drain electrode of the thin film transistor. The method of claim 13, wherein the transparent conductive material is formed of any one of indium tin oxide, tin oxide, indium zinc oxide, and indium tin zinc oxide. A first substrate comprising a pixel capacitor and a storage capacitor including a thin film transistor positioned in a non-transmissive region, a transparent first electrode sequentially positioned in a transmissive region, a dielectric layer, and a transparent second electrode;
A second substrate facing the second substrate and including a common electrode; And
A liquid crystal layer positioned between the first substrate and the second substrate,
And the transmission area is defined as an area where the pixel electrode and the common electrode overlap each other. 22. The small and medium liquid crystal display of claim 21, wherein the pixel electrode includes a transparent conductive material and overlaps at least one of the first electrode and the second electrode to form a capacitance together with a storage capacitor. 22. The method of claim 21, further comprising a backlight positioned below the first substrate,
And a light transmittance of the light incident from the backlight and passing through the first substrate, the liquid crystal layer, and the second substrate in the transmission region is 80% to 99.5%. 24. The small and medium liquid crystal display of claim 23, wherein the dielectric film is formed of a film including at least one selected from the group consisting of silicon nitride and silicon oxide. The method of claim 24, wherein the thickness of the first electrode is 150 kPa to 1500 kPa,
The thickness of the insulating film is 400 kPa to 6000 kPa,
A small and medium liquid crystal display device having a thickness of 150 kW to 1500 kPa. 22. The small and medium liquid crystal display of claim 21, wherein at least one of the first electrode and the second electrode extends outside the transmission area. 22. The medium and small size liquid crystal display of claim 21, wherein the size of the liquid crystal display is 11 inches or less.

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