KR20110048333A - Array substrate for fringe field switching mode liquid crystal display device - Google Patents

Abstract

PURPOSE: An array substrate for a fringe field switching mode liquid crystal display device is provided to reduce the defective gradation and the crosstalk by minimizing the coupling between a data wire and a pixel electrode during an inversion driving operation. CONSTITUTION: An array substrate for a fringe field switching mode liquid crystal display device comprises: a gate wire which is extended in one direction on a transparent substrate; a gate insulating film(115) which is formed on the gate wire; a data wire which defines a pixel region(P) by crossing the gate wire at right angle; and a thin film transistor(Tr) which is connected to the gate wire and the data wire.

Description

Array substrate for fringe field switching mode liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device capable of suppressing horizontal crosstalk generation and reducing power consumption.

In general, the liquid crystal display device is driven by using the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display device (AM-LCD: below Active Matrix LCD, abbreviated as liquid crystal table market value), in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, has the best resolution and video performance. It is attracting attention.

The liquid crystal display includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display, the common electrode and the pixel electrode are caused by an electric field applied up and down. It is excellent in the characteristics, such as transmittance | permeability and aperture ratio, by the method of driving a liquid crystal.

However, the liquid crystal drive due to the electric field applied up and down has a disadvantage that the viewing angle characteristics are not excellent.

Accordingly, a transverse field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG. 1.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other, and the liquid crystal layer 11 is interposed between the upper and lower substrates 9, 10. It is.

The common electrode 17 and the pixel electrode 30 are formed on the lower substrate 10 on the same plane. In this case, the liquid crystal layer 11 is formed by the common electrode 17 and the pixel electrode 30. It is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views illustrating operations of on and off states of a general transverse electric field type liquid crystal display device, respectively.

First, referring to FIG. 2A, which illustrates an arrangement of liquid crystals in an on state where a voltage is applied, a phase change of a liquid crystal 11a at a position corresponding to the common electrode 17 and the pixel electrode 30 is performed. Although the liquid crystal 11b positioned in the section between the common electrode 17 and the pixel electrode 30 is formed by the horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, It is arranged in the same direction as the horizontal electric field (L). That is, in the transverse electric field type liquid crystal display device, since the liquid crystal moves by the horizontal electric field, the viewing angle is widened.

Therefore, when viewed from the front, the transverse electric field type liquid crystal display device can be seen in the up / down / left / right directions without inversion phenomenon even in about 80 to 85 degrees.

Next, referring to FIG. 2B, since no voltage is applied to the liquid crystal display, a horizontal electric field is not formed between the common electrode and the pixel electrode, so that the arrangement state of the liquid crystal layer 11 does not change.

However, such a transverse field type liquid crystal display device has an advantage of improving the viewing angle, but has a disadvantage of low aperture ratio and low transmittance.

Therefore, in order to characterize the shortcomings of the transverse electric field type liquid crystal display, a fringe field switching mode LCD is characterized in that the liquid crystal is operated by a fringe field.

3 is a cross-sectional view of a portion cut through a central portion of one pixel area of a conventional fringe field switching mode liquid crystal display array substrate.

As shown, the conventional fringe field switching mode liquid crystal display array substrate 41 has a plurality of pixel regions (not shown) intersecting with each other at a lower portion and an upper portion thereof through a gate insulating layer 45 to define a gate wiring. (Not shown) and data lines 47 are formed, and each of the pixel regions (not shown) is connected to the gate and data lines (not shown) 47 and a thin film transistor (not shown) is formed.

In addition, the pixel electrode 55 in the form of a plate is formed in each pixel region (not shown) on the gate insulating layer 45 to contact the drain electrode (not shown) of the thin film transistor. In this case, the pixel electrode 55 is formed on the same layer as the data line 47, that is, the gate insulating layer 45, and the data line 47 is prevented from being shorted with the data line 47. It is formed at regular intervals.

In addition, a protective layer 60 is formed on the front surface of the data line 47 and the pixel electrode 55 as an inorganic insulating material, and corresponds to each pixel region (not shown) on the front surface of the protective layer 60. Thus, the common electrode 65 is spaced apart from each other and has a plurality of openings (oa) having a bar shape.

The conventional fringe field switching mode liquid crystal display array substrate 41 having such a cross-sectional configuration has a structure in which the common electrode 65 is positioned at the top and formed on the entire display area, and thus corresponds to the data line 47. Also, the common electrode 65 is formed to overlap with the protective layer 60.

Accordingly, the data line 47, the protective layer 60, and the common electrode 67 overlap each other to form a parasitic capacitor, and the protective layer is an inorganic insulating material having a relatively high dielectric constant and has a thickness of about 2000 μs. Since the parasitic capacitor generated by the data line 47 and the common electrode 47 overlap each other through the protective layer, the load is increased on the common electrode 65, and finally, the power consumption is increased. I'm making it.

In addition, since the data line 47 and the pixel electrode 55 are formed on the same layer, the data line has a spaced interval of about 3 μm to 5 μm so as to prevent a short circuit caused by a patterning error during the manufacturing process. Although 47 and the pixel electrode 55 are disposed, gradation defects that cause vertical crosstalk and upper and lower luminance differences are caused by coupling between the pixel electrode 55 and the data line 47 during frame inversion driving. I'm doing it.

The present invention has been made to solve the problems of the conventional array substrate for a fringe field switching mode liquid crystal display device, and to minimize the parasitic capacitance between the data line and the common electrode to reduce the power consumption, and the data line and It is an object of the present invention to provide an array substrate for a fringe field switching mode liquid crystal display device capable of minimizing coupling between pixel electrodes to suppress crosstalk and gradation defects.

According to an exemplary embodiment of the present invention, an array substrate for a fringe field switching mode liquid crystal display device includes: a gate wiring extending in one direction on a transparent substrate; A gate insulating film formed over the gate wiring; A data line over the gate insulating layer, the data line crossing the gate line and defining a pixel area; A thin film transistor electrically connected to the gate line and the data line and formed near an intersection point of the two lines; A first protective layer formed of an organic insulating material over the substrate over the thin film transistor and the data line; A common electrode formed on the entire surface of the substrate over the first passivation layer and having a first hole exposing the first passivation layer in a portion corresponding to the drain electrode of the thin film transistor; A second passivation layer on the front surface of the substrate, the second passivation layer having a planar area smaller than the first hole and having a drain contact hole penetrating inside the first hole to expose the drain electrode; And a pixel electrode formed on the second protective layer in contact with the drain electrode through the drain contact hole and formed in the pixel area, and having a plurality of bar-shaped openings spaced apart from each other.

The organic insulating material is benzocyclobutene (BCB) or photo acryl, and the second protective layer is made of silicon oxide (SiO ₂ ) or silicon nitride (SiNx), which is an inorganic insulating material. The electrode and the pixel electrode are made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials.

In addition, the first protective layer is formed having a thickness of 4000 kPa to 30000 kPa, and the second protective layer is formed having a thickness of 1500 kPa to 2500 kPa.

In addition, the pixel electrode, the plurality of openings provided therein, and the data line may be symmetrically bent based on an imaginary line parallel to the gate line passing through the central portion of the pixel area.

In addition, the pixel electrode may be formed such that both ends thereof overlap the data line.

The array substrate for the fringe field switching mode liquid crystal display device according to the present invention is formed of an organic insulating material having a relatively low dielectric constant and formed to have a thicker thickness than a protective layer made of a conventional inorganic insulating material. Minimizing the parasitic capacitance between the data line and the common electrode has the effect of reducing the power consumption.

In addition, even if the protective layer is thickly formed as an organic insulating material, the strength of the fringe field according to the voltage applied between the common electrode and the pixel electrode does not change as in the prior art. Minimizing the coupling between these two components has the effect of suppressing vertical crosstalk and gradation defects.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention. Although not shown in the drawings for convenience of description, an area in which a plurality of pixel areas are formed is defined as a display area, and an area outside the display area is referred to as a non-display area, and an area where a thin film transistor is formed is defined as a switching area.

As illustrated, a plurality of gate wires 105 are formed in the display area and extend in a first direction, and extend in a second direction orthogonal to the first direction and include a plurality of pixel areas P together with the gate wires. A large number of data wires 130 are defined.

In addition, the gate line 105 and the data line 130 are connected to the inside of each of the plurality of pixel regions P or to boundaries of the pixel regions P, and the gate electrode 108 and the gate insulating layer (not shown). And a semiconductor layer (not shown) consisting of an active layer (not shown) of pure amorphous silicon and an ohmic contact layer (not shown) of impurity amorphous silicon, and source and drain electrodes 133 and 136 spaced apart from each other. The thin film transistor Tr is formed. In this case, although the separation region (hereinafter, referred to as a channel region) between the source and drain electrodes 133 and 136 forms a '-' shape, the channel region may be modified in various forms. have. For example, when the source electrode 133 is formed in a 'U' shape, and the drain electrode 136 is formed to be inserted into an opening of the 'U' type source electrode 133, the channel region is formed of 'U'. Form.

In addition, although the thin film transistor Tr is formed on the boundary of the pixel region P and a part of the pixel region P in the drawing, the semiconductor layer (not shown) and the source and drain electrodes 133 and 136 are shown. ) May be formed to completely overlap the gate wiring 105 to be formed at the boundary of each pixel region P, thereby improving the aperture ratio.

On the other hand, the thin film transistor Tr and the data line 130 have a relatively lower dielectric constant value than the inorganic insulating material, and overcome the step difference between the underlying components, and have a flat surface and have a first protective layer ( Not shown), and a common electrode (not shown) is formed on the entire surface of the display area above the first passivation layer (not shown). In this case, the common electrode (not shown) is patterned and removed corresponding to the drain electrode 136 in each pixel region P, so that the first hole 152 exposing the first protective layer (not shown) is provided. Is characteristic.

A second passivation layer (not shown) is formed on the common electrode as an inorganic insulating material, and the second passivation layer (not shown) passes through the first hole 152 to form the drain electrode. A drain contact hole 157 exposing 136 is provided.

In addition, a pixel electrode 160 having a plate shape in contact with the drain electrode 136 through the drain contact hole 157 is formed on the second passivation layer (not shown). Formed. In this case, a plurality of openings (oa) having a bar shape and spaced apart from each other by a predetermined interval are formed in the pixel electrodes 160.

Although not shown in the drawings, each pixel electrode may have a structure that is symmetrically bent with respect to an imaginary line extending in parallel with the gate line with respect to the center of each pixel region. In this case, the plurality of bar-shaped openings also have a structure bent with respect to the center portion thereof, and the data lines or the shape of the bars having the shape bent with respect to the center portion of each pixel region form a zigzag shape in the display area. It is characteristic.

Hereinafter, the cross-sectional structure of the array substrate for the fringe field switching mode liquid crystal display device according to the above-described embodiment and modification will be described.

5 is a cross-sectional view of a portion taken along the cutting line VV of FIG. 4. For convenience of description, a portion in which a thin film transistor, which is a switching element, is formed is defined as a switching region TrA.

As shown, a metal material having low resistance, for example aluminum (Al), is formed on the transparent insulating substrate 101 that forms the base of the array substrate 101 for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention. ), An aluminum alloy (AlNd), copper (Cu), copper alloy, chromium (Cr), molybdenum (Mo) is a metal material selected from the gate wiring extending in the first direction (not shown), A gate electrode 108 is formed in the switching region TrA in connection with the gate line.

In addition, a gate insulating film 115 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the entire surface of the substrate 101 over the gate wiring 105 and the gate electrode 108. have.

In the switching region TrA on the gate insulating layer 115, a semiconductor layer 120 including an active layer 120a of pure amorphous silicon and an ohmic contact layer 120b of impurity amorphous silicon is formed corresponding to the gate electrode 108. The source and drain electrodes 133 and 136 are spaced apart from each other above the semiconductor layer 120. In this case, the active layer 120a is exposed between the source and drain electrodes 133 and 136 spaced apart from each other.

In addition, an upper portion of the gate insulating layer (not shown) may include a data line 130 that crosses the gate line 105 and defines a pixel area P, extending in a second direction perpendicular to the first direction. . In this case, although the first and second dummy patterns 121a and 121b are formed under the data line 130 with the same material forming the semiconductor layer 120, the first and second dummy patterns are formed. Reference numerals 121a and 121b are due to the manufacturing method and may be omitted.

Meanwhile, the source electrode 133 of the thin film transistor Tr is formed to branch from the data line 130 to be connected to the data line 130.

Next, an organic insulating material, for example, benzocyclobutene (BCB) or photo acryl, which covers the data line 130 and the thin film transistor Tr and has a dielectric constant having a lower dielectric constant than that of the inorganic insulating material. The first passivation layer 140 is formed on the entire surface of the substrate 101.

In addition, a common electrode 150 formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the entire surface of the substrate 101 on the first protective layer 140. It is. In this case, the common electrode 150 exposes the first hole 152 that exposes the first passivation layer 140 positioned on the drain electrode 136 to correspond to the drain electrode 136 of each pixel region P. FIG. It is characterized by having a).

Next, an inorganic insulating material, such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is formed on the entire surface of the substrate 101 over the common electrode 150 having the first hole 152 corresponding to each pixel area P. FIG. The second protective layer 155 made of) is formed. In this case, the second passivation layer 155 and the first passivation layer 140 have a planar smaller than the first hole 152 corresponding to each of the first holes 152 and the first hole 152. A drain contact hole 157 is formed through the hole to expose the drain electrode 136. The first hole 152 and the drain contact hole 157 are formed to have this shape, and the drain contact hole 157 is not formed without the first hole 152 having a larger planar area than the drain contact hole 157. If only the side surface of the drain contact hole 157 is formed, the side surface of the common electrode 150 is exposed, in this state and the drain electrode 136 through the drain contact hole 157 This is to prevent the short circuit between the common electrode 150 and the pixel electrode 160 in the drain contact hole 157 when the pixel electrode 160 is in contact with the pixel electrode 160.

Next, each of the pixel regions P is disposed on the second protective layer 155 provided with the drain contact holes 157 through the drain contact hole 157 corresponding to each pixel region P. By forming the pixel electrode 160 in contact with 136, the array substrate 101 for a fringe field switching mode liquid crystal display device according to the present invention is completed. In this embodiment, the pixel electrode 160 is formed inside the pixel region P by being spaced apart without overlapping the end of the data line 130 in the drawing. The pixel electrode 160 may be formed such that an end thereof is positioned above the data line 130. In this case, the effect of improving the aperture ratio is obtained.

According to the modified example, the data line 130 and the pixel electrode 160 are not formed on the same layer, and the first protective layer 140 is formed between the data line 130 and the pixel electrode 160. And the common electrode 150 and the second protective layer 155 are formed.

On the other hand, in the case of the array substrate 101 for the fringe field switching mode liquid crystal display device according to the embodiment and the modification of the present invention having the above-described cross-sectional structure, the common electrode 150 is particularly connected to the pixel electrode 160 and the data line. Since the coupling between the data lines 130 and the pixel electrode 160 is hardly generated even when the inversion driving is performed, the coupling between the pixel electrodes 160 and the data wire 130 is performed. Vertical crosstalk and gradation defect due to

In addition, in the array substrate 101 for a fringe field switching mode liquid crystal display device according to an exemplary embodiment and a modification of the present invention, the parasitic capacitance generated by the overlapping of the data line 130 and the common electrode 160 is also the first protection. It can be reduced by forming the layer 140 as an organic insulating material. In the case of the organic insulating material, the dielectric constant value is lower than that of the inorganic insulating material, and since the parasitic capacitance is proportional to the dielectric constant value of the material forming the dielectric layer, the first protective layer 140 is formed to have the same thickness as in the prior art. Relatively parasitic doses can be reduced. Therefore, an increase in power consumption due to an increase in load due to parasitic capacitance generated by overlapping the data line 130 and the common line 160 can be suppressed.

Hereinafter, a method of manufacturing an array substrate for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention having the above-described structural features will be described with reference to FIGS. 4 and 5. In this case, for convenience of description, an area in which the thin film transistor Tr is formed in each pixel area P is defined as a switching area TrA.

First, a first metal material having low resistance on the transparent insulating substrate 101, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, chromium (Cr), molybdenum (Mo) A first metal layer (not shown) by depositing on the selected material DMo surface, and subsequently applying a photoresist, exposing using a photo mask, developing the exposed photoresist, etching the first metal layer (not shown), and A plurality of gate wirings 105 extending in the first direction are formed by patterning a first metal layer (not shown) to advance a mask process including a series of unit processes such as strips of photoresist, At the same time, a gate electrode 108 connected to the gate line 105 is formed in the switching region TrA.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the gate wiring 105 and the gate electrode 108 to form a gate insulating film 115 on the entire surface of the substrate 101. .

Next, a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown) are formed on the gate insulating layer 115, and a second metal material such as aluminum (not shown) is formed on the impurity amorphous silicon layer (not shown). A second metal layer (not shown) is formed by depositing one of Al), aluminum alloy (AlNd), molybdenum (Mo), copper (Cu), and copper alloy. Subsequently, first and second photoresist patterns (not shown) having different thicknesses are formed by forming a photoresist layer (not shown) on the second metal layer (not shown), and performing and developing halftone or diffraction exposure. To form.

Next, the gate wiring line may be formed by etching and removing the second metal layer (not shown) and impurities and lower pure silicon layers (not shown) exposed to the outside of the first and second photoresist patterns (not shown). A plurality of data lines 130 are formed to intersect 105 and extend in a second direction to define a plurality of pixel regions P, and at the same time, a drain connected to the data lines 130 in the switching region TrA. An ohmic contact pattern (not shown) and an active layer 120a sequentially stacked under the pattern (not shown) are formed.

 Next, the second photoresist pattern (not shown) having a thin thickness is removed, whereby the ohmic contact pattern (not shown) positioned below and in the center of the newly exposed source drain pattern (not shown) is removed. Etching and removal remove the source and drain electrodes 133 and 136 from each other, and form an ohmic contact layer 120b exposing the active layer 120a below the source and drain electrodes 133 and 136. do. In this case, the active layer 120a and the ohmic contact layer 120b form the semiconductor layer 120, and the gate electrode 108, the gate insulating layer 115, and the semiconductor layer (sequentially stacked in the switching region TrA). 120, the source and drain electrodes 133 and 136 spaced apart from each other form a thin film transistor Tr.

Meanwhile, in the embodiment, the semiconductor layer 120, the data line 130, and the source and drain electrodes 133 and 136 are simultaneously formed through one mask process, thereby forming the semiconductor layer 120 under the data line 130. Although the first and second dummy patterns 121a and 121b formed of the same material forming the layer 120 are formed, the semiconductor layer 120, the data line 130, the source and drain electrodes 133, 136 may be formed through different mask processes. In this case, the first and second dummy patterns 121a and 121b made of a semiconductor material are not formed under the data line 130.

Next, an organic insulating material, for example, benzocyclobutene (BCB) or photo acryl, is coated on the thin film transistor Tr and the data line 130 in front of a bar, for example. The first protective layer 140 having a thickness of about 4000 kPa to about 30000 kPa is formed by coating through a coating apparatus, a slit coating apparatus, and a spin coating apparatus. At this time, the thickness of the first protective layer 140 is formed by using a coating apparatus (not shown), whether the thickness is formed thick or thin in the range of about 4000 ~ 30000 Å, the formation time is the same, the structure As the thickness thereof increases, the intensity of the fringe field between the pixel electrode and the common electrode may be freely changed within the aforementioned range when the same voltage is applied.

Next, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface of the substrate 101 on the first passivation layer 140, and the mask process is performed. Patterning to form a common electrode 150 having a first hole 152 that exposes the first passivation layer 140 corresponding to the drain electrode 136 formed in each pixel region P. Referring to FIG.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the common electrode 150 having the first hole 152 by using a chemical vapor deposition apparatus (not shown). The second passivation layer 155 is formed on the entire surface of the substrate 101. At this time, it is preferable that the thickness of the second protective layer 155 is about 1500 kPa to about 2500 kPa. Since the thickness of the second passivation layer 155 is a gap between the common electrode 150 and the pixel electrode 160, when the gap between the two electrodes 150 and 160 increases, the strength of the fringe field becomes relatively weak. It is preferable to have thickness within the above-mentioned range. Since the deposition of the inorganic insulating material takes a longer time as the thickness of the inorganic insulating material is formed, it may be desirable to form the second protective layer 155 to have the above-described thickness range in terms of productivity.

Subsequently, the second protective layer 155 and the first protective layer 140 are patterned in correspondence to the portion where the first hole 152 is formed to have a planar area smaller than that of the first hole 152 and the first hole. A drain contact hole 157 is formed through the 152 to expose the drain electrode 136. In this case, a first hole 152 is provided in the common electrode 150, and the drain contact hole 157 is formed inside the first hole 152 so that the common electrode 150 is the drain contact hole 157. ) Is not exposed from the inner surface.

Next, a transparent conductive material layer, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the second protective layer 155 having the drain contact hole 157. (Not shown) is formed. Subsequently, the transparent conductive material layer (not shown) is patterned to contact the drain electrode 136 of the thin film transistor Tr through the drain contact hole 157 in each pixel region P. The array substrate 101 for the fringe field switching mode liquid crystal display according to the exemplary embodiment of the present invention is completed by forming the pixel electrode 160 having a plurality of openings (oa) in a bar shape spaced apart from each other.

Meanwhile, in the modified example in which the data line and the plurality of openings are bent, the data line is patterned to have a zigzag shape in the forming of the data line, and the pixel line is bent based on the center of each pixel region in the forming of the pixel electrode. It can be formed to have a double domain structure by patterning to have a structure.

Meanwhile, the present invention is not limited to the above-described embodiments and modifications, and various changes and modifications are possible without departing from the spirit of the present invention.

1 is a cross-sectional view schematically showing a part of a general transverse electric field type liquid crystal display device.

2A and 2B are cross-sectional views showing operations of on and off states of a general transverse electric field type liquid crystal display device, respectively.

3 is a cross-sectional view of one pixel area of an array substrate of a conventional fringe field switched mode liquid crystal display device.

4 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of a portion cut along the cutting line VV of FIG. 4. FIG.

<Brief description of the main parts of the drawing>

101: array substrate 108: gate electrode

115: gate insulating film 120: semiconductor layer

120a: active layer 120b: ohmic contact layer

130: data wiring 133: source electrode

136: drain electrode 140: first protective layer

150: common electrode 152: first hole

155: second protective layer 157: drain contact hole

160: pixel electrode

oa: opening part P: pixel area

Tr: Thin Film Transistor TrA: Switching Area

Claims (5)

A gate wiring formed extending in one direction on the transparent substrate; A gate insulating film formed over the gate wiring; A data line over the gate insulating layer, the data line crossing the gate line and defining a pixel area; A thin film transistor electrically connected to the gate line and the data line and formed near an intersection point of the two lines; A first protective layer formed of an organic insulating material over the substrate over the thin film transistor and the data line; A common electrode formed on the entire surface of the substrate over the first passivation layer and having a first hole exposing the first passivation layer in a portion corresponding to the drain electrode of the thin film transistor; A second passivation layer on the front surface of the substrate, the second passivation layer having a planar area smaller than the first hole and having a drain contact hole penetrating inside the first hole to expose the drain electrode; A pixel electrode formed in the pixel region in contact with the drain electrode through the drain contact hole on the second passivation layer, and having a plurality of bar-shaped openings spaced at predetermined intervals therein; Fringe field switching mode liquid crystal display array substrate comprising a. The method of claim 1, The organic insulating material is benzocyclobutene (BCB) or photo acryl, The second protective layer is made of silicon oxide (SiO ₂ ) or silicon nitride (SiNx), which is an inorganic insulating material. And the common electrode and the pixel electrode are made of indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive materials. The method of claim 1, And the first protective layer has a thickness of 4000 kPa to 30000 kPa, and the second protective layer has a thickness of 1500 kPa to 2500 kPa. The method of claim 1, Fringe field switching mode, wherein the pixel electrode, the plurality of openings and the data lines are symmetrically bent based on an imaginary line parallel to the gate line passing through the central portion of the pixel region. Array substrate for liquid crystal display device. The method according to claim 1 or 4, And the pixel electrode is formed so that both ends thereof overlap with the data line.

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