KR20110028135A - Chip-type electric double layer capacitor and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A chip-type electric double layer capacitor and a manufacturing method thereof are provided to simplify the surface mounting process by applying the batch mounting technology using the solder method. CONSTITUTION: An external case(110) is made of the insulating resin and has the receiving space inside. A first external terminal(120a) and a second external terminal are buried in the case. The first and second external terminals connect the outer surface of the external case and the receiving space inside. Glue layers(115a, 115b) cover the boundary face of the first and second external terminals and the external case.

Description

Chip-type electric double layer capacitor and method for manufacturing the same

The present invention relates to a chip type electric double layer capacitor and a method of manufacturing the same, and more particularly, to a chip type electric double layer capacitor capable of miniaturization and light weight and a method of manufacturing the same.

The supply of stable energy is becoming an important factor in various electronic products such as information and communication devices. In general, this function is performed by a capacitor. In other words, the capacitor collects and discharges electricity from circuits of information and communication devices and various electronic products, thereby stabilizing electric flow in the circuit. A typical capacitor has a very short charge and discharge time, a long lifespan, and a high output density, but a small energy density limits its use as a storage device.

In order to overcome these limitations, a new category of capacitors, such as electric double layer capacitors, which have a short charge / discharge time and a high output density, have been developed.

Electric Double Layer Capacitor is an energy storage device that uses a pair of charge layers (electrode layers) with different polarities. It is capable of continuous charging and discharging, and has high energy efficiency and high output and durability compared to other capacitors. And there is an advantage of excellent stability. Accordingly, recently, an electric double layer capacitor capable of charging and discharging with a large current has been promising as a power storage device having a high charge / discharge frequency such as an auxiliary power supply for a mobile phone, an auxiliary power supply for an electric vehicle, an auxiliary power supply for a solar cell, and the like.

The basic structure of an electric double layer capacitor is composed of an electrode, an electrolyte, a current collector, and a separator having a relatively large surface area, such as a porous electrode. The principle of operation is the electrochemical mechanism generated by applying voltage to move ions in the electrolyte along the electric field and adsorb to the electrode surface.

A general scheme for surface mount technology (SMT) of such electric double layer capacitors is to mount brackets on the circuit boards by welding brackets above and below the electric double layer capacitors.

However, the electric double layer capacitor of this structure is relatively large in thickness, and the thickness is made thicker by additional structures (brackets, etc.) necessary for surface mounting. In the case of using such an electric double layer capacitor, it is difficult to manufacture a high-capacity product due to the increase in thickness, and furthermore, it becomes a factor of an increase in product cost due to the occurrence of additional processes.

SUMMARY OF THE INVENTION An object of the present invention is to provide a chip type electric double layer capacitor capable of miniaturization and weight reduction and surface mounting without an additional structure, and a method of manufacturing the same.

The present invention is an embodiment for solving the above problems, the outer case having a storage space therein made of an insulating resin; First and second external terminals embedded in the outer case and connecting the outer surface of the outer case and the inside of the storage space; An adhesive layer formed to cover a boundary surface between the first and second external terminals and the exterior case; And an electric double layer capacitor cell mounted in the storage space and electrically connected to a region provided in the storage space among the first and second external terminals.

The first and second external terminals may be embedded in the outer case to insert injection molding.

The first and second external terminals may have buried region extensions.

The adhesive layer may include an epoxy resin.

The adhesive layer may be formed to cover an area provided on an outer surface of the outer case of the first and second outer terminals and an interface between the outer case.

 The adhesive layer may be formed to cover an interface between the outer case and the region provided in the storage space among the first and second external terminals.

The first and second external terminals may be formed on the same surface of the outer case.

The outer case may have a storage space having an upper surface open, a lower case including first and second external terminals, and an upper cap mounted to the lower case to cover the storage space.

The lower case and the upper cap may be mounted by an adhesive layer.

The insulating resin may be polyphenylene sulfide or liquid crystal polymer.

The electric double layer capacitor cell may include first and second current collectors, first and second electrodes connected to the first and second current collectors, and ion permeable separators formed between the first and second electrodes, respectively. Can be.

The area provided to the accommodation space of the first and second external terminals and the electric double layer capacitor cell may be connected by welding or ultrasonic welding.

In the electric double layer capacitor cell, one or more first and second current collectors, first and second electrodes, and a separator may be continuously stacked.

In the electric double layer capacitor cell, first and second electrodes may be wound.

In accordance with another aspect of the present invention, an insulating surface and an inner surface of the outer case and an inner space of the outer case are formed while the insulating resin and the first and second external terminals are integrally molded to have an open space. Forming a lower case to fill the first and second external terminals connecting the first and second external terminals; Forming an adhesive layer to cover the interface between the first and second external terminals and the outer case; Mounting an electric double layer capacitor cell in the storage space so as to be electrically connected to an area provided in the storage space among the first and second external terminals; And mounting an upper cap on the lower case so as to cover the accommodation space.

The lower case may be formed by insert injection molding. Mounting the upper cap on the lower case may include forming an adhesive layer between the lower case and the upper cap.

The chip type electric double layer capacitor according to the present invention has a high space utilization because the external case and the external terminal are integrally formed. Accordingly, the electric double layer capacitor can be miniaturized, reduced in weight, and high in capacity.

It is also possible to mount the surface as a chip-type electric double layer capacitor itself without additional structure. Solder-based batch mounting techniques can be applied to simplify the surface mount process.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. In addition, embodiments of the present invention are provided to more completely describe the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.

1A is a schematic perspective view showing a chip type electric double layer capacitor according to an embodiment of the present invention, and FIG. 2A is a schematic cross-sectional view showing a chip type electric double layer capacitor taken along line II ′ of FIG. 1A.

1A and 2A, the chip type electric double layer capacitor 100 according to the present embodiment has a storage space therein, and is disposed in an exterior case 110 made of an insulating resin and a storage space of the exterior case 110. Electrical double layer capacitor cells.

The first and second external terminals 120a and 120b are embedded in the outer case 110, and have a structure connecting the outer surface of the outer case 110 to the inside of the storage space. More specifically, the first and second external terminals 120a and 120b are entirely embedded in the outer case, but one area is exposed to the outer surface of the outer case, and the other area is exposed to the storage space to expose the outer case. It has a structure for connecting the outer surface and the interior of the storage space.

The exterior case 110 may be integrally molded with the first and second external terminals 120a and 120b by insert injection molding. For example, the mold may be prepared by preparing a mold having a desired exterior case shape, disposing first and second external terminals in the mold, and injecting an insulating resin into the mold. In this case, the first and second external terminals may be disposed to have one region exposed to the outer surface of the outer case and another region exposed to the storage space of the outer case.

An electrical double layer capacitor cell is disposed in the storage space of the outer case 110, and the electrical double layer capacitor cell is electrically connected to an area provided in the storage space among the first and second external terminals 120a and 120b. One region exposed to an outer surface of an outer case of the first and second external terminals 120a and 120b may be a means for electrically connecting an electric double layer capacitor cell to an external power source.

In addition, the chip type electric double layer capacitor according to the present embodiment includes adhesive layers 115a and 115b formed to cover the interface between the first and second external terminals 120a and 120b and the outer case. More specifically, as shown in FIGS. 1A and 2A, the adhesive layers 115a and 115b may be formed to cover the interface provided between the outer surface of the outer case and the area provided as the outer surface of the outer case among the first and second outer terminals. have.

Although not shown, the adhesive layer may be formed to cover the interface between the outer case and the area provided as a storage space among the first and second external terminals.

Although the external terminal and the outer case are integrated, fine gaps may occur due to heterogeneity between materials, and electrolyte may be discharged by the minute gaps. That is, when the electrolyte is leaked during the manufacturing and use of the chip type electric double layer capacitor cell, the reliability may be lowered and the life may be shortened.

Therefore, when the adhesive layers 115a and 115b are formed on the interface between the first and second external terminals and the outer case, the leakage of the electrolyte may be prevented.

The adhesive layer can be formed using an epoxy resin. The epoxy resin is not particularly limited, and for example, bisphenol A epoxy resin, bisphenol novolac epoxy resin, or the like can be used as the multifunctional epoxy resin having two or more epoxy groups in the molecule. The epoxy resin may include a crosslinking agent.

As shown in FIGS. 1A and 2A, the first and second external terminals 120a and 120b may be formed on the same surface 111 of the exterior case 110. In addition, although not shown, the first and second external terminals may be formed on different surfaces of the outer case, respectively.

When the first and second external terminals are formed on the same surface 111, the chip type electric double layer capacitor 100 may be surface mounted (SMT) by itself without an additional structure.

The formation position of the first and second external terminals is not particularly limited, and the first and second external terminals 120a and 120b may be formed at both ends of the same surface 111 of the outer case. The first and second external terminals may extend from side ends of the same surface 111 of the outer case to a side surface connected to the same surface 111. When the chip type electric double layer capacitor is surface mounted, the areas of the first and second external terminals extending laterally may be utilized for the performance test of the chip type electric double layer capacitor.

1B is a schematic perspective view illustrating a chip type electric double layer capacitor 200 according to another embodiment of the present invention. As shown in FIG. 1B, the first and second external terminals 220a and 220b may be formed on the same surface 211 of the exterior case 210, and may be formed in the center of the same surface. 2 includes adhesive layers 215a and 215b formed to cover the interface between the external terminals 220a and 220b and the exterior case 210.

The electric double layer capacitor cell disposed in the storage space of the outer case 110 is electrically connected to an area provided as the storage space among the first and second external terminals 120a and 120b. The connection between the electric double layer capacitor cell and the region provided as an accommodation space among the first and second external terminals 120a and 120b may be by welding or ultrasonic welding.

The electric double layer capacitor cell includes first and second current collectors 130a and 130b, first and second electrodes 140a and 140b connected to the first and second current collectors, and the first and second electrodes, respectively. It may include an ion-permeable separation membrane 150 formed therebetween.

The first and second current collectors 130a and 130b are conductive sheets for transmitting electrical signals to the first and second electrodes 140a and 140b, respectively, and may be formed of a conductive polymer, a rubber sheet, or a metallic foil. Can be done. In this embodiment, the electric double layer capacitor cell is electrically connected to the first and second external terminals 120a and 120b by the first and second current collectors 130a and 130b. The shape of the first and second current collectors 130a and 130b may be appropriately changed to be electrically connected to the first and second external terminals 120a and 120b. This change in shape can be affected by the shape or size of the electrical double layer capacitor cell.

As shown in FIG. 2A, the first current collector 130a may have a shape in which a portion of the first current collector 130a is bent to be connected to the first external terminal 120a. The first and second current collectors 130a and 130b may be formed. ) May be directly connected to the first and second external terminals 120a and 120b.

Although not shown, the first and second current collectors may be electrically connected to the first and second external terminals through appropriate connection means.

In addition, although not shown, an insulating layer may be formed between one surface of the outer case in which the first and second external terminals 120a and 120b are embedded and the second current collector 130b in contact therewith. .

When the electric double layer capacitor cell does not include the first and second current collectors 130a and 130b, the first and second external terminals through which the first and second electrodes 130a and 130b are exposed to the storage space. It may be electrically connected to the first surfaces of 120a and 120b.

The first and second electrodes 140a and 140b may use a polarizable electrode material, and may use activated carbon having a relatively high specific surface area. The first and second electrodes 140a and 140b may be made of a solid sheet of an electrode material mainly composed of powdered activated carbon, or the electrode material slurry may be fixed on the first and second current collectors 130a and 130b. It can manufacture.

The separator 150 may be made of a porous material to allow the transmission of ions. Although not limited to this, for example, a porous material such as polypropylene, polyethylene, or glass fiber may be used.

In the present embodiment, the outer case 110 has a storage space with an upper surface open, and the lower case 110a and the lower housing so as to cover the first case and the second outer terminal (120a, 120b) and the receiving satin It may be made of an upper cap (110b) mounted on the case (110a).

The lower case 110a and the upper case 110b may be coupled by an adhesive layer. P of FIG. 2A shows the joining area of the lower case and the upper case.

In addition, the outer case 110 is made of an insulating resin, the insulating resin may be polyphenylene sulfide (PPS) or a liquid crystal polymer (LCP). Accordingly, the chip type electric double layer capacitor 100 may protect the internal structure during the surface mounting process performed at a high temperature (about 240-270 ° C.).

As described above, the chip type electric double layer capacitor according to the present embodiment has a structure in which the first and second external terminals 120a and 120b are embedded in the exterior case 110 and have high space utilization. Accordingly, the stacking degree of the electric double layer capacitor cell mounted therein can be increased.

2B is a schematic cross-sectional view of only a lower case of a chip type electric double layer capacitor according to another embodiment of the present invention. The components different from the above-described embodiments will be described mainly, and detailed descriptions of the same components will be omitted.

In the present embodiment, the first and second external terminals 120a and 120b are embedded in the lower case 110b and are provided as the storage spaces of the first and second external terminals 120a and 120b. And an area exposed to an external area of the outer case.

Although the first and second external terminals 120a and 120b and the external case 110b are integrally formed, the first and second external terminals 120a and 120b are embedded in the external case 110b. Due to the heterogeneity of the liver, minute gaps may occur, and the electrolyte may be discharged by the minute gaps.

When electrolyte is leaked during the manufacturing and use of the chip type electric double layer capacitor, reliability may be reduced and life may be shortened.

Therefore, it is preferable that the first and second external terminals and the outer case have a wide contact area to form a long electrolyte discharge path.

Accordingly, the first and second external terminals may be formed to have the buried region extension part D. The shape of the buried region extension D is not particularly limited, and as shown in FIG. 2B, the first and second external terminals are manufactured in a plate shape, a part of the plate shape is provided as a storage space, and It may have a bent shape to be provided to the outer region. Accordingly, the buried regions of the first and second external terminals and the exterior resin can be expanded.

2C is a schematic cross-sectional view of only a lower case of a chip type electric double layer capacitor according to another embodiment of the present invention. The components different from the above-described embodiments will be described mainly, and detailed descriptions of the same components will be omitted.

As shown in FIG. 2C, the first and second external terminals have an area provided as an accommodation space and an area provided as an external area, and have a buried area extension D. As shown in FIG. The buried region extension part D may have various shapes such that an area in contact with the exterior resin is wide.

3 is a schematic cross-sectional view showing a chip type electric double layer capacitor 300 according to another embodiment of the present invention. The components different from the above-described embodiments will be described mainly, and detailed descriptions of the same components will be omitted.

Referring to FIG. 3, an electric double layer capacitor cell has a structure in which one or more first and second current collectors, first and second electrodes, and a separator are sequentially stacked. The electric double layer capacitor according to the present embodiment may include an electric double layer capacitor cell having a multi-layer structure due to high space utilization.

More specifically, the first first current collector 331a and the second current collector 331b are connected to the first and second external terminals 320a and 320b, respectively. The first first electrode 341a is connected to the first first current collector 331a, and the first second electrode 341b is connected to the first second current collector 331b, and the first first electrode and the second electrode are connected to each other. A first ion permeable separator 351 is formed between the 341a and 341b to form one unit cell.

In addition, a second first electrode 342a is connected to the first first current collector 331a, and a second second electrode 342b is connected to the second second current collector 332b. A second ion permeable separator 352 is formed between the two electrodes 342a and 342b to form another unit cell. The second second current collector 332b is bent and electrically connected to the second external terminal 320b.

In addition, a third second electrode 343b is connected to the second second current collector 332b, a third first electrode 343a is connected to the second first current collector 332a, and the third first electrode and the first A third ion permeable separator 353 is formed between the two electrodes 343a and 343b to form another unit cell. The second first current collector 332a is bent and electrically connected to the second external terminal 320b.

As in the present embodiment, higher electrical capacitance can be obtained by stacking a plurality of unit cells. In addition, although not shown, an insulating material may be coated on the outside of the unit cell stack to prevent an unintended short circuit.

In the present embodiment, the first and second external terminals 320a and 320b are embedded in one surface 311 of the outer case, but have a thickness greater than that of the outer case, and protrude into an outer region of the outer case.

4 and 5 are schematic cross-sectional views showing an electric double layer capacitor cell 460 and a chip type electric double layer capacitor 400 including the same according to another embodiment of the present invention. The components different from the above-described embodiments will be described mainly, and detailed descriptions of the same components will be omitted.

4 and 5, the electric double layer capacitor cell 460 according to the present embodiment has a form in which first and second electrodes are wound. More specifically, the first electrode 440a, the first separator 450a, the second electrode 440b, and the second separator 450b are sequentially stacked, and the stack is wound to form the electric double layer capacitor cell 460. Configure. A first current collector 430a and a second current collector 430b are connected to the first electrode 440a and the second electrode 440b, respectively.

The electric double layer capacitor cell 460 is disposed in a storage space of the outer case 410, and the first current collector 430a and the second current collector 430b are bent to form first and second external terminals 420a, respectively. 420b).

In the present embodiment, the first and second external terminals 420a and 420b are embedded in one surface 411 of the outer case, but have a thickness greater than that of the outer case, and protrude into the storage space of the outer case.

6 (a) to 6 (c) are cross-sectional views for explaining a method for manufacturing a chip type electric double layer capacitor according to an embodiment of the present invention.

As shown in FIG. 6 (a), the insulating resin and the first and second external terminals 120a and 120b are integrally molded to have an open space on the upper surface thereof, One surface is exposed to the outer area, and the first surface is formed to expose the lower case (110b).

The method of forming the lower case 110b is not particularly limited as long as the insulating resin and the first and second external terminals are integrally molded to embed the first and second external terminals in the insulating resin. For example, insert injection molding can be used.

More specifically, the first and second external terminals are disposed in a mold having a desired lower case shape, and the insulating resin is filled in the mold.

The first and second external terminals are arranged to have a structure connecting the outer surface of the lower case and the inside of the storage space formed in the lower case.

The insulating resin filled in the mold is solidified together with the first and second external terminals by cooling or crosslinking in the mold. Insulation resins having different materials and first and second external terminals are integrated according to insert molding.

Next, an adhesive layer is formed to cover the interface between the first and second external terminals and the outer case. As shown in FIG. 6A, the adhesive layers 115a and 115b may be formed to cover an interface provided between an outer surface of the outer case and an area provided among the first and second outer terminals. Although not shown, the adhesive layer may be formed to cover the interface between the outer case and the area provided as a storage space among the first and second external terminals.

Next, as illustrated in FIG. 6B, an electric double layer capacitor cell is mounted to be electrically connected to an area provided in the accommodation space among the first and second external terminals.

As described above, the electric double layer capacitor cell includes first and second current collectors 130a and 130b and first and second electrodes 140a and 140b connected to the first and second current collectors 130a and 130b, respectively. ) And an ion permeable separator 150 formed between the first and second electrodes 140a and 140b. The first and second current collectors 130a and 130b are electrically connected to an area provided in the storage space among the first and second external terminals 120a and 120b, and the first current collector 130a is bent. It may have a shape.

The connection of the first and second external terminals 120a and 120b and the first and second current collectors 130a and 130b may be performed by welding or ultrasonic welding. Although not limited thereto, the welding may use resistance welding or arc welding.

Next, as shown in (c), the upper cap (110a) is mounted on the lower case (110b) to cover the storage space. An electric double layer capacitor cell is mounted on the lower case 110b, and the electrolyte is filled. The electrolyte may be an aqueous electrolyte solution or a non-aqueous electrolyte solution.

Mounting of the lower case and the upper cap may be performed by the formation of an adhesive layer (not shown). That is, the adhesive layer may be applied to the P region of the lower case, and the upper cap may be mounted and bonded. In this way, the airtightness of the lower case and the upper cap is improved to protect the internal elements in the outer case.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

1 is a schematic perspective view showing a chip type electric double layer capacitor according to an embodiment of the present invention.

2A is a schematic cross-sectional view showing a chip type electric double layer capacitor according to one embodiment of the present invention.

2B is a schematic cross-sectional view of only a lower case of a chip type electric double layer capacitor according to another embodiment of the present invention.

2C is a schematic cross-sectional view of only a lower case of a chip type electric double layer capacitor according to still another embodiment of the present invention.

3 is a schematic cross-sectional view showing a chip type electric double layer capacitor according to another embodiment of the present invention.

4 is a schematic perspective view showing an electric double layer capacitor cell according to an embodiment of the present invention.

5 is a schematic cross-sectional view showing a chip type electric double layer capacitor according to still another embodiment of the present invention.

6 is a cross-sectional view illustrating a method of manufacturing a chip type electric double layer capacitor according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: chip type electric double layer capacitor 110: outer case

115a and 115b: adhesive layers 120a and 120b: first and second external terminals

      130a and 130b: first and second current collectors 140a and 140b: first and second electrodes

150: separator

Claims (17)

An exterior case having a storage space therein and made of an insulating resin; First and second external terminals embedded in the outer case and connecting the outer surface of the outer case and the inside of the storage space; An adhesive layer formed to cover a boundary surface between the first and second external terminals and the exterior case; And An electric double layer capacitor cell mounted in the storage space and electrically connected to an area provided in the storage space among the first and second external terminals; Chip type electric double layer capacitor comprising a. The method of claim 1, And the first and second external terminals are embedded in the outer case in insert injection molding. The method of claim 1, And the first and second external terminals have a buried region extension. The method of claim 1, And the adhesive layer comprises an epoxy resin. The method of claim 1, And the adhesive layer is formed to cover a region provided on an outer surface of an outer case of the first and second outer terminals and an interface of the outer case. The method of claim 1, The adhesive layer is a chip-type electric double layer capacitor, characterized in that formed to cover the interface between the area provided in the storage space of the first and second external terminals and the outer case. The method of claim 1, And the first and second external terminals are formed on the same surface of the outer case. The method of claim 1, The outer case has a storage space having an upper surface open, a chip type electric double layer capacitor, characterized in that the lower case including a first and second external terminals and an upper cap mounted to the lower case to cover the storage space. . The method of claim 8, And the lower case and the upper cap are mounted by an adhesive layer. The method of claim 1, The insulating resin is a chip type electric double layer capacitor, characterized in that the polyphenylene sulfide or liquid crystal polymer. The method of claim 1, The electric double layer capacitor cell includes first and second current collectors, first and second electrodes connected to the first and second current collectors, and an ion permeable separator formed between the first and second electrodes, respectively. Chip type electric double layer capacitor, characterized in that. The method of claim 1, And the area provided to the accommodation space of the first and second external terminals and the electric double layer capacitor cell are connected by welding or ultrasonic welding. The method of claim 1, The electric double layer capacitor cell is a chip type electric double layer capacitor, characterized in that one or more first and second current collectors, the first and second electrodes and separators are sequentially stacked. The method of claim 1, The electric double layer capacitor cell is a chip type electric double layer capacitor, characterized in that the first and second electrodes are wound. The insulating resin and the first and second external terminals are integrally molded to have a storage space with an open upper surface, and to fill the first and second external terminals connecting the external surface of the exterior case and the interior of the storage space. Forming a case; Forming an adhesive layer to cover an interface between the first and second external terminals and the outer case; Mounting an electric double layer capacitor cell in the storage space so as to be electrically connected to an area provided in the storage space among the first and second external terminals; And Mounting an upper cap on the lower case to cover the storage space; Method of manufacturing a chip-type electric double layer capacitor comprising a. The method of claim 15, Forming the lower case is a method of manufacturing a chip-type electric double layer capacitor, characterized in that performed by insert injection molding. The method of claim 15, Mounting the upper cap on the lower case comprises the step of forming an adhesive layer between the lower case and the upper cap.

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