KR20110013700A - Vertical channel type non-volatile memory device - Google Patents

Abstract

PURPOSE: A vertical channel type nonvolatile memory device is provided to easily control the off-current of a lower selection transistor by separately controlling the source region of a memory block. CONSTITUTION: A plurality of memory cells(MC) is respectively separated by an interlayer insulating film(21). The memory cell includes a channel(CH) and a gate electrode(22). The memory cells are serially connected between a lower selection transistor and an upper selection transistor. A source region(S) is in a parallel connection with a plurality of strings forming one memory block. A switch controls the source region.

Description

Vertical channel type nonvolatile memory device {VERTICAL CHANNEL TYPE NON-VOLATILE MEMORY DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a vertical channel type nonvolatile memory device.

A non-volatile memory device is a memory device in which stored data is retained even if power supply is interrupted. Recently, as the degree of integration of a memory device having a two-dimensional structure in which a memory device is manufactured in a single layer on a silicon substrate has reached a limit, a nonvolatile memory device having a three-dimensional structure in which memory cells are stacked vertically from a silicon substrate has been proposed. .

Hereinafter, a structure and a problem thereof of a nonvolatile memory device having a three-dimensional structure according to the prior art will be described in detail with reference to the accompanying drawings.

1A and 1B are a cross-sectional view and a plan view illustrating a structure of a vertical channel type nonvolatile memory device according to the prior art.

As shown in FIG. 1A, the vertical channel type nonvolatile memory device includes a plurality of memory cells MC stacked along a channel CH protruding from the substrate 10. Are separated by the interlayer insulating film 11, respectively. The memory cell MC includes a channel CH and a gate electrode 12, and a charge blocking film, a charge trap film, and a tunnel insulating film are interposed between the gate electrode 12 and the channel CH, although not shown in the drawing. .

The plurality of memory cells MC are connected in series between the lower select transistor LST and the upper select transistor UST to form a string, and each channel CH is connected to the bit line BL.

A source region S is provided in the substrate 10. The source region S is doped with N type impurities, and the channel CH is also doped with N type impurities. Therefore, the memory cell MC operates in a depletion mode. Also. An active region is defined by an isolation layer ISO formed by filling an insulating film in a field region in the substrate 10.

As shown in FIG. 1B, the plurality of bit lines BL connected to the channel CH are connected to the page buffer, and the plurality of gate electrodes 12 are connected to the X-decoder. do. In addition, as described above, the source region S is provided in the substrate 10, and the plurality of memory blocks MB_0 to MB_N share one source region S. FIG.

However, according to the structure of the vertical channel type nonvolatile memory device as described above, since the plurality of memory blocks MB_0 to MB_N share one source region S, the memory block selected to perform a predetermined operation ( MB_0) and the unselected memory blocks MB_1 to MB_N have the same condition. Therefore, it is difficult to control the off current of the lower select transistor LST.

First, the problems in the read operation are as follows.

The nonvolatile memory device performs a read operation in units of pages, and determines a threshold voltage difference between the memory cell MC in which data "1" is stored (erased) and the memory cell MC in which data "0" is stored (programmed). Data stored in the memory cell MC is read.

That is, by applying a read voltage to the word line WL to which the memory cell MC to be read is connected, the memory cell MC storing the data “1” is turned on and the memory cell MC storing the data “0” is turned on. Turn off. In addition, the turn-on voltage is applied to the other word lines WL to turn on all the memory cells MC regardless of the stored data values.

In this case, the voltage of the 'high' level is applied to the bit line BL, and the lower select transistor LST is turned on to detect whether the potential of the bit line is maintained at the 'high' level. When the bit line BL maintains the potential of the 'high' level, it can be seen that "0" is stored in the corresponding memory cell MC, that is, the programmed memory cell MC. In addition, when the potential of the bit line BL is changed to the 'low' level, it can be seen that "1" is stored in the corresponding memory cell, that is, the erased memory cell MC.

However, as described above, when the plurality of memory blocks MB_0 to MB_N share the same source area S, when the read operation is performed on the memory block MB_0, the remaining memory block that does not perform the read operation ( The source region S connected to the MB_1 to MB_N serves as a resistance component. That is, since the resistance value according to the source region S is large, the current does not flow even when "1" is stored in the memory cell MC to be read. That is, the potential of the bit line BL maintains the 'high' level, and an error in which "0" is stored incorrectly leads to an error.

Second, the problem in the erase operation is as follows.

Vertical channel type nonvolatile memory devices are generally operated in a depletion mode. That is, the semiconductor device includes a source region S and a channel CH doped with N-type impurities, and performs an erase operation by using a hot hole formed by the GIDL effect in the lower selection transistor LST. .

At this time, a hot hole is formed by a voltage difference between the gate electrode and the source region S of the lower selection transistor LST. In addition, the formed hot holes move along the channel CH, and then are injected into the charge trap layers of each memory cell to perform an erase operation.

However, as described above, when the plurality of memory blocks MB_0 to MB_N share the same source area S, when the erase operation is performed on the memory block MB_0, the remaining memory block that does not perform the erase operation ( The source region S connected to the MB_1 to MB_N serves as a resistance component. Therefore, the potential of the erase voltage to which the source region S is applied by the resistance component is lowered, thereby causing a problem that the erase speed of the memory element is lowered.

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a nonvolatile memory device having a source region for each memory block, and capable of individually controlling each source region.

In order to achieve the above object, the present invention provides a nonvolatile memory device, comprising: a source region formed in a substrate and connected in parallel with a plurality of strings constituting one memory block; And a switch for controlling the source region.

The nonvolatile memory device according to the present invention includes a source region for each of a plurality of memory blocks, or a source region for each predetermined number of memory blocks. In addition, a switch for controlling the source region formed in accordance with the memory block, respectively.

According to the present invention, since only the source region of the memory block to perform a predetermined operation can be separately controlled, the off current of the lower selection transistor can be easily controlled. In particular, it is possible to prevent an error during read operation and to improve the speed of the erase operation.

In the following, the most preferred embodiment of the present invention is described. In the drawings, thickness and spacing are expressed for convenience of description and may be exaggerated compared to actual physical thickness. In describing the present invention, well-known structures irrelevant to the gist of the present invention may be omitted. In adding reference numerals to the components of each drawing, it should be noted that the same components as much as possible, even if displayed on different drawings.

2A and 2B are a cross-sectional view and a plan view for explaining the structure of the vertical channel type nonvolatile memory device according to the first embodiment of the present invention.

As shown in FIG. 2A, the vertical channel type nonvolatile memory device according to the first exemplary embodiment includes a plurality of memory cells MC stacked along a channel CH protruding from the substrate 20. The plurality of stacked memory cells MC are separated by the interlayer insulating layer 21. The memory cell MC includes a channel CH and a gate electrode 22, and a charge blocking film, a charge trap film, and a tunnel insulating film are interposed between the gate electrode 22 and the channel CH, although not shown in the drawing. .

The plurality of memory cells MC are connected in series between the lower select transistor LST and the upper select transistor UST to form one string, and each channel CH is connected to the bit line BL.

An active region is defined by an isolation layer ISO formed by filling an insulating film in a field region in the substrate 20.

In addition, a source region S is included in the substrate 20, and the source region S is connected in parallel with a plurality of strings ST constituting one memory block MB. Here, the source region S is preferably formed for each of the plurality of memory blocks MB_0 to MB_N. That is, it is preferable to provide the source region S individually for each memory block MB.

Alternatively, the source area S may be provided for each predetermined number of memory blocks MB. For example, two memory blocks MB may share one source region S. FIG. In the drawing, as an example, a case in which a source region S is provided for each memory block MB is illustrated.

In addition, the nonvolatile memory device includes a plurality of switches SW_0 to SW_N for controlling the plurality of source regions S_0 to S_N, respectively, and the switch SW is an input voltage V_INPUT applied to the source region S. FIG. It is preferable that it is a transistor for controlling), and it is more preferable that it is a high voltage transistor especially.

In the figure, a transistor is shown as an example of the switch SW. The transistor includes a gate insulating film 23 and a gate electrode 24 formed on the substrate 20, and within the substrate 20 on both sides of the gate electrode 24, a source / drain region 25 for operation of the transistor. Is provided. In addition, a metal wiring 26 connected to the source region 25 of the transistor and a metal wiring 27 connecting the drain region 25 of the transistor and the source region S of the memory block MB are provided.

The voltage V_INPUT is transmitted through the metal wire 26, and is transferred to the source region S through the metal wire 27 according to the turn on / off of the transistor. That is, when the memory block MB is selected, the transistor which is a switch of the memory block MB is turned on to transfer the input voltage V_INPUT to the source region S. If the memory block MB is not selected, the transistor is turned on. It is turned off and does not transfer the input voltage V_INPUT to the source region S.

As shown in FIG. 2B, the plurality of bit lines BL connected to the channel CH are connected to the page buffer, and the plurality of gate electrodes 22 are connected to the X-decoder. do.

In addition, a plurality of switches SW_0 to SW_N for controlling the plurality of source regions S_0 to S_N are provided. The switches SW_0 to SW_N are connected to the plurality of source regions S_0 to S_N, respectively, to control input voltages applied to the source region S according to the operation of the memory block MB. In the drawing, a plurality of switches SW_0 to SW_N are illustrated in the X-decoder, but this is only an example and the position of the switch SW is not limited thereto.

According to the present invention as described above, each of the plurality of memory blocks (MB_0 ~ MB_N) is provided with a source area (S), or each predetermined number of memory blocks (MB) each has a source area (S). In addition, a plurality of switches SW_0 to SW_N for controlling the plurality of source regions S_0 to S_N, respectively.

Therefore, when the memory block MB for performing the read operation or the erase operation is selected, only the source region S of the memory block MB to perform the corresponding operation may be individually controlled through the switches SW_0 to SW_N. Can be. Accordingly, the selected memory block MB and the unselected memory block MB have different conditions to perform a predetermined operation, and thus, the off current of the lower selection transistor LST can be easily controlled. .

First, the read operation is as follows.

When the memory cell MC to be read is included in the memory block MB_0, the select signal SELECT_0 of the memory block MB_0 is activated to turn on the switch SW_0, for example, a transistor. As a result, the input voltage V_INPUT is transferred to the source region S0 of the memory block MB_0. Here, the input voltage V_INPUT is preferably a ground voltage.

At this time, the select signals SELECT_1 to SELECT_N for the remaining memory blocks MB_1 to MB_N except for the selected memory block MB_0 are inactivated to turn off the corresponding switches SW1 to SW_N, for example, a transistor. As a result, the input voltage V_INPUT is blocked from being transferred to the source areas S_1 to S_N of the remaining memory blocks MB_1 to MB_N.

According to the present invention, when the read operation is performed on the selected memory block MB_0, the source regions S_1 to S_N of the remaining memory blocks MB_1 to MB_N may be prevented from acting as a resistance component. In this case, an error may be prevented when the read operation is performed.

Second, the erase operation is as follows.

When the memory block MB_0 to be erased is selected, the selection signal SELECT_0 of the memory block MB_0 is activated to turn on the switch SW_0, for example, a transistor. As a result, the input voltage V_INPUT is transferred to the source region S0 of the memory block MB_0. Here, the input voltage V_INPUT is preferably 8 to 20V.

At this time, the select signals SELECT_1 to SELECT_N for the remaining memory blocks MB_1 to MB_N except for the memory block MB_0 are inactivated to turn off the corresponding switches SW1 to SW_N, for example, a transistor. As a result, the input voltage V_INPUT is blocked from being transferred to the source areas S_1 to S_N of the remaining memory blocks MB_1 to MB_N.

According to the present invention, when the erase operation is performed on the selected memory block MB_0, the source regions S_1 to S_N of the remaining memory blocks MB_1 to MB_N may be prevented from acting as a resistance component. The potential of the input voltage V_INPUT applied to the source region S_0 can be prevented from being lowered. That is, the erasing speed can be prevented from decreasing.

In particular, the vertical channel type nonvolatile memory device of the present invention can operate in an enhancement mode as well as a depletion mode. For example, when operating in the depletion mode, since the drop of the input voltage V_INPUT due to the source areas S_1 to S_N of the remaining memory blocks MB_1 to MB_N can be prevented, a hot hole is generated. Can be increased to improve the erase speed. As another example, when operating in the enhancement mode, the lower select transistor LST is floated and the input voltage V_INPUT is transferred to the channel CH to perform an erase operation. The source regions of the remaining memory blocks MB_1 to MB_N are performed. Since the drop of the input voltage V_INPUT due to (S_1 to S_N) can be prevented, the erase speed can be improved.

3A and 3B are cross-sectional views and a plan view illustrating a structure of a vertical channel type nonvolatile memory device according to a second embodiment of the present invention. However, the content duplicated with the content described in the first embodiment will be omitted.

As shown in FIG. 3A, the vertical channel type nonvolatile memory device according to the second exemplary embodiment includes a plurality of memory cells MC stacked along a channel CH protruding from the substrate 30. . The plurality of memory cells MC are connected in series between the lower select transistor LST and the upper select transistor UST to form a string.

In addition, a well region WELL is provided in the substrate 10, and a source region S is provided in the well region WELL. As such, by providing the well region WELL surrounding the source region S, even if a high level voltage is applied to the source region S, the generation of the leakage from the source region S to the substrate 20 is prevented. As a result, the input voltage V_INPUT applied to the source region S may be prevented from dropping.

The well region WELL and the source region S may be formed with respect to the plurality of memory blocks MB_0 to MB_N, respectively. That is, it is preferable that the well region WELL and the source region S are separately provided for each memory block MB.

Alternatively, the well region WELL and the source region S may be provided for each predetermined number of memory blocks MB. For example, one well region WELL and a source region S may be shared for every two memory blocks MB. In the drawing, as an example, a case in which a well region WELL and a source region S is provided for each memory block MB is illustrated.

In addition, the nonvolatile memory device includes a plurality of switches SW_W_0 to SW_W_N for controlling the plurality of well regions WELL_0 to WELL_N, respectively, and a plurality of switches for controlling the plurality of source regions S_0 to S_N, respectively. (SW_S_0 to SW_S_N).

In the drawing, a transistor is shown as an example of the switches SW_S and SW_W. The transistor includes gate insulating films 23 and 28 and gate electrodes 24 and 29 formed on the substrate 20, and the gate electrode ( The substrates 20 on both sides 24 and 29 are provided with source / drain regions 25 and 30 for the operation of the transistor. In addition, the metal lines 26 and 31 connected to the source regions 25 and 30 of the transistor and the metal lines 27 connecting the drain regions 25 and 30 of the transistor and the source region S of the memory block MB. , 32).

As shown in FIG. 3B, the vertical channel type nonvolatile memory device according to the second exemplary embodiment includes a plurality of switches SW_W_0 to SW_W_N for controlling the plurality of well regions WELL_0 to WELL_N, respectively. . The switches SW_W_0 to SW_W_N are connected to the plurality of well regions W_0 to W_N, respectively, to control the well region WELL according to the operation of the memory block MB.

In addition, a plurality of switches SW_W_0 to SW_W_N for controlling the plurality of source regions S_0 to S_N, respectively. The switches SW_0 to SW_N are connected to the plurality of source regions S_0 to S_N, respectively, to control the source region S according to the operation of the memory block MB.

In the drawing, although the plurality of switches SW_W and SW_S are provided in the X-decoder, only one embodiment is provided, and the positions of the switches SW_W and SW_S are not limited thereto.

According to the present invention as described above, each of the plurality of memory blocks MB_0 to MB_N has a well region WELL and a source region S, or each well region WELL for each predetermined number of memory blocks MB. ) And a source region (S). Also, a plurality of switches SW_W_0 to SW_W_N for controlling the plurality of well regions W_0 to W_N, respectively, and a plurality of switches SW_S_0 to SW_S_N for controlling the plurality of source regions S_0 to S_N, respectively. It is provided.

Therefore, when the memory block MB for performing the read operation or the erase operation is selected, the well region WELL and the source region S of the memory block MB to perform the corresponding operation through the switches SW_W and SW_S. ) Can be controlled individually. Accordingly, the selected memory block MB and the unselected memory block MB have different conditions to perform a predetermined operation, and thus, the off current of the lower selection transistor LST can be easily controlled. .

In particular, since the well region WELL is formed for each of the plurality of memory blocks MB_0 to MB_N, it is not necessary to form a separate contact for connecting the well region WELL. Therefore, the degree of integration of the memory device may be improved by reducing the contact area. In addition, there is no need to use a memory cell adjacent to the contact as a dummy cell.

First, the read operation is as follows.

When the memory cell MC to be read is included in the memory block MB_0, the well region selection signal SELECT_W_0 of the memory block MB_0 is activated to turn on the switch SW_W_0, for example, a transistor. As a result, the input voltage V_INPUT_W is applied to the well region W0 of the memory block MB_0. Here, the input voltage V_INPUT_W is preferably a ground voltage.

At this time, the select signals SELECT_W_1 to SELECT_W_N for the remaining memory blocks MB_1 to MB_N except for the selected memory block MB_0 are inactivated to turn off the corresponding switches SW_W_1 to SW_W_N, for example, transistors. As a result, the input voltage V_INPUT_W is blocked from being applied to the well areas W_1 to W_N of the remaining memory blocks MB_1 to MB_N.

Therefore, when the read operation is performed on the selected memory block MB_0, the input voltage V_INPUT_W may be applied only to the well region W_0_ of the selected memory block MB_0. In addition, by applying the input voltage V-IVPUT_W to the well region W_0, it is possible to suppress the generation of the leakage from the source region S_0 to the well region W_0.

Second, the erase operation is as follows.

When the memory block MB_0 to be erased is selected, the well selection signal SELECT_W_0 of the memory block is activated to turn on the switch SW_W_0, for example, a transistor. As a result, the well input voltage V_INPUT_W is transferred to the well region WELL_0 of the memory block MB_0. Here, the well input voltage V_INPUT_W is preferably 8 to 20V.

In this case, all of the well select signals SELECT_W_1 to SELECT_W_N for the remaining memory blocks MB_1 to MB_N except for the selected memory block MB_0 are inactivated to turn off the corresponding switches SW_W_1 to SW_W_N, for example, the transistor. As a result, the well input voltage V_INPUT_W is blocked from being transferred to the well regions WELL_1 to WELL_N of the remaining memory blocks MB_1 to MB_N.

According to the second embodiment of the present invention, not only the plurality of well regions WELL_0 to WELL_N are controlled, but also the well regions WELL_0 to WELL_N and the source regions S_0 to S_N can be controlled together. Do.

For example, when the read operation or the erase operation is performed, the input voltages V_INPUT_W and V_INPUT_S are applied only to the well region WELL_0 and the source region S_0 of the memory block MB_0 to perform the operation. V_INPUT_W, V_INPUT_S) can be prevented from falling to perform the operation efficiently. In particular, by applying input voltages V_INPUT_W and V_INPUT_S having the same level to the source region S_0 and the well region WELL_0, it is possible to prevent leakage from the source region S_0 to the substrate 20. The operation can be performed stably.

Of course, in performing the read operation or the erase operation, the switch SW_S_0 of the source region of the memory block MB_0 to perform the operation is turned off so that the input voltage V_INPUT_S is applied to the source region S_0. It is also possible to cut off and apply the input voltage V_INPUT_W only to the well region WELL_0 by turning on the switch SW_W_0 of the well region.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A and 1B illustrate a structure and a problem of a vertical channel type nonvolatile memory device according to the related art.

2A and 2B are views for explaining the structure and operation of a vertical channel type nonvolatile memory device according to a first embodiment of the present invention;

3A and 3B are views for explaining the structure and operation of a vertical channel type nonvolatile memory device according to a second embodiment of the present invention;

[Description of Symbols for Main Parts of Drawing]

20: substrate 21: interlayer insulating film

22: conductive film for gate electrode 23: gate insulating film

24: gate electrode 25: source / drain region

26,27: metal wiring

Claims (15)

A source region formed in the substrate and connected in parallel with a plurality of strings constituting one memory block; And A switch for controlling the source region Vertical channel type nonvolatile memory device comprising a. The method of claim 1, The source region is, Each of which is formed for a plurality of memory blocks Vertical channel type nonvolatile memory device. The method of claim 1, The source region is, Is formed for each predetermined number of memory blocks Vertical channel type nonvolatile memory device. The method of claim 1, The switch, To control the input voltage applied to the source region Vertical channel type nonvolatile memory device. The method of claim 1, When performing a lead action, Applying an input voltage to the source region by turning on a switch of a memory block including a memory cell to perform a read operation Vertical channel type nonvolatile memory device. The method of claim 5, The input voltage is, Ground voltage Vertical channel type nonvolatile memory device. The method of claim 1, When performing an erase operation, Applying an input voltage to the source region by turning on a switch of a memory block to be erased; Vertical channel type nonvolatile memory device. The method of claim 7, wherein The input voltage is, 8 to 20V Vertical channel type nonvolatile memory device. The method of claim 1, A well region formed in the substrate; And A switch for controlling the well region Vertical channel type nonvolatile memory device further comprising. The method of claim 9, When performing a lead action, Turn on the switch for controlling the source region and the switch for controlling the well region of the memory block including the memory cell to perform a read operation, the input to the well region and the source region for applying an input voltage to the source region and the well region Energized Vertical channel type nonvolatile memory device. The method of claim 9, When performing an erase operation, Applying an input voltage to the source region and the well region by turning on a switch that controls the source region of the memory block to perform the erase operation and a switch that controls the well region Vertical channel type nonvolatile memory device. A plurality of well regions formed in the substrate and respectively formed for the plurality of memory blocks; A plurality of source regions formed in the well region and respectively formed with respect to a plurality of memory blocks; And A plurality of switches for respectively controlling the plurality of well regions and the source region Vertical channel type nonvolatile memory device comprising a. 13. The method of claim 12, The switch, To control an input voltage applied to the well region or the source region Vertical channel type nonvolatile memory device. 13. The method of claim 12, When performing a lead action, The input voltage is transferred to the well region and the source region by turning on a switch of a memory block including a memory cell to perform a read operation. Vertical channel type nonvolatile memory device. 13. The method of claim 12, When performing an erase operation, Applying an input voltage to the well region and the source region by turning on a switch of a memory block to be erased Vertical channel type nonvolatile memory device.

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