KR20110001592A - Method for fabricating vertical channel type non-volatile memory device - Google Patents

Abstract

PURPOSE: A method is provided to secure an etching margin and a process margin and to prevent the line width of a contact hole bottom part from being narrowed by applying a hard mask pattern which is simultaneously and gradually etched with an etching process. CONSTITUTION: A lower structure like a lower selection transistor is formed on a substrate(30). An interlayer insulating layer(31) insulates following memory cells. A conductive layer(32) for a gate electrode forms a memory cell through a following etching process. The interlayer insulating layer and the conductive layer for a gate electrode form a single stack.

Description

Vertical channel type nonvolatile memory device manufacturing method {METHOD FOR FABRICATING VERTICAL CHANNEL TYPE NON-VOLATILE MEMORY DEVICE}

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a method of manufacturing a vertical channel type nonvolatile memory device.

The memory device is divided into a volatile memory device and a nonvolatile memory device according to whether data is maintained when the power supply is cut off. Volatile memory devices are memory devices in which data is lost when a power supply is cut off, and DRAM and SRAM are examples thereof. A nonvolatile memory device is a memory device in which stored data is maintained even when a power supply is cut off, and a flash memory device belongs to the nonvolatile memory device.

In particular, the charge trap type nonvolatile memory device includes a tunnel insulating film, a charge trap film, a charge blocking film, and a control gate electrode formed on a substrate, and traps charge at a deep level trap site in the charge trap film. To save the data.

However, in the case of the planar nonvolatile memory device according to the prior art, there is a limit in improving the degree of integration of the memory device. Therefore, recently, a vertical channel type nonvolatile memory device in which strings are arranged vertically from a substrate has been proposed. Here, the vertical channel type nonvolatile memory device has a structure in which a lower selection transistor, a plurality of memory cells, and an upper selection transistor are sequentially stacked on a substrate, and thus the integration degree of the memory device may be improved through a string arranged vertically from the substrate. .

Hereinafter, a vertical channel type nonvolatile memory device manufacturing method according to the related art will be described with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical channel type nonvolatile memory device according to the prior art.

As shown in FIG. 1A, the interlayer insulating film 11 and the conductive film 12 for the gate electrode are alternately stacked on the substrate 10. At this time, the interlayer insulating film 11 and the gate electrode conductive film 12 form one stack, and through the subsequent etching process, the gate electrode conductive film 12 is formed by each interlayer insulating film 11. Form a memory cell that is insulated. In addition, a stack composed of a stack of an interlayer insulating film 11 and a conductive film for a gate electrode 12 is repeatedly stacked in multiple layers (1st, 2nd, 3rd, ... Nth Stack) for high integration of semiconductor devices. do. At this time, one stack has a thickness of several hundred A, it is common to stack repeatedly several to several tens of times.

Subsequently, the hard mask layer 13 and the anti-reflection film 14 are formed on the stack in which the interlayer insulating film 11 and the gate electrode conductive film 12 are alternately stacked. The hard mask layer 13 and the anti-reflection film 14 are used to etch the interlayer insulating film 11 and the conductive film 12 for the gate electrode, and typically, the interlayer insulating film 11 and the conductive film 12 for the gate electrode. It is formed of a material having an etching selectivity, and the larger the number of stacked stacks, the thicker it is to secure an etching margin.

Subsequently, the photosensitive film pattern 15 is formed on the antireflection film 14. The photoresist layer pattern 15 may be formed by coating a photoresist layer on the antireflection layer 14 and patterning the channel predetermined region to be opened by exposure and development.

As shown in FIG. 1B, the antireflection film 14A and the hard mask layer 13A are etched using the photoresist pattern 15 as an etched wall.

As shown in FIG. 1C, the gate electrode conductive film 12 (see FIG. 1B) and the interlayer insulating film 11 (see FIG. 1B) are etched using the hard mask layer 13A as an etch barrier, and the interlayer insulating film 11A is etched. A channel contact hole 16 for forming a memory cell 12A that is insulated by the insulating layer and simultaneously opening the substrate 10 is formed.

As described above, in order to form a vertical channel type nonvolatile memory device, the prior art alternately stacks an interlayer insulating film 11 and a conductive film 12 for a gate electrode on a substrate 10, and then hard mask layer is formed. The etching was performed using the etching barrier.

However, the conventional technology requires a higher thickness of the hard mask layer as the number of stacked stacks increases as the integration of semiconductor devices progresses, and as the thickness of the hard mask layer increases, contact hole etching becomes more difficult. have.

2A and 2B are cross-sectional views and SEM photographs for explaining problems of the method for manufacturing a vertical channel type nonvolatile memory device according to the related art.

As shown in FIG. 2A, after the interlayer insulating film 21 and the conductive film 22 for the gate electrode are laminated on the substrate 20, an amorphous carbon hard mask pattern 23 and a silicon oxynitride film ( 24) is used as an etch barrier to form a contact hole 26 for the channel.

However, in the case of amorphous carbon that is commonly used, there is a problem that it is difficult to deposit a thickness of 10000A or more due to stress. In addition, due to the properties of relatively soft amorphous carbon, bowing ('B') occurs in the amorphous carbon during the etching process, so that the top attack or the top portion of the contact hole 26 is reduced. There is a problem that causes widening (Widening) phenomenon.

Referring to FIG. 2B, in the SEM photograph of the etching using the amorphous carbon hard mask pattern, the critical dimension of the excessively large opening, the rough shape of the sidewall, and the line width (CD) of the bottom of the contact hole are very small. can do.

The above problems are more aggravated as the number of stacks stacked for higher integration of the device increases, making the process more difficult.

In addition, when a hard mask is applied with a material different from the interlayer insulating film and the gate electrode conductive film other than amorphous carbon, for example, when the interlayer insulating film is an oxide film and the conductive film for the gate electrode is polysilicon, the hard mask is a nitride film or It can be used as a metal thin film.

However, it is difficult to increase the thickness of the nitride film or the metal thin film due to problems such as film stress and excessive deposition time, and even if the thickness is increased, productivity decreases or process defects are caused, making the process more difficult. do. Moreover, there is a disadvantage that it is difficult to remove after contact hole etching. That is, in the case of amorphous carbon can be easily removed by a photosensitive film strip process, in the case of a nitride film or a metal thin film, a separate removal process such as etching or planarization should be additionally performed. In addition, in the case of the nitride film hard mask, a polymer is generated when the contact hole is etched, thereby causing an open defect (eg, open) of the contact hole.

Therefore, there is a need for a hard mask application technique that can be easily removed while solving the above problems.

The present invention has been proposed to solve the above problems of the prior art, a method of manufacturing a vertical channel type nonvolatile memory device including a hard mask that is easy to deposit and remove, and secures the line width of the top attack and the bottom of the contact hole. The purpose is to provide.

According to an aspect of the present invention, there is provided a method of manufacturing a vertical channel type nonvolatile memory device, the method comprising: repeatedly stacking a stack in which an interlayer insulating film and a conductive film are stacked on a substrate; Forming a hard mask pattern on the stack using a material similar to that of the interlayer insulating film; Forming a contact hole for a channel by etching the conductive layer and the interlayer insulating layer using the hard mask pattern as an etch mask, wherein the uppermost layer of the stack is a conductive layer.

Particularly, the interlayer insulating film is an oxide film, the conductive film is polysilicon, and the hard mask layer is formed of an oxide film, and the hard mask layer is formed of a material having better etching resistance than the interlayer insulating film.

The method may further include forming a passivation layer on the stack before forming the hard mask pattern, wherein the passivation layer is formed of a material having a selectivity different from that of the interlayer insulating layer and the conductive layer.

In the step of forming the channel contact hole, the hard mask pattern is gradually etched and simultaneously removed while the interlayer insulating layer and the conductive layer are etched.

In addition, the stack is repeatedly stacked 2 to 128 times, and the stack in which the interlayer insulating film and the conductive film are stacked is 200 mW to 800 mW.

The hard mask pattern may have a thickness greater than at least the total thickness of the laminated interlayer insulating film.

Another embodiment includes repeating stacking a stack of interlayer insulating films and conductive films stacked on a substrate; Forming a hard mask pattern on the stack using a material similar to that of the conductive film; Forming a contact hole for a channel by etching the conductive layer and the interlayer insulating layer using the hard mask pattern as an etch mask, wherein the uppermost layer of the stack is an interlayer insulating layer.

Particularly, the interlayer insulating film is an oxide film, the conductive film is polysilicon, and the hard mask layer is formed of polysilicon, and the hard mask layer is formed of a material having better etching resistance than the conductive film.

The above-described manufacturing method of the vertical channel type nonvolatile memory device can be easily removed by applying a hard mask pattern which is gradually etched at the same time as the etching process, ensuring an etching margin and a process margin, and narrowing the line width at the bottom of the contact hole. It is effective to prevent losing.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

(Example 1)

3A to 3F are cross-sectional views illustrating a method of manufacturing a vertical channel type nonvolatile memory device according to a first embodiment of the present invention.

As shown in FIG. 3A, an interlayer insulating film 31 and a conductive film 32 for a gate electrode are alternately stacked on a substrate 30 on which a desired substructure, such as a source line and a lower select transistor, is formed. The interlayer insulating film 31 is for interlayer insulation between subsequent memory cells, and is preferably formed of an oxide film. The conductive film 32 for the gate electrode is used to form a memory cell through a subsequent etching process, and is formed of a conductive material, and preferably formed of polysilicon.

In the interlayer insulating film 31 and the gate electrode conductive film 32, two layers form a stack, and the stacks are stacked to form a string. At this time, one stack composed of the lamination of the interlayer insulating film 31 and the conductive film 32 for the gate electrode has a thickness of 200 kPa to 800 kPa.

As the integration of semiconductor devices increases, the number of stacked stacks must be increased in order to include more memory cells in one string. To this end, a stack consisting of a stack of the interlayer insulating film 31 and the conductive film 32 for the gate electrode is repeatedly stacked in several layers (1st, 2nd, 3rd ,, N-1th, Nth Stack). At this time, it is preferable that the number of stacking is repeated 2 to 128 times.

As shown in FIG. 3B, the hard mask layer 33 is formed on the stack in which the interlayer insulating film 31 and the gate electrode conductive film 32 are alternately stacked. The hard mask layer 33 is used to etch the interlayer insulating film 31 and the gate electrode conductive film 32. The hard mask layer 33 may be formed of the same or similar material as the interlayer insulating film 31 or the gate electrode conductive film 32. It is preferably formed of a material having a higher etching resistance, and formed of a material opposite to the top layer of the stack.

That is, when the interlayer insulating film 31 is formed on the uppermost layer of the stack, the hard mask layer 33 is formed in the same or similar series as the conductive film 32 for the gate electrode, and the conductive film for the gate electrode is formed on the uppermost layer of the stack. In the case of forming the 32, the hard mask layer 33 is formed in the same series or similar series as the interlayer insulating film 31.

In addition, the hard mask layer 33 is preferably formed to have a predetermined thickness or more of the total thickness of the interlayer insulating film 31 or the conductive film 32 for a gate electrode. That is, when the interlayer insulating film 31 is formed on the uppermost layer of the stack, the hard mask layer 33 has a thickness of at least the total thickness of the conductive films 32 for gate electrodes formed on the substrate 30. This is because the hard mask layer 33 is formed in the same or similar series as the interlayer insulating film 31 or the conductive film 32 for the gate electrode, and as the etching proceeds in a subsequent etching process, the hard mask layer 33 is also continuously formed. Because it is etched. If the hard mask layer 33 is not formed over the total thickness, all of the hard mask layer 33 is removed during the etching process, so that open defects may occur in the contact hole, or the contact hole top portion may be lost. It is desirable to form more than the total thickness of the material.

In the first embodiment of the present invention, a description will be given on the assumption that the interlayer insulating film 31 is formed on the uppermost layer of the stack. Therefore, the hard mask layer 33 is preferably formed in the same series or similar series as the conductive film 32 for the gate electrode.

When the gate electrode conductive film 32 is made of polysilicon, the hard mask layer 33 is also formed of polysilicon, and at this time, if the gate electrode conductive film 32 is doped polysilicon, The hard mask layer 33 is preferably formed of undoped polysilicon (Undoped Poly Silicon) having a higher etching resistance.

As described above, when the hard mask layer 33 is formed of a material having higher etching resistance than the etching target layer (for example, the conductive layer 32 for the gate electrode), an effective mask may be used during etching, and thus, the hard mask layer 33 may be formed. There is an advantage that does not have to form an excessively high height.

Subsequently, a photosensitive film pattern 34 is formed on the hard mask layer 33. The photoresist pattern 34 is formed by coating a photoresist on the hard mask layer 33 and patterning the channel predetermined region to be opened by exposure and development. When forming the photoresist pattern 34, an antireflection film may be further formed before the photoresist pattern 34 is formed to prevent reflection.

As shown in FIG. 3C, the hard mask layer 33 (see FIG. 3B) is etched using the photoresist pattern 34 (see FIG. 3B) as an etch barrier to form the hard mask pattern 33A.

Next, the photosensitive film pattern 34 (refer FIG. 3B) is removed. The photoresist pattern 34 may be removed by dry etching, and the dry etching may be performed by an oxygen strip process.

By removing the photoresist pattern 34 (refer to FIG. 3B), only the hard mask pattern 33A having the channel predetermined region opened remains on the stack. This is for automatic removal of the hard mask pattern 33A in the subsequent etching process. That is, in the subsequent etching process, the hard mask pattern 33A is gradually etched as the etching proceeds, so that the hard mask pattern 33A is almost removed at the time when the contact hole is completed, so that a separate removal process is not required. There is this. This will be described later in detail.

As shown in FIGS. 3D to 3F, the interlayer insulating film 31 (see FIG. 3C) and the gate electrode conductive film 32 (see FIG. 3C) are etched using the hard mask pattern 33A as an etch barrier, and the channel contact hole is etched. A memory cell 32A insulated by 35 and each interlayer insulating film pattern 31A is formed.

As shown in FIGS. 3D and 3E, as the etching process proceeds, the hard mask pattern 33A is gradually lowered as the hard mask pattern 33A is gradually etched, and when the contact hole 35 is completed, All of the hard mask patterns 33A are removed so that a separate removal process is not performed. The process margin is secured by not removing the hard mask pattern 33A separately, and productivity is improved.

In addition, as the height of the hard mask pattern 33A is lowered, the etching depth, that is, the depth that the etching gas must reach in order to etch the etching target layer is lower than that in the prior art (see FIG. 1C), thereby securing an etching margin. Therefore, the line width (Critical Dimension) of the bottom of the contact hole 35 can be prevented from being narrowed, thereby securing a certain line width.

(Example 2)

4A to 4F are cross-sectional views illustrating a method of manufacturing a vertical channel type nonvolatile memory device according to a second embodiment of the present invention.

As shown in FIG. 4A, an interlayer insulating film 41 and a conductive film 42 for a gate electrode are alternately stacked on a substrate 40 on which a desired substructure, such as a source line and a lower select transistor, is formed. The interlayer insulating film 41 is for interlayer insulating between subsequent memory cells and is preferably formed of an oxide film. The conductive film 42 for the gate electrode is used to form a memory cell through a subsequent etching process. The gate electrode conductive layer 42 may be formed of a conductive material, and may be formed of polysilicon.

In the interlayer insulating film 41 and the gate electrode conductive film 42, two layers form a stack, and the stacks are stacked to form a string. At this time, one stack composed of the lamination of the interlayer insulating film 41 and the conductive film 42 for the gate electrode has a thickness of 200 kPa to 800 kPa.

As the integration of semiconductor devices increases, the number of stacked stacks must be increased in order to include more memory cells in one string. To this end, a stack consisting of a stack of the interlayer insulating film 41 and the conductive film 42 for the gate electrode is repeatedly stacked in several layers (1st, 2nd, 3rd ,, N-1th, Nth Stack). At this time, it is preferable that the number of stacking is repeated 2 to 128 times.

Subsequently, the protective film 43 is formed on the stack in which the interlayer insulating film 41 and the gate electrode conductive film 42 are alternately stacked. The passivation layer 43 is for protecting the damage of the top portion of the contact hole during subsequent contact hole formation, and is preferably formed of a material having a selectivity with respect to the lower stack.

As shown in FIG. 4B, the hard mask layer 44 is formed on the passivation layer 43. The hard mask layer 44 is used to etch the interlayer insulating film 41 and the gate electrode conductive film 42. The hard mask layer 44 may be formed of the same or similar material as the interlayer insulating film 41 or the gate electrode conductive film 42. It is preferably formed of a material having a higher etching resistance, and formed of a material opposite to the top layer of the stack.

That is, when the interlayer insulating film 41 is formed on the top layer of the stack, the hard mask layer 44 is formed in the same or similar series as the gate electrode conductive film 42, and the conductive film for the gate electrode is formed on the top layer of the stack. In the case of forming 42, the hard mask layer 44 is formed in the same series or similar series as the interlayer insulating film 41.

In addition, the hard mask layer 44 is preferably formed to have a predetermined thickness or more of the total thickness of the interlayer insulating film 41 or the conductive film 42 for the gate electrode. That is, when the interlayer insulating film 41 is formed on the top layer of the stack, the hard mask layer 44 has a thickness of at least the total thickness of the conductive films 42 for gate electrodes formed on the substrate 40. This is because the hard mask layer 43 is formed in the same series or similar series as the interlayer insulating film 41 or the conductive film 42 for the gate electrode, and the hard mask layer 44 is continuously formed as the etching proceeds in a subsequent etching process. Because it is etched. If the hard mask layer 44 is not formed to have a thickness greater than or equal to the total thickness, the hard mask layer 44 may be removed during the etching process, thereby causing an open defect in the contact hole or a loss of the contact hole top portion. It is preferable to form more than the total thickness of.

In the second embodiment of the present invention, it is assumed that the interlayer insulating film 41 is formed on the top layer of the stack. Therefore, the hard mask layer 44 is preferably formed in the same series or similar series as the conductive film 42 for the gate electrode.

When the gate electrode conductive film 42 is made of polysilicon, the hard mask layer 44 is also formed of polysilicon, and at this time, if the gate electrode conductive film 42 is doped polysilicon, The hard mask layer 44 may be formed of undoped polysilicon having higher etching resistance.

As described above, when the hard mask layer 44 is formed of a material having higher etching resistance than the etching target layer (for example, the conductive layer 42 for the gate electrode), an effective mask may be used during etching, and thus, the hard mask layer 44 may be There is an advantage that does not have to form an excessively high height.

Subsequently, the photoresist pattern 45 is formed on the hard mask layer 44. The photoresist pattern 45 is formed by coating a photoresist on the hard mask layer 44 and patterning the channel predetermined region to be opened by exposure and development. When forming the photoresist pattern 45, an antireflection film may be further formed before the photoresist pattern 45 is formed to prevent reflection.

As shown in FIG. 4C, the hard mask layer 44A is etched using the photoresist pattern 45 (see FIG. 4B) as an etch barrier and the protective layer 43 (see FIG. 4B) is etched. And a protective film pattern 43A.

Next, the photosensitive film pattern 45 (refer FIG. 4B) is removed. The photoresist pattern 45 may be removed by dry etching, and the dry etching may be performed by an oxygen strip process.

By removing the photoresist pattern 45 (refer to FIG. 4B), only the hard mask pattern 44A and the passivation layer pattern 43A in which the channel predetermined region is opened remain on the stack. This is for automatic removal of the hard mask pattern 44A in the subsequent etching process. That is, in the subsequent etching process, the hard mask pattern 44A is gradually etched as the etching proceeds, so that the hard mask pattern 44A is almost removed at the time when the contact hole is completed, thus eliminating a separate removal process. There is this. This will be described later in detail.

As shown in FIGS. 4D to 4F, the interlayer insulating film 41 (see FIG. 4C) and the gate electrode conductive film 42 (see FIG. 4C) are etched using the hard mask pattern 44A as an etch barrier, and the channel contact hole is etched. A memory cell 42A insulated by the 46 and each interlayer insulating film pattern 31A is formed.

As shown in FIGS. 4D and 4E, as the etching process proceeds, the hard mask pattern 44A is gradually lowered as the hard mask pattern 44A is gradually etched, and at the time when the contact hole 46 is completed, All of the hard mask patterns 44A are removed so that a separate removal process is not performed. The process margin is secured by not removing the hard mask pattern 44A separately, and productivity is improved.

In addition, as the height of the hard mask pattern 44A is lowered, the etching depth, that is, the depth that the etching gas must reach in order to etch the etched layer is lower than in the prior art (see FIG. 1C), thereby securing an etching margin. Therefore, the line width of the contact hole 46 may be prevented from narrowing, thereby securing a predetermined line width.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical channel type nonvolatile memory device according to the prior art;

2A and 2B are cross-sectional views and SEM photographs for explaining a problem of a method of manufacturing a vertical channel type nonvolatile memory device according to the prior art;

3A to 3F are cross-sectional views illustrating a method of manufacturing a vertical channel type nonvolatile memory device according to a first embodiment of the present invention;

4A through 4F are cross-sectional views illustrating a method of manufacturing a vertical channel type nonvolatile memory device according to a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

30 substrate 31 interlayer insulating film

32: conductive film for gate electrode 33: hard mask layer

34: photosensitive film pattern 35: contact hole

Claims (22)

Repeatedly stacking a stack of interlayer insulating films and conductive films stacked on a substrate; Forming a hard mask pattern on the stack using a material similar to that of the interlayer insulating film; And Forming a contact hole for a channel by etching the conductive layer and the interlayer insulating layer using the hard mask pattern as an etch mask Wherein the top layer of the stack is a conductive film. The method of claim 1, And the interlayer insulating film is an oxide film. The method of claim 1, And the conductive film is polysilicon. The method of claim 2, The hard mask pattern may be formed using an oxide layer based method for manufacturing a vertical channel type nonvolatile memory device. The method of claim 4, wherein The hard mask pattern may be formed of a material having better etching resistance than the interlayer insulating layer. The method of claim 1, And forming a passivation layer on the stack before forming the hard mask pattern. The method of claim 6, And wherein the passivation layer is formed of a material having a selectivity different from that of the interlayer insulating layer and the conductive layer. The method of claim 1, In the step of forming the contact hole for the channel, And removing the hard mask pattern by gradually etching the interlayer insulating layer and the conductive layer. The method of claim 1, The stack is repeated two to 128 times stacked vertical channel type nonvolatile memory device manufacturing method. The method of claim 1, And said stack in which said interlayer insulating film and said conductive film are stacked has a thickness of 200 mW to 800 mW. The method of claim 1, And forming a hard mask pattern thicker than a total thickness of the stacked interlayer dielectric layers. Repeatedly stacking a stack of interlayer insulating films and conductive films stacked on a substrate; Forming a hard mask pattern on the stack using a material similar to that of the conductive film; And Forming a contact hole for a channel by etching the conductive layer and the interlayer insulating layer using the hard mask pattern as an etch mask Wherein the top layer of the stack is an interlayer insulating film. The method of claim 12, And the interlayer insulating film is an oxide film. The method of claim 12, And the conductive film is polysilicon. The method of claim 13, The hard mask pattern is a polysilicon-based vertical channel type nonvolatile memory device manufacturing method. The method of claim 15, The hard mask pattern may be formed of a material having better etching resistance than the conductive layer. The method of claim 12, And forming a passivation layer on the stack before forming the hard mask pattern. The method of claim 17, And wherein the passivation layer is formed of a material having a selectivity different from that of the interlayer insulating layer and the conductive layer. The method of claim 12, In the step of forming the contact hole for the channel, And removing the hard mask pattern by gradually etching the interlayer insulating layer and the conductive layer. The method of claim 12, The stack is repeated two to 128 times stacked vertical channel type nonvolatile memory device manufacturing method. The method of claim 12, And said stack in which said interlayer insulating film and said conductive film are stacked has a thickness of 200 mW to 800 mW. The method of claim 12, And forming a hard mask pattern thicker than a total thickness of the stacked conductive layers.

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