KR20100138203A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to improve yield by preventing a device fail by increasing the overlapped area between a storage node contact and a source region that is an active region. CONSTITUTION: A gate(G) is formed on the lower side of a trench on a substrate(10). A source region(S) and a drain region(D) are formed on the substrate of both sides of the trench. A first interlayer insulation layer is formed on the substrate and a bit line contact hole is formed to expose the part of the source region and the insulation layer. A second insulation spacer(20) is formed on the side of a first insulation spacer. A bit line contact(21) is formed in a bit line contact hole. A storage node contact hole is formed between the first and second interlayer insulation layers to expose the source region. The first insulation spacer is removed from the side of the storage node contact hole. A storage node contact(28) is formed in the storage node contact hole.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for reducing the resistance of the storage node contact.

In DRAM devices, in which a unit cell is composed of one MOS transistor and one capacitor, reducing the area while increasing the capacitance of a capacitor, which occupies a large area on a chip, is highly integrated. Has become an important factor.

In order to form a capacitor having a high capacitance in a small area, attempts have been made to increase the height of the capacitor or to reduce the thickness of the dielectric film.

However, when the height of the capacitor is increased, a problem occurs due to an increase in the level difference due to the increase in the height of the capacitor, and when the thickness of the dielectric film is decreased, the leakage current increases as the thickness of the dielectric film is decreased.

To overcome this problem, a buried type gate structure has recently been used to reduce the capacitance of the capacitor required to maintain the same sense amplifier capability by reducing the bitline parasitic capacitance to half. A dramatically lowering method has been introduced.

However, when the buried gate structure is used, an overlap margin between the storage node contact and the active region (source region) is difficult to secure due to its structural characteristics, so the overlap area between the storage node contact and the active region is small.

In detail, the overlap area between the storage node contact and the active area is increased as the width of the bit line is smaller and the length of the active area is shorter and the critical dimension (CD) is increased. However, shorter and longer-length CDs in the active area tend to be reduced due to higher integration, and when the width of the bitline is smaller than the CD of the bitline contact, the bitline contact and the storage node contact are shorted. Since it is difficult to reduce the width, the overlap area between the storage node contact and the active area becomes small.

As a result, the resistance of the storage node contact becomes higher than a threshold value, and thus the yield is reduced as it is determined to be a defective product during the test.

The present invention provides a method of manufacturing a semiconductor device for reducing the resistance of the storage node contact.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming a gate under the trench formed in the substrate and forming an insulating film on the trench, forming a source region and a drain region on both sides of the trench; Forming a first interlayer dielectric layer on the substrate and forming a bit line contact hole in the first interlayer dielectric layer to expose the drain region, a portion of the insulating layer on both sides, and a portion of the source region; Forming a first insulating film spacer on a side surface of the bit line contact hole and forming a second insulating film spacer on a side of the first insulating film spacer, and forming a bit line contact on the bit line contact hole Forming a second interlayer insulating film on the entire surface including the bit line contact; Forming a storage node contact hole exposing the source region in a second interlayer insulating film and the first interlayer insulating film, removing the first insulating film spacer at a side of the storage node contact hole, Forming a storage node contact.

The first interlayer insulating film is formed by laminating a nitride film and an oxide film.

The first insulating film spacer may be formed of an oxide film, and the second insulating film spacer may be formed of a nitride film.

Stacking a bit line and a bit line hard mask film electrically connected to the bit line contact on a portion of the first interlayer insulating film after forming the bit line contact and before forming the second interlayer insulating film. It is characterized by.

And forming a bit line spacer insulating layer along the surface curvature on the entire surface including the bit line and the bit line hard mask layer after the stacking of the bit line and the bit line hard mask layer.

The bit line spacer insulating film is formed of a nitride film.

The removing of the first insulating layer spacer may be performed by a wet etching process or a cleaning process.

According to the present invention, since the overlap area between the storage node contact and the active area (source area) is increased to decrease the resistance of the storage node contact, the device can be prevented from being lost due to the high storage node contact resistance, thereby improving the yield.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, an isolation layer 11 is formed on a substrate 10 to define an active region 10A.

Next, the trench 10 is formed by etching the substrate 10 and the device isolation layer 11 in the gate predetermined region, and the gate G is formed below the trench 12.

The gate G forms the gate insulating layer 13 along the surface curvature, forms the gate electrode 14 on the gate insulating layer 13 to fill the trench 12, and then leaves the gate 12 below the trench 12. The electrode 14 and the gate insulating layer 13 may be formed by etching the entire surface.

An oxide film or a composite film of an oxide film and a nitride film can be used for the gate insulating film 13, and a metal can be used for the gate electrode 14.

Subsequently, an insulating film 15 is formed on the entire surface including the trench 12, and the insulating film 15 formed outside the trench 12 is removed to fill the upper portion of the trench 12 with the insulating film 15.

Next, impurity ions are implanted into the active region 10A to form source and drain regions S and D.

Alternatively, the source region and the drain region S and D may be formed by implanting impurity ions before forming the trench 12 to form an impurity implantation layer and separating the impurity implantation layer when forming the trench 12. Can also be.

Then, first interlayer insulating films 16 and 17 are formed on the entire surface.

The first interlayer insulating films 16 and 17 may be formed by stacking the capping film 16 and the oxide film 17.

The capping layer 16 may be formed of a nitride layer, and the oxide layer 17 may be formed of a TEOS (TetraEthOxySilane) layer.

Referring to FIG. 1B, a bit line contact that exposes a portion of the drain region D, the insulating layer 15 and the source region S on both sides by patterning the oxide layer 17 and the capping layer 16 by a photolithography process is performed. The hole 18 is formed.

Next, a first insulating layer spacer 19 is formed on the side of the bit line contact hole 18 to cover the source region S at the bottom of the bit line contact hole 18.

The first insulating film spacer 19 may be formed of an oxide film.

The first insulating layer spacer 19 may be formed by forming an oxide layer on the entire surface including the bit line contact hole 18 and etching the entire surface of the oxide layer so as to remain on the side of the bit line contact hole 18. In this case, an etchback process may be used as the entire etching process.

Referring to FIG. 1C, a second insulating film spacer 20 is formed on the side of the first insulating film spacer 19.

The second insulating film spacer 20 may be formed of a nitride film.

The second insulating film spacer 20 may be formed by forming a nitride film on the entire surface including the first insulating film spacer 19 and etching the entire surface of the nitride film so as to remain on the side surface of the first insulating film spacer 19. In this case, an etch back process may be used as the entire surface etching process.

Referring to FIG. 1D, the bit line contact 21 is formed in the bit line contact hole 18.

The bit line contact 21 fills the bit line contact hole 18 by forming a conductive film, for example, a polysilicon film, on the entire surface including the bit line contact hole 18, and then forms the bit line contact hole 18 by a front surface etching process. It may be formed by removing the polysilicon film formed on the outside. In this case, a chemical mechanical polishing (CMP) process may be used as the front surface etching process.

Referring to FIG. 1E, a bit line conductive film 22 and a bit line hard mask film 23 are stacked on the entire surface including the bit line contact 21, and bit lines are scheduled on the bit line hard mask film 23. A mask pattern 24 covering the region is formed.

Referring to FIG. 1F, the bit line hard mask layer 23 and the bit line conductive layer 22 are etched using the mask pattern 24 as a barrier to form the bit line contact 21 and the second insulating layer spacer 20 around the bit line contact 21. The bit line BL electrically connected to the bit line contact 21 is formed on the top surface layer, and the remaining mask pattern 24 is removed.

In this case, the second insulating layer spacer 20, the first insulating layer spacer 19, and the oxide layer 17 under the bit line BL may be further etched.

Next, the bit line spacer insulating layer 25 is formed on the entire surface including the bit line BL and the bit line hard mask layer 23.

The bit line spacer insulating layer 25 may be formed of a nitride film.

Referring to FIG. 1G, a second interlayer insulating layer 26 is formed on the bit line spacer insulating layer 25.

The second interlayer insulating layer 26 may be formed of an oxide layer, for example, a boron phosphorus silicate glass (BPSG) layer.

After forming the second interlayer insulating layer 26, a CMP process may be performed to expose the bit line spacer insulating layer 25 on the bit line hard mask 23.

Subsequently, the second interlayer insulating layer 26, the bit line spacer insulating layer 25, and the capping layer 16 are selectively etched to form a storage node contact hole 27 exposing the source region S.

Referring to FIG. 1H, the first insulating layer spacer 19 exposed on the side surface of the storage node contact hole 27 is removed.

The first insulating layer spacer 19 may be removed by a wet etching process or a cleaning process. The wet etching process or cleaning process may be performed using an etching solution or a cleaning solution containing HF or BOE (Buffer Oxide Etchant).

As the first insulating layer spacer 19 is removed to expose the source region S under the first insulating layer spacer 19, the area of the source region S at the bottom of the storage node contact hole 27 increases.

Referring to FIG. 1I, a storage node contact 28 is formed by filling a conductive layer, for example, a polysilicon layer, in the storage node contact hole 27.

As described in detail above, since the overlap area between the storage node contact and the source region is increased, the resistance of the storage node contact is reduced, thereby preventing device waste due to high storage node contact resistance, thereby improving yield.

In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

1A to 1I are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of main parts of drawing>

10: substrate

16, 17: first interlayer insulating film

18: bit line contact hole

19, 20: 1st, 2nd insulating film spacer

21: bitline contact

25: bit line spacer insulating film

26: second interlayer insulating film

27: storage node contact hole

28: Storage Node Contact

G: Gate

BL: Bitline

Claims (7)

Forming a gate under the trench formed in the substrate and forming an insulating layer over the trench;  Forming source and drain regions on both sides of the trench; Forming a first interlayer insulating film on the substrate and forming a bit line contact hole in the first interlayer insulating film exposing the drain region, the insulating film on both sides thereof, and a portion of the source region; Forming a first insulating film spacer on a side of the bit line contact hole and covering the source region at a bottom of the bit line contact hole, and forming a second insulating film spacer on a side of the first insulating film spacer; Forming a bit line contact in the bit line contact hole; Forming a second interlayer insulating film over the entire surface including the bit line contacts; Forming a storage node contact hole exposing the source region in the second interlayer dielectric layer and the first interlayer dielectric layer; Removing the first insulating spacer on the side of the storage node contact hole; And Forming a storage node contact in the storage node contact hole; Method of manufacturing a semiconductor device comprising a. The method of claim 1, The first interlayer insulating film is a semiconductor device manufacturing method, characterized in that formed by laminating a nitride film and an oxide film. The method of claim 1, And the first insulating film spacer is formed of an oxide film and the second insulating film spacer is formed of a nitride film. The method of claim 1, Stacking a bit line and a bit line hard mask film electrically connected to the bit line contact on a portion of the first interlayer insulating film after forming the bit line contact and before forming the second interlayer insulating film. A method of manufacturing a semiconductor device, characterized in that. The method of claim 4, wherein And forming a bit line spacer insulating layer on the entire surface including the bit line and the bit line hard mask layer along the surface curvature after stacking the bit line and the bit line hard mask layer. Manufacturing method. The method of claim 5, And the bit line spacer insulating film is formed of a nitride film. The method of claim 1, The removing of the first insulating layer spacer is a method of manufacturing a semiconductor device, characterized in that performed by a wet etching process or a cleaning process.

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