KR20100125464A - Film forming method and semiconductor device manufacturing method - Google Patents

Abstract

The film forming method is a step of forming an oxide film on the surface of a silicon substrate, etching the oxide film, and forming an interfacial oxide film by the oxide film so that the film thickness of the interfacial oxide film measured by XPS method is 6.7 kPa or less and 6.0 kPa or more. And forming a HfO ₂ film on the interfacial oxide film in an oxidizing atmosphere by MOCVD.

Description

Film formation method and manufacturing method of semiconductor device {FILM FORMING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a film formation method, and more particularly, to a method of forming a high dielectric film called a high-K film and a method of manufacturing a semiconductor device using the high-K film.

With the progress of miniaturization technology, it is possible to manufacture ultrafine and ultrafast semiconductor devices such as gate lengths of less than 60 nm today.

In such ultrafine and ultrafast semiconductor devices, the thickness of the gate oxide film needs to be reduced along the scaling side with the reduction of the gate length. For example, in a semiconductor device such that the gate length is less than 45 nm, the gate is reduced. In the case where a conventional thermal oxide film is used, it is necessary to set the thickness of the oxide film to 1 nm or less. However, in such a very thin gate insulating film, the tunnel current increases and as a result, the gate leak current increases.

For this reason, the relative dielectric constant is much larger than that of the thermal oxide film. Therefore, even if the actual film thickness is large, Ta ₂ O ₅ , Al ₂ O ₃ , ZrO ₂ having a small SiO ₂ conversion film thickness (EOT) It is proposed to apply a high dielectric (so-called high-K dielectric) material, such as HfO ₂ , or ZrSiO ₄ or HfSiO ₄ , to the gate insulating film. By using such a high dielectric material, a gate insulating film having a physical thickness of several nm can be used even in an ultrafast semiconductor device having a very short gate length of 45 nm or less, and the gate leak current due to the tunnel effect can be suppressed. In general, such high dielectric materials become polycrystalline structures when formed on silicon substrate surfaces.

In the case where a high dielectric film is directly formed on the surface of the silicon substrate, large interdiffusion of Si atoms and metal atoms is likely to occur between the silicon substrate and the high dielectric film. Is common.

Japanese Patent Laid-Open No. 2001-85422

De Witte, H. et al., J. Electrochem. Soc. 150 (9) F169-F172 (2003) Barnett, J. et al., Semiconductor International, February 1, 2006

In the gate insulating film in which the high dielectric film is formed on such an interfacial oxide film, it is preferable to reduce the oxide film conversion film thickness of the gate insulating film as much as possible, and for this purpose, the ratio of the interfacial oxide film having a low relative dielectric constant in the gate insulating film, and thus the film thickness. It is desirable to reduce as much as possible.

According to one aspect, the present invention provides a step of forming an oxide film on a surface of a silicon substrate, etching the oxide film, and measuring the interface oxide film by the oxide film using the XPS method. And forming a HfO ₂ film on the interfacial oxide film in an oxidizing atmosphere by an MOCVD method.

According to another aspect, the present invention provides a step of forming an oxide film on the surface of a silicon substrate, etching the oxide film, and measuring the interface oxide film by the oxide film using the XPS method. and the step of forming is at least Å, and the step of forming in an oxidizing atmosphere by the MOCVD method HfO ₂ film on the surface oxide film, the HfO ₂ film Forming a silicon film or a metal film on the substrate; forming a gate electrode pattern by patterning the silicon film or the metal film; introducing an impurity element into the silicon substrate using the gate electrode pattern as a mask, and It provides a method for manufacturing a semiconductor device, comprising the step of forming a region.

According to the present invention, by setting the film thickness of the interfacial oxide film formed on the silicon substrate to 6.7 Pa or less and 6.0 Pa or more by etching, the interfacial oxide film and the HfO ₂ are not affected without affecting the film formation of the HfO ₂ film thereon. It is possible to minimize the oxide film equivalent film thickness of the laminated film in which the films are laminated, and to reduce the leakage current of the laminated film.

1A is a view for explaining a first embodiment (1 thereof),
1B is a view for explaining the first embodiment (2 of it),
1C is a view for explaining the first embodiment (3 thereof),
1D is a view for explaining the first embodiment (4 of it),
2 is a diagram showing a configuration of a MOCVD apparatus used in the embodiment;
3 is a diagram showing a relationship between a film thickness of an EOT and an interfacial oxide film and a film thickness of an HfO ₂ film according to the first embodiment;
4 is a view for explaining the structure obtained in the first embodiment;
5 is a diagram illustrating a relationship between a leak current and an EOT in the first embodiment;
FIG. 6A is a diagram (1 thereof) showing an outline of a film forming mechanism in the first embodiment; FIG.
FIG. 6B is a diagram showing an outline of a film formation mechanism in the first embodiment (2 of it),
FIG. 6C is a diagram (3 thereof) showing an outline of the film forming mechanism in the first embodiment; FIG.
FIG. 7A is a diagram showing an outline of a conventional film forming mechanism (1 thereof),
7B is a diagram showing an outline of a conventional film forming mechanism (2 thereof),
8A is a diagram showing the film formation method according to the first embodiment (1 thereof),
8B is a view showing the film forming method according to the first embodiment (2 of it),
8C is a diagram showing the film formation method according to the first embodiment (3 thereof),
FIG. 9A is a diagram (1 thereof) showing the method for manufacturing the semiconductor device according to the second embodiment; FIG.
FIG. 9B is a diagram (2 of it) showing the method of manufacturing the semiconductor device according to the second embodiment; FIG.
FIG. 9C is a view (3 thereof) showing the method for manufacturing the semiconductor device according to the second embodiment; FIG.
FIG. 9D is a diagram showing a method of manufacturing a semiconductor device according to the second embodiment (4 thereof). FIG.

[First embodiment]

First, as a first embodiment of the present invention, a film forming experiment which is the basis of the present invention will be described.

In the present embodiment, first, as shown in FIG. 1A, the thermal oxide film 12 is, for example, 16 kPa by heat treatment at 1000 ° C. in an oxygen atmosphere on the surface of the silicon substrate 11 in a (100) orientation. The silicon substrate 11 formed in the film thickness and thus formed with the thermal oxide film 12 was placed on the HF etchant 13A held in the container 13 as indicated by an arrow in FIG. 1B. The silicon substrate 11 is immersed at a constant controlled speed so as to enter the HF etching liquid 13A from one side edge thereof, and then rapidly pulled up at a higher speed, as shown in FIG. The film thickness t1 of the oxide film 12 is continuously changed from one side of the silicon substrate 11 to the other side. In the example of FIG. 1C, the thermal oxide film 12 is present in the region 11B of the substrate 11 at a thickness of 6.0 GPa or more as measured by the XPS method, but in the region 11A. The film thickness t1 is less than 6.0 kPa, or the thermal oxide film 12 is lost. The critical meaning of the film thickness t1 of "6.0 kV" is described in detail below.

Further, in the process of FIG. 1D, the HfO ₂ film 14 is formed on the structure of FIG. 1C with a film thickness of 16 to 17 kPa by the MOCVD method. The HfO ₂ film 14 forms a laminated film 16 together with the thermal oxide film 12 thereunder. However, as will be described later, in the structure of FIG. 1D, the surface state of the thermal oxide film 12 is changed from the surface state of the original thermal oxide film 12 by the etching process of FIG. In the above description, the thermal oxide film 12 constituting the laminated film 16 will be referred to as "interface oxide film".

2 shows the configuration of the film forming apparatus MOCVD apparatus 60 used to form the HfO ₂ film 14 in this embodiment.

Referring to FIG. 2, the MOCVD apparatus 60 includes a processing container 62 exhausted by a pump 61, and a holding table holding the substrate W to be processed in the processing container 62. 62A).

Further, in the processing container 62, a shower head 62S is provided to face the substrate W, and the shower head 62S has an MFC in which a line 62a for supplying oxygen gas is omitted. It is connected via the (mass flow controller) and the valve V1.

The MOCVD apparatus 60 is provided with the container 63B which hold | maintains organometallic compound raw materials, such as 3 butyl hafnium (HTB), and the organometallic compound raw material in the said container 63B is based on the pressure gas, such as He gas. Supplied to the vaporizer 62e via the fluid flow controller 62d, and the organometallic compound source gas vaporized by the modification of the carrier gas such as Ar in the vaporizer 62e passes through the valve V3. It is supplied to the shower head 62S.

In the shower head 62S, the oxygen gas and the HTB gas are formed from the opening 62S formed in the surface of the shower head 62S facing the silicon substrate W through the respective paths. In the process space in

In this embodiment, the silicon substrate 21 in the state of FIG. 1C is introduced into the processing container 62 and held on the substrate holding table 62A as the processing target substrate W. For example, the processing The internal pressure of the vessel 62 was set at 0.3 Torr and the substrate temperature was set at 480 ° C., the oxygen gas was flowed at 100 sccm from the shower head 62S, and HTB was 45 mg / at the flow rate at the fluid flow controller 62d. By introducing a value of minutes, the HfO ₂ film is formed in the same manner to have a thickness of 16 to 18 kPa on the silicon substrate 11 on which the thermal oxide film 12 is partially formed.

In addition, formation of the thermal oxidation film 12 in the process of FIG. 1A is performed using a well-known heat processing apparatus. Therefore, description of the heat processing apparatus is abbreviate | omitted.

FIG. 3 shows the silicon substrate 11 in which the HfO ₂ film 14 is formed by the MOCVD method on the interfacial oxide film 12 shown in FIG. 1D with the film thickness continuously changing. The film thickness of the interfacial oxide film 12 and the film thickness of the HfO ₂ film were determined by the XPS method, and the EOT was determined by the in-line electrical measurement method for the laminated structure of the interfacial oxide film 12 and the HfO ₂ film 14. Indicates. This in-line electrical measurement method is a combination of corona bias technology, vibration Kelvin probe technology, and pulsed light source technology, and is obtained from KLA-Tencor's Quantox device. Please refer to Non-Patent Document 1 for the details of the measurement. The EOT, the XPS film thickness of the interfacial oxide film 12 and the XPS film thickness of the HfO ₂ film 14 are all expressed in angstrom units.

In FIG. 3, "REF" shows the relationship between the EOT and the XPS film thickness of the interfacial oxide film 12 obtained for the sample in the state shown in FIG. 1C, and represents a control standard. Since "REF" has shown the relationship of EOT and XPS film thickness with respect to the same interface oxide film 12, EOT and XPS film thickness are shown by the straight line corresponding one-to-one. Here, the EOT represents a film thickness obtained electrically based on the equivalent circuit of the capacitor, whereas the film thickness of the interfacial oxide film 12 or the HfO ₂ film 14 obtained by the XPS method is determined by the Si atoms or Hf atoms contained in the film. Reflects numbers.

Referring to FIG. 3, in the "region I" of the XPS film thickness t1 of the interfacial oxide film 12 in the range of 14 kV to 6.7 kPa (6.7 k <t1≤14 kPa), the laminated film 16 It can be seen that the EOT decreases approximately parallel to the straight line REF with the decrease in the XPS film thickness t1 of the interfacial oxide film 12. In the region I, the XPS film thickness t2 of the HfO ₂ film 14 is substantially constant in the range of 16.5 kPa to 17.5 kPa, so that the EOT of the laminated film 16 seen in the "region I" is reduced. Is considered to have occurred in response to the decrease in the physical film thickness of the interfacial oxide film 12.

On the other hand, when the XPS film thickness t1 of the interfacial oxide film 12 is 6.7 kPa or less and 6.0 kPa or more, in the "region II" (6.0 k? T1? 6.7 kPa), the EOT of the laminated film 16 is When the XPS film thickness of the thermally oxidized film 12 decreases, the thickness decreases more rapidly than the straight line "REF", and the laminated film 16 where the XPS film thickness t1 of the interfacial oxide film 12 reaches 6.0 kPa. It can be seen that the EOT of) becomes the minimum.

On the other hand, in the region III where the XPS film thickness t1 of the interfacial oxide film 12 is less than 6.0 GPa, the EOT of the laminated film 16 is changed even though the film thickness t1 is almost unchanged at 6.0 GPa. It can be seen that it is rapidly increasing from about 12 Hz to 30 Hz. In addition, it can be seen that the film thickness t2 of the HfO ₂ film 14 is also slightly reduced in the region III.

The regions I and II in FIG. 3 are observed in the region 11B on the substrate 11 shown in FIGS. 1C and 1D, whereas the region III is observed in the region 11A in FIGS. 1C and 1D. As shown in FIG. 4, the apparent relative dielectric constant is small due to oxygen used at the interface between the silicon substrate 11 and the HfO ₂ film 14 when the HfO ₂ film 14 is formed. Or it is interpreted that it shows that the oxide film 12A with a large physical film thickness is formed. At that time, since the XPS film thickness t1 of the oxide film 12A is not increasing, that is, the number of atoms of Si atoms is not increasing, the oxide film 12A is formed in the region 11B. Unlike the interfacial oxide film 12 present, it is interpreted that the porous film is formed. Further, since also be film-thinning of the thickness of the HfO ₂ film 14 resulting from the area Ⅲ according to 3, and an oxide film (12A) that is the basis is a porous film quality is deteriorated, it is difficult to occur accumulation of the Hf atom, It is interpreted that the incubation time is increased when the HfO ₂ film 14 is formed.

FIG. 5 shows the relationship between the EOT and the leakage current Jg obtained for the structure of FIG. In FIG. 5, the leak current is measured by the KLT-Tencor Quantox apparatus described above, and is expressed by a leak current index (Jg index) using a breakdown voltage (V). The value of the leakage current index corresponds to the logarithmic plot of the leakage current Jg. The smaller the value, the larger the leakage current, and the larger the value, the smaller the leakage current.

Referring to FIG. 5, in the sample corresponding to region I of FIG. 3, HfO without etching on a conventional thermal oxide film, in which the leakage current Jg flowing through the laminated film 16 together with the EOT is represented by a double circle. _{In the} region II, the leakage current Jg is indicated by? In the drawing, whereas the _second comparative sample (THO _x / HfO ₂ ) on which the _two films are formed is substantially the same, that is, it is changed to the same slope. It can be seen that on the oxide film formed of oxygen radicals, the change was substantially the same as in the case of the second comparative control sample (UVO ₂ / HfO ₂ ) in which the HfO ₂ film was formed without etching.

In the region III of FIG. 3 indicated by III in FIG. 5, the EOT is greatly increased corresponding to FIG. 3, the value of the leakage current Jg is also large (the value of the leakage current index is 09 to 0.6V). The interfacial oxide film 12A formed is composed of an oxide film having poor porous film quality.

In addition, in the plot of FIG. 3, it may be considered difficult to recognize the critical significance of dividing the region I from the region II. However, in the plot of the leakage current of FIG. 5, the region I and the region II are compared. It is clear that there is a critical meaning that distinguishes between I and II. In addition, the critical significance between the region II and the region III is also clearly recognized.

In particular, in comparison with the second comparative control structure in which an interfacial oxide film is formed by ultraviolet light-excited oxygen radicals, which are indicated by? In FIG. 5, and an HfO ₂ film is formed without etching thereon, in the present invention, it is shown in the same EOT. The leakage current (Jg) in the second comparative control structure in which the value of the leakage current (Jg) represented by a straight line in "A: the present invention region II" is represented by a straight line "B: UVO ₂ / HfO₂" in the same drawing ( From the value of Jg), especially, the value of EOT becomes smaller in the range of about 13 mA or more, and it turns out that the leak current characteristic improves.

6A to 6C are diagrams illustrating the mechanism by which such an improvement in the leakage current characteristic is obtained in the present embodiment.

6A to 6C, in the present embodiment, as shown in FIG. 6A, the thermal oxide film 12 formed in the process of FIG. 1A has substantially all of the Si atoms on the surface terminated by oxygen atoms at the time of film formation. 1B, but a part of the surface is removed by the etching process of FIG. 1B, and as a result, a large number of dangling bonds of Si atoms are formed on the surface of the interfacial oxide film 12 in the state of FIG. 6B. Will be.

Thus, when the HfO ₂ film 14 is deposited on the interfacial oxide film 12 by MOCVD in the process of FIG. 6C, a high density is formed on the surface of the interfacial oxide film 12 at the initial stage of film formation of the HfO ₂ film 14. Nucleation occurs, and the film density and the flatness of the film surface of the formed HfO ₂ film 14 are improved. The improvement of the leak current characteristic shown in FIG. 5 is considered to be due to the improvement of the film density and flatness of the HfO ₂ film 14. In addition, in this embodiment, incubation time also decreases and film-forming efficiency improves.

On the other hand, as shown in FIG. 7A, when the HfO ₂ film is formed directly by the MOCVD method on the thermal oxide film 12 where the surface dangling bond is terminated, the HfO ₂ film ( The nucleation density at the beginning of film formation in 14) is low, and the incubation time is long, resulting in deterioration of the film quality of the formed HfO ₂ film or deterioration of the flatness of the film surface. For this reason, in the film forming methods of Figs. 7A and 7B, the leak current characteristics excellent in this embodiment cannot be obtained.

8A to 8C are diagrams showing an outline of the film formation method according to the present embodiment based on the above findings.

Referring to FIG. 8A, on the (100) plane of the (100) oriented silicon substrate 21, a thermal oxide film 22 is formed by, for example, heat treatment at 1000 ° C. in an oxygen atmosphere, and the process of FIG. 8B. In the above, the thermal oxide film 22 is wet etched in an etching solution using HF or BHF, and the film thickness t1 is reduced to a range of 6.0 Pa or more and 6.7 or less to form an interfacial oxide film 22A. Such wet etching can be performed by controlling the temperature and etching time of the etching liquid. For example, when the thermal oxide film 22 is formed to have a film thickness of 20 kPa, the film thickness t1 can be controlled to a predetermined range by etching for 60 seconds using an HF etchant at 24 ° C. .

Alternatively, the etching step of FIG. 8B may be performed by dry etching.

Or the etching process of FIG. 8B can also be performed by chemical dry etching. For example, by using the MOCVD apparatus 60 of FIG. 2, the silicon substrate on which the thermal oxide film 22 is formed is placed on the substrate holding base 62A in the processing container 62. See you as. The pressure of the processing vessel was set to 1 to 2 Torr, the substrate temperature was set to 150 to 200 ° C, and HF gas and NH ₃ gas were respectively passed from lines 62f and 62g through the shower head 62S to the processing vessel 62. Is introduced. According to this method, it is possible to chemically etch the film thickness of the thermal oxide film 22 until it reaches the predetermined range, thereby forming an interfacial oxide film 22A having no damage. It is possible to form the interfacial oxide film 22A by reducing the film thickness of the thermal oxide film 22 to the predetermined range.

In addition, the structure of FIG. 8B is introduced into the processing container 62 of the MOCVD apparatus 60 of FIG. 2, and held as the to-be-processed substrate W on the substrate holding table 62A. The internal pressure of the vessel 62 was set at 0.3 Torr and the substrate temperature was set at 480 ° C., the oxygen gas at a flow rate of 100 sccm and the HTB at a flow rate at the fluid flow controller 62d from the shower head 62S. By introducing at a minute value, an HfO ₂ film 23 is formed on the interface oxide film 12A in the same manner, for example, at a film thickness of 16 to 18 kPa.

The laminated film 24 of the interfacial oxide film 22A and the HfO ₂ film 23 thus formed has a minimum EOT as described above with reference to FIG. 3 and exhibits excellent leakage current characteristics as described with reference to FIG. 5. .

Second Embodiment

9A to 9D show a process for manufacturing a semiconductor device using the laminated film 24 of FIG. 8A as a gate insulating film.

Referring to Fig. 9A, an element region 41A is partitioned by an element isolation region 41I on the surface of (100) of a silicon substrate 41 having a (100) orientation, and the silicon substrate 41 is formed. The dielectric film 42 having the same structure as that of the laminated film 24 is formed on the surface by the process of FIGS. 8A to 8C.

In addition, in the process of FIG. 9B, a silicon film 43 made of polysilicon or amorphous silicon is deposited on the dielectric film 42, and the silicon film 43 is patterned in the process of FIG. 9C to form a gate electrode ( 43G) is formed. In the process of FIG. 8C, the dielectric film 42G is patterned with the gate electrode 43G as a mask to form a gate insulating film 42G.

In the process of FIG. 9D, if the semiconductor device is an n-channel MOS transistor, the gate electrode 43G is ion-implanted in the silicon substrate 41, and P +, As + or Sb + is ion implanted. In the case of a p-channel MOS transistor, B + is ion implanted, and source and drain diffusion regions 41S and 41D are respectively formed in the device region 41A on the first and second sides of the gate electrode of the silicon substrate 41, respectively. Form. At the same time, the gate electrode 43G is doped to a predetermined conductivity type.

In the semiconductor device manufactured by this process, since the film 42 having the same laminated structure as that of the laminated film 24 of FIG. 8D is used as the gate insulating film 42G, the EOT is small as described above with reference to FIG. In addition, as described with reference to FIG. 5, the leakage current characteristics are excellent, so that the operation can be performed even if the gate length is shortened to 32 nm or less.

It is also possible to manufacture a semiconductor device having a metal gate by using a metal film or a conductive metal nitride film instead of the silicon film 43.

As mentioned above, although this invention was demonstrated about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and a change are possible within the summary described in a claim.

This invention is based on Japanese Patent Application No. 2008-087446 of an application on March 28, 2008 as a priority claim, and uses the whole content.

Claims (5)

In the film forming method,
Forming an oxide film on the silicon substrate surface;
Etching the oxide film and forming an interfacial oxide film by the oxide film such that the interfacial oxide film is 6.7 kPa or less and 6.0 kPa or more, measured by XPS;
Forming an HfO ₂ film on the interfacial oxide film in an oxidizing atmosphere by MOCVD;
The deposition method. The method of claim 1,
The step of forming an oxide film on the surface of the silicon substrate is characterized in that the step of forming a thermal oxide film
The deposition method. The method of claim 2,
The etching step is performed so that the film thickness of the interfacial oxide film is 6.0 kPa.
The deposition method. The method of claim 1,
The step of forming the HfO ₂ film is characterized in that the third butyl hafnium is used as a raw material.
The deposition method. In the manufacturing method of a semiconductor device,
Forming an oxide film on the silicon substrate surface;
Etching the oxide film and forming an interfacial oxide film by the oxide film such that the interfacial oxide film is 6.7 kPa or less and 6.0 kPa or more, measured by XPS;
Forming a HfO ₂ film on the interfacial oxide film in an oxidizing atmosphere by MOCVD;
Forming a silicon film or a metal film on the HfO ₂ film;
Patterning the silicon film or the metal film to form a gate electrode pattern;
Forming a source and a drain region by introducing an impurity element into the silicon substrate using the gate electrode pattern as a mask;
The manufacturing method of a semiconductor device.

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