KR20100107084A - Memory cell - Google Patents

Abstract

As a single-transistor (1T) NVRAM cell, the single-transistor (1T) NVRAM cell utilizes silicon carbide (SiC), which provides both isolation of unbalanced charge and fast and nondestructive charge / discharge. To enable detection of controlled resistance (and many memory levels) rather than capacitance, the cell incorporates memory transistors that can be implemented in either silicon or SiC. The 1T cell has diode isolation that enables the implementation of the present flash memory, and particularly the structure used in the NOR and NAND arrays. 1T cells with diode isolation are not limited to SiC diodes. The manufacturing method includes forming a nitrided silicon oxide gate on a SiC substrate, then performing ion implantation, and finishing the formation of a self-aligned MOSFET.

Description

Memory cell {MEMORY CELL}

The present invention relates to non-volatile memory cells, and more particularly to silicon carbide based memory cells.

In current silicon-based technology, dynamic random access memory (RAM) devices are volatile because they require periodic refreshes of stored information and information is lost when memory cells are no longer connected to a power supply.

Flash memory provides complementary functionality to modern electronic systems. Flash memory uses a floating gate that is charged or discharged through surrounding insulating material to change the logic state. It is a ROM because information writing takes very long and is limited to a certain number of write cycles, so it cannot be used for RAM applications. However, as it provides non-volatile storage of information, it is maintained even when any power is disconnected from the memory cell. Flash memory also relies on processing and, in fact, needs to make adjustments to the processing by having microprocessors containing corrections made on the same chip to compensate for this process variation.

Attempts have been made to form non-volatile RAM (NVRAM) devices—memory cells having the access characteristics of silicon RAM and retention time of silicon ROM (flash memory) —USA Patent 6373095 is one example.

Another attempt at advancing memory devices is to enable an increase in memory capacity, and one way to achieve this is to reduce the cell area (8F ² in current DRAMs). F is the minimum feature (the minimum line width that can be achieved by some technology), and 8F ² indicates that the memory cell technology structure of the current technology level is such that all cells take up an area of 8F ² . This attempt was outlined by S. Okhonin, M. Nagoga, JM Sallese and P Fazan (IEEE Electron Device letters Vol 23 No 2 Feb 2002). In the case of a single transistor single capacitor (1T1C) used in DRAMs, the limiting factor in downscaling feature size is that the memory capacitance is dependent on F. Flash offers higher memory capacity because it uses a smaller single transistor (1T) with more possibilities than two logic steps per cell. There is a limit to downscaling the feature size, which is set by the need to accelerate electrons to enough energy to inject into the floating gate. An additional element is that set by the minimum thickness of the insulator, which becomes aging as the thickness of the insulator decreases.

Silicon carbide is not widely used to produce semiconductor devices that are mostly made of silicon. Silicon carbide has been proposed in US Pat. Nos. 5831288, 6218254, and 6281521 for use in transistor applications, not for memory devices.

U. S. Patent 6365919 discloses a silicon carbide junction type field effect transistor (JFET).

U.S. Patent 5465249 discloses two possible implementations of 1T1C cells in silicon carbide to realize non-volatile RAM (NVRAM) with fast write characteristics and a substantially unlimited number of write cycles (dynamic NVRAM). The difference between the two implementations is the type of transistor. In one case it is a SiC bipolar junction transistor (BJT) and in other cases a SiC metal-oxide-semiconductor field effect transistor. In both cases, the capacitor is implemented as a metal-oxide-semiconductor (MOS) capacitor on SiC. Since it is a 1T1C cell, the memory is read by sensing capacitance.

U.S. Patent 5510630 discloses a SiC based 1T1C cell and stacked polysilicon-dielectric-metal capacitors with specific structures for MOSFETs (accumulation-type MOSFETs).

U.S. Patents 5801401, 5989958, and 6166401 disclose ROM devices using silicon carbide floating gates.

It is an object of the present invention to provide a dynamic NVRAM which can have a small feature size and avoids the disadvantages of flash memory. Another goal is to provide a cell that can significantly reduce power dissipation with more aggressive downscaling. This process also increases the density of memory storage.

For this purpose, the present invention provides a single-transistor (1T) NVRAM cell using silicon carbide to provide isolation of unbalanced charge and fast and non-destructive charge / discharge. To enable sensing of controlled resistance (and many memory levels) rather than capacitance, the cell incorporates memory transistors that can be implemented in silicon or silicon carbide.

The present invention is based in part on realizing that the nitrided SiO ₂ -SiC interface consequently retains long unbalanced charges, which is suitable for developing nonvolatile memory storage devices. The process of preparing the device is based on direct oxide growth or nitriding of the SiC—SiO _{2 surface} by oxide annealing in an NO or N ₂ O atmosphere.

One embodiment of the invention is a modification of a 1T flash cell (prior art). The floating gate of a 1T flash cell can be thought of as a connection between two capacitor terminals, with one of the two capacitors between the control gate and the floating gate, and the other capacitor located between the floating gate and the channel of the transistor. . This embodiment of the present invention can then be described briefly as a replacement of a capacitor on the control-gate side by a SiC diode. Since bulk and surface charge generation / recombination are substantially negligible in the passivated SiC region, SiC diodes can provide charge retention achieved by replaced capacitors. It is also important that the SiC diode can provide fast and non-destructive charge removal / deposition, while avoiding the limitations imposed by the replaced capacitor. Designing the diode as a reference diode allows the use of forward and reverse turn-on voltages for easier charge and discharge operation. Such a 1T cell with diode isolation enables the direct implementation of the architectures used in the present flash memory, and the NOR and NAND arrangements achieved, particularly as industry standards for code and data storage.

Therefore, in another aspect, the present invention includes a single-transistor cell in which a silicon carbide device replaces a capacitor between a control gate and a floating gate, and reads information by sensing a resistance between the source and drain terminals of the transistor. It provides a dynamic non-volatile random access memory. The silicon carbide device may be a diode, preferably a reference-type diode or a controlled switch, preferably a transistor.

The disclosure of 1T cells with diode isolation in the present invention is not limited to SiC diodes. Although SiC diodes are needed to maximize retention time, the use of other materials can still be a significant advantage in terms of increased memory capacity. Memory-capacity increases beyond the levels possible by existing cells still enable certain applications that need to periodically refresh information by electrically refreshing memory cells as in conventional dynamic RAM.

In another embodiment of the present invention, a metal oxide semiconductor field effect transistor (MOSFET) is provided, which has silicon or silicon with a bit line (MOSFET drain) across a word line (MOSFET gate). Implemented in carbide, the source is parallel to the word line. This MOSFET operates as a single transistor (less capacitor) NVRAM cell. Preferably the write operation is performed by a ground gate (zero gate-to-substrate voltage). In this embodiment, the memory array is accessed by a nonleaky switch, which is an implementation of a non-leak switch that relies on a low incidence / recombination ratio in the film-protected SiC. Although other SiC-based switches (diodes, BJTs, etc.) may also be used, SiC MOSFETs are a common implementation of a switch that does not leak.

In another embodiment, the cell is read by sensing a resistance. This has the result of enabling multiple levels with a significant increase in memory capacity and eliminates the problem of downscaling cell size.

This structure has a 4F ² feature size. Another advantage is that the logic level is implemented as at least two states of the channel resistance because of the channel charge, and the difference in the resistance values of the two levels is not strictly dependent on F. A further advantage is the multi-level logic caused by the different amounts of channel charge, and thus the multi-level of resistance.

Lower voltages are required compared to flash memory, and the rates of charge and discharge are greater than with flash. The memory cell of the present invention has the added benefit that the cell can have some (infinite) logic state if necessary, and does not have any disadvantages of flash memory. Another advantage of the present invention over flash memory is that charging and discharging in flash memory is disruptive and changes the state of the material, whereas in the present invention the film-protected interface provides fast / nondestructive charge removal / deposition. will be. In the present invention, the charge and discharge of the gate through the diode does not change the electrical properties of the material forming the diode and does not stress the gate oxide in any way. With the dynamic memory cell of the present invention, the number of write cycles is high enough, and the rate of discharge / charge is fast enough to allow real time data processing. Film protection of the SiC-SiO ₂ interface can sufficiently lengthen the charge retention time, thereby avoiding the necessity of electrically refreshing the memory cells of the present invention as in a conventional RAM. Charge retention times of more than seven years can be achieved by the present invention.

Film protection can be achieved by thermal SiO ₂ film protection or by nitriding the surface at high temperatures, preferably with NO or N ₂ O.

The method for fabricating a SiC diode includes the essential step of forming a "mildly" nitrided SiC-SiO ₂ interface to reduce the etch and surface generation / recombination rate of the SiC epitaxial layers. The method for the fabrication of SiC MOSFETs also includes an important step of forming a “weak” nitrided gate oxide, then performing ion implantation, and then finishing the formation of the MOSFET. It is preferred to use self-aligned MOSFETs. The fabrication method of becoming a self-aligned MOSFET with a metal gate provides improved performance (better downscaling to F, reduced power consumption, and reduced leakage through the gate oxide). Self-aligned MOSFETs are made in a predetermined order in silicon (with either polysilicon or metal gates).

The problem with SiC is that, after making the drain and source regions by ion implantation with MOSFET gates as self-aligned masks, high temperature annealing is required to activate doping of the drain and source regions. Ion implantation can be performed at room temperature, but this requires a very high annealing temperature (> 1400 ° C.). One alternative method is to perform ion-implantation at high temperatures (about 800 ° C.), in which case the post implant annealing temperature up to 1300 ° C. is sufficient. The challenge is to find metals (or metal-based structures) that provide the necessary adhesion to gate oxides and withstand hot ion implantation. The preferred metal is molybdenum, which enables a Mo-gate process that satisfies the conditions for the production of self-aligned SiC MOSFETs by hot ion implantation. Other suitable materials are P + polysilicon, and platinum silicides. An essential feature of this preferred method is to use a capping dielectric (e.g., deposited oxide) to prevent sublimation of the Mo gate, and also use a thin metal film to avoid destroying the filling effect during ion implantation. Coating the capping dielectric.

In another aspect, the present invention provides a dynamic NVRAM comprising a 1T cell, wherein the transistor is

(a) a polysilicon body,

(b) metal or thick-doped polysilicon contacts operating as source and drain regions, and

(c) SiC gate integrated with the anode or cathode of the isolation diode

Is made by

Important substances ( Critical Material ) And technical considerations

Suitable functions for the memory cell of the present invention

(1) low occurrence / recombination rate and

(2) low leakage through gate oxide

Is possible by

The low occurrence / recombination ratio is required because silicon cannot be used to achieve very long storage times. Many semiconductor materials with a wide energy gap can theoretically fulfill this requirement, as long as the bulk recombination rate is involved. However, it is difficult to achieve a high quality interface between a semiconductor and a dielectric having a wide energy gap so that the surface recombination rate is sufficiently reduced. The native oxide of SiC is silicon-dioxide, i.e. the same dielectric as at the only industry-standard semiconductor-dielectric interface--silicon-silicon dioxide interface developed so far. SiC is the only wide energy gap material capable of providing a high-quality interface with its inherent dielectric, so the implementation of a switch (either diode or transistor) that is not leaking in the present invention is substantially limited to silicon carbide substrates. There are many SiC polytypes (3C, 4H, 6H, ...), each of which meets the basic requirements. The energy gap of 3C SiC is about 2.4 eV, which is smaller compared to other common multitypes (about 3.0 eV for 6H and about 3.2 eV for 4H SiC). This means that the occurrence / recombination ratio is the largest of all common multitypes. However, good quality 3C materials with good quality gate-dielectric interfaces can provide sufficiently low occurrence / recombination ratios for the implementation of nonvolatile RAMs. The attraction of 3C SiC is that it can be deposited on Si, for example, by a process developed by Hoya Advanced Semiconductor Technologies (HAST), in which a SiC film can be deposited on a Si wafer or a large diameter freestanding SiC wafer. Makes it possible to integrate. The interface quality between SiC and gate dielectric is essential for two requirements: low surface recombination / occurrence rate and low leakage through gate dielectric. The present invention provides a specific treatment for the interface between the SiC and the gate dielectric as one method of achieving the required high-quality interface. This treatment results in a "nitrided" interface, where the nitrogen atoms are removed and the interface defects are protected by a film. Interfacial nitriding is a direct reaction in NO or N ₂ O atmospheres at high temperatures (> 1000 ° C). It can be achieved by oxide growth or by annealing of pre-grown oxides.

Critical cells and Architecture  Considerations

Two potent approaches to cell design and memory architecture will be represented by 1C1T and 1T.

The 1C1T approach is found in modern DRAMs on silicon. In this type of cell, transistors are used as switches to access capacitors where charge is stored to store different logic levels. The transistor is set as an on-mode switch to enable reading of the information / charge stored in the capacitor. Therefore, capacitance is said to be sensed in this type of cell. Although there is only one transistor and a capacitor can be stacked on top of the transistor, using the transistor as a switch connecting the capacitor requires a contact made outside the transistor region. Therefore, the area of this cell is wider than the area occupied by a single transistor, typically equal to 8F ² . Thus, a cell will be labeled 1C1T to distinguish it from a 1T cell that occupies an area no larger than that of a single transistor.

1C1T cells with transistors implemented in silicon are volatile (as in modern DRAMs), which means that the stored charge must be refreshed periodically. Charge can leak through the MOSFET's gate oxide (if the gate oxide is very thin) and through the MOSFET's channel (if the subthreshold or off current is too high). Two such leakage mechanisms can be minimized to insignificant levels in SiC. In the case of silicon, charge leakage is also manifested by a high occurrence / recombination ratio. This leakage is set by the energy gap of the material used (silicon in modern DRAMs) and is inevitable by cell design. If a transistor in a 1C1T cell is implemented in SiC, the transition / recombination ratio can be reduced to an insignificant level while switching the 1C1T cell to nonvolatile RAM. This is disclosed in US patents 5465249 and 5510630.

Although the implementation of 1C1T cells in SiC solves the problem of memory volatility, there are limitations on memory capacity: (1) The reduction in feature size F is limited by practical limitations in detecting small capacitance (capacitance is F If it is proportional to ² , the capacitance is reduced in proportion to the cell area.), (2) The side contact between the transistor and the capacitor causes the wide cell area (about 8F ² ). Thus, the concept of 1C1T cell is not used in the present invention.

The approach disclosed in the present invention relates to the concept of 1T cells typically found in modern flash memory. The advantage of this approach is that

(1) smaller cell area is possible (close to 4F ² )

(2) if the resistance of the MOSFET is detected, downscaling of feature size F is limited by the sensing mechanism, and

(3) Multiple logic levels are practically feasible.

All these advantages help to achieve higher memory capacities, and the evidence shows that higher memory capacities are achieved by modern flash rather than by modern DRAMs.

In flash, it is clear that a 1T cell integrates two vertically integrated capacitors instead of one, a MOS capacitor between the floating gate and the MOSFET channel and a capacitor between the floating gate and the control gate. There is only one vertically integrated capacitor in a 1C1T cell. However, this does not make any difference in cell size (an important factor is the capacitors that are laterally connected in the cell we refer to as 1C1T).

Two vertically integrated capacitors in the flash present a specific way of achieving a floating gate in electrical terms. We can call this type of floating gate as a capacitor-isolating gate. The essential advantage of having a floating gate is that any unbalanced charge trapped within the floating gate can be maintained for a very long time. Therefore, this type of 1T cell becomes the basic block for making nonvolatile memory. An inherent disadvantage of capacitor-isolating gates arises from the fact that charge is forced to pass through the capacitor dielectric (s) in two processes: charge deposition to the floating gate and removal of charge from the floating gate. result,

(1) the number of charge / discharge cycles is limited,

(2) the charge and discharge time is relatively long,

(3) The charge / discharge mechanism adds a restriction to downscaling of the feature size (F).

The first two elements limit the application of this type of memory as known as read-only memory, and the third element limits the increase in memory capacity.

The present invention provides a 1T memory cell that does not require capacitor isolation, thus eliminating the disadvantages associated with flash memory. It additionally provides SiC with a film-protected surface that enables 1T non-volatile memory with a fast write of an unlimited number of cycles. Many specific implementations are possible, in particular 1T cells with diode isolation and 1T cells without gate isolation.

1 shows an energy-band diagram of a 1T cell with capacitor isolated floating gates used in related prior art flash memories.
2 shows an energy-band diagram of a 1T cell with diode isolation disclosed herein.
3 shows an Arrhenius plot of charge-hold time measured at different temperatures for a MOS capacitor on 4H SiC.
4 shows an Arrhenius plot of charge-hold time measured at different temperatures for a MOS capacitor on 3C SiC.
5 illustrates a NOR memory arrangement using a 1T cell with diode isolation, as disclosed herein.
6 shows IV characteristics for a reference diode, which defines the forward (V _F ) and reverse (V _R ) on voltages.
7 shows a cross-sectional view of a 1T cell with diode isolation in a preferred embodiment.
8 shows the layout of 1T cells used in a NOR-type arrangement.
9 shows a cross-sectional view of a 1T cell without gate isolation in a NOR-type arrangement.
10 shows the read state of a 1T cell without gate isolation.
Figure 11 shows the writing of logic 0 in a 1T cell without gate isolation.
12 shows the writing of logic 1 in a 1T cell without gate isolation.
Figure 13 shows step 1 of the manufacturing method applicable to the present invention.
Figure 14 shows step 2 of the manufacturing method applicable to the present invention.
Figure 15 shows step 3 of the manufacturing method applicable to the present invention.
Figure 16 shows step 4 of the manufacturing method applicable to the present invention.
Figure 17 shows step 5 of the manufacturing method applicable to the present invention.
18 shows step 6 of the manufacturing method applicable to the present invention.
19 shows step 8 of a manufacturing method applicable to the present invention.

1T cell with diode isolation

This type of cell is a preferred embodiment of the invention. The difference from the capacitor-isolated 1T cell used in modern flash memory can be described simply as the capacitor between the floating gate and the control gate is replaced by a SiC diode.

1 shows a cross-section and energy-band diagram of a capacitor-isolated 1T cell. When the voltage between the control gate and the body of the MOSFET is at zero voltage (FIG. 1B) it is shown that electrons are trapped in a potential well created by the floating gate and the surrounding gate dielectric. This enables long charge retention even when the unbalanced charge cannot escape the high potential barrier created on both sides by the dielectric of the capacitor. It is shown that the barrier height between the floating gate and either capacitor dielectric does not change when a positive voltage is applied to the control gate (FIG. 1C). This is a problem in terms of charge removal / deposition.

2 shows a cross-section and energy-band diagram for a 1T cell with diode isolation. In this example, the diode is implemented as an NPN structure in SiC and is separated by the gate dielectric from the body of the MOSFET, which can be made from silicon, polysilicon, or any other semiconductor. In the case of zero bias (FIG. 2B) it is shown that the PN junction adjacent to the gate dielectric (diode) creates a potential well that can store charge in a manner similar to the potential well created by the floating gate (FIG. 1B). In principle, NPN structures in silicon and any other semiconductor have the same energy-band diagram. The difference from the SiC case is that because all leakage paths are eliminated, unbalanced charge can be retained in the potential well: (1) Carrier generation in the depletion layer of the PN junction is negligible because of the wide energy gap, (2) the release over the barrier is negligible because of the large barrier height (> 1.5 eV), and (3) the occurrence / recombination at the interface between the SiC and the surrounding dielectric (SiO ₂ ) is negligible. This allows for a long charge-retention time as in the case of capacitor-isolated 1T cells.

It is shown that when a positive voltage is applied to the control gate (FIG. 2C) the barrier is removed by the applied voltage and fast and nondestructive removal of negative charges (or equivalently, deposition of positive charges) is possible. Similarly, the negative voltage at the control gate removes the barrier by lifting the energy band from the control-gate side and allows for fast and nondestructive deposition of negative charge.

This is the inherent difference between the barrier created by the diode and the capacitor, which eliminates the shortcomings of capacitor-isolated 1T cells. This is the difference that makes use of nonvolatile 1T memory cells possible to create dynamic RAM (an unlimited number of fast write cycles).

As mentioned previously, the major issue with published 1T cells with diode isolation is charge retention rather than fast and nondestructive charge deposition and removal. Recently published results (Cheong, Dimitrijev, Han, "Investigation of Electron-Hole Generation in MOS Capacitors on 4H SiC", IEEE Trans. Electron Devices, vol. 50, pp. 1433-1439, June 2003) surface generation) is a major leakage mechanism even at the highest-quality nitrided interface on 4H SiC. Therefore, charge retention in diode-isolated 1T cells is characterized by investigating charge retention in MOS capacitors on SiC. The results of such a study for MOS capacitors on 4H SiC are shown in FIG. 3. As shown, measurements are performed at high temperatures to accelerate charge generation. Details of the measurement procedure are described elsewhere (eg Cheong and Dimitrijev, "MOS Capacitor on 4H-SiC as a Nonvolatile Memory Element", IEEE Electron Dev. Lett., Vol. 23, pp. 404-406 , July 2002). Assuming Arenius type dependence on temperature, experimental results for charge-holding time at high temperatures can be extrapolated to room temperature. The result obtained in this manner is 4.6 x 10 ⁹ years. Similar studies were performed for MOS capacitors on 3C SiC, and the results are shown in FIG. Extrapolation to room temperature gives a charge-retention time of 7.8 years. Although the energy gap for 3C SiC is narrow, the difference between the retention times by 4H SiC and 3C SiC is much larger than the difference that would be made if the energy gap was the main cause. This difference implies a lower-quality 3C material, which further means that a significant improvement in charge retention on the 3C SiC is possible with further improvement in material quality.

As described above, the nitrided SiC-SiO ₂ interface provides maximum retention time for published 1T cells. However, published 1T cells with diode isolation have many useful properties even when implemented without a new, nitrided SiC—SiO ₂ interface or with other semiconductors. For example, if the diode is implemented in Si, the charge retention time can drop to less than one second, but features related to high memory capacity can still be used to make better active DRAMs.

Reading the memory cell is similar to the capacitor-isolated 1T used in flash memory. The charge in the MOSFET channel depends on the amount of charge stored in the floating gate. Assuming that the charge in the channel determines the resistance of the channel, the readout is simply performed by applying a voltage across the MOSFET channel and sensing the resulting current.

The gate-isolating diode makes it possible to program the cell without the unwanted disturbances of any neighboring cell, even when the cell is used in a NOR-type arrangement (Figure 5). To deposit positive charge at the gate of the cell, a voltage V _p is applied between the corresponding word and bit line. This voltage must be greater than the diode's forward on voltage, V _F (FIG. 6 defines the forward, V _F and reverse, V _R on voltages of the reference diode). If part of V _P is set between word line and ground (V _W = aV _P where a <1), and the other part is set between ground and bit line [V _B =-(1-a) V _P ] The voltage V _P will appear between the anode and cathode of the selected diode. This brings the diode into forward on mode and deposits a positive charge on the gate proportional to V _P -V _F. The gates of all cells parallel to the selected word line will be lifted at V _W , but no other bit lines will drop to V _B as in the case of the selected cell. If V _P remains below the maximum limit set by the values of V _F and V _R , none of the neighboring diodes will be in the on mode of either forward or reverse.

It is important that V _P can be adjusted between its minimum and maximum values to deposit different amounts of positive charge on the gate. This provides a simple mechanism for setting different logic levels in the cell.

Once the gate is charged, the word line drops to V _W = 0 V to lock the positive charge of the gate by a reverse-biased diode. The bit line also leads to V _B = 0 V to complete the write cycle.

To prepare the cell for writing, the deposited charge can be removed by setting the diode in reverse on mode in a similar manner. In this case, negative voltage V _N is used instead of V _P , causing a voltage drop larger than V _R between the cathode and anode without disturbing any neighboring cells.

There are many possible implementations for diodes and transistors in this cell. 7 shows a memory cell cross section in a preferred implementation. It can be seen that the diode is at the bottom (on the SiC or Si substrate), while the transistor is made on top of the diode and if the gate is below the transistor body, it appears below the top-side. This enables simple fabrication of diodes in single crystal SiC epitaxial layers. Regarding the body of the transistor, it can be made from a polysilicon film deposited on the oxide around the diode by well established techniques in silicon technology. The resistance of the polysilicon film is affected by the charge on the floating gate through the field effect associated with this structure. One of the depletion layer-type or inversion-type field effects can be used.

To sense the resistance, self-aligned contacts are made to contact the transistor body as the source and drain do in a typical MOSFET structure. This structure can be described as a charge-controlled polysilicon resistor with metal (or polysilicon) contacts. Although this may be a more descriptive description, electrically, this structure plays the role of a MOSFET.

The structure shown in FIG. 7 shows MOSFETs having an NPN type reference diode and a P-type body that matches the electrical diagram of FIG. 5. Other combinations are also possible, such as PNP type reference diodes and MOSFETs with either P-type or N-type bodies. Both diodes and MOSFETs can also be implemented in many different ways. For example, the diode implementation may include a Schottky contact and may utilize avalanche generation in reverse on mode.

The starting material for the structure shown in FIG. 7 is a SiC or Si substrate with three SiC epitaxial layers (NPN) on top. SiC substrates can be SiC wafers, in which case excellent temperature conductivity for SiC is used for very effective heat removal. This mitigates the power loss limit, which otherwise could be a limiting factor in increasing memory capacity. Combinations of established processing steps can be used to fabricate this structure. The diode is made by etching of SiC epilayers, where the bottom N-epitaxial layer is used to make a word line. The gate oxide is made by SiC oxidation and the SiC-SiO ₂ interface is nitrided to maximize the retention time. The body of MOSFETs is made by polysilicon deposition, doping and etching. Contacts to the body (source and drain) are made by metal or polysilicon deposition and etching or by chemical and mechanical polishing (CMP). Source lines and bit lines are made by standard techniques—oxide deposition, contact hole opening and filling, standard CMP, and metal deposition and etching.

8 illustrates the placement of 1T cells used in a NOR-type arrangement. As the diagram shows, the bit line (drain of MOSFETs) crosses the word line (gate of MOSFETs). The source of the MOSFETs runs parallel to the word line (the gate of the MOSFETs). This corresponds to a cell region of 4 F ² .

1T cell without gate isolation

A 1T cell without any gate isolation has been described in S. Okhonin, M. Nagoga, J.M. Sallese and P Fazan (IEEE Electron Device letters Vol 23 No 2 Feb 2002) were used for NOR-type arrays. The implementation of a 1T cell having a film-protected surface and no gate isolation in SiC creates a nonvolatile cell that constitutes an embodiment of the present invention.

In this embodiment, the memory cell stores minority carriers (electrons in the case of N-channel MOSFETs on P-type substrates) in the MOSFET channels. Assuming that the memory MOSFETs share a common substrate and that all MOSFETs parallel to the word line have a gate connected, it is desirable to select the gate material so that the surface is not inverted at V _G = 0 V. In other words, it is desirable to select the gate material such that the plane-band voltage (V _FB ) is negative for the N-channel MOSFET.

In order to reduce surface generation / recombination ratio, gate leakage, and minimum feature F, the preferred implementation of the MOSFET in this embodiment is a self-aligned structure (self-aligned gate and source / drain regions). Self-aligned MOSFETs have been made of silicon (either polysilicon or metal gates). Attempts in SiC are because high temperature annealing is required to activate the doping of the drain and source regions with MOSFET gates as self-aligned masks after the drain and source regions are created by ion implantation. Ion implantation can be performed at room temperature, but this requires very high annealing temperatures (> 1400 ° C.). One alternative method is to perform ion implantation at high temperatures (about 800 ° C.), in which case the post implant annealing temperature up to 1300 ° C. is sufficient. Gate materials that meet this criterion include polysilicon, molybdenum, and platinum silicides. The required SiC film can be deposited on Si to enable fusion with today's Si electronics.

Figure 9 shows a cross section of a 1T cell without gate isolation in a NOR-type arrangement. For the case of N-channel MOSFETs, a particular proposal is to select the gate material such that the plane-band voltage V _FB <0 and the threshold voltage V _T > 0. With this, the channel region is depleted for V _G = 0. Some positive charge is present in the gate to compensate for the negative acceptor ions at the depleted SiC surface, but this equilibrium charge will be ignored (for clarity) in the following considerations. Note that completely similar descriptions are valid if a P-channel MOSFET is used.

Information reading: The equilibrium state (depleted surface) corresponds to a very high channel resistance and is defined as logic '0' (FIG. 10A). Reading of this state is accomplished by connecting the source line to ground and the bit line to a small positive voltage V _B. The channel-resistance at the intersection between the source and the bit line determines the current, and if this MOSFET has a depleted channel, there is no current (logic '0').

The logic '1' state is achieved by trapping an additional positive charge on the MOSFET gate to sufficiently increase the potential in the channel so that an inversion layer of electrons is formed on the SiC surface (Figure 10b). The readout is as above, with the difference that the response is a significant current through the channel (logic '1'). Note that the application of voltage to the drain and ground of the source do not affect the stored information. There will be a small change in surface potential, but the charge on the gate will not change, so the surface SiC conditions will be restored after a read cycle.

Storage time. The logic '1' state is non-equilibrium, so the natural mechanism will act to remove the inverted-layer electrons to bring the structure into equilibrium. There are two possible mechanisms for electron removal: (1) leakage through the gate oxide (gate dielectric), and (2) leakage through the switch in the connecting circuit. High-quality oxide-SiC interfaces can be achieved to reduce leakage to a sufficient level. The above experimental results indicate that it is possible to achieve a switch (implemented as a SiC MOSFET) that sufficiently low bulk and surface-recombination levels do not substantially leak.

Floating gate connection for read operation. The read operation (for both logic '1' and logic '0') is performed by the ground gate. In this embodiment, the gate is electrically disconnected from ground by using the SiC MOSFET as a switch, allowing direct selection of cells for reading and writing information. It has already been described that the trapped charge on the gate recovers the state of the cell after the disturbance caused by the V _B potential used for reading the information. Likewise, as will be described in the following text, the state of the cell does not change when the bit line (MOSFET drain) is connected to a potential for information writing purposes.

Write logic '0'. Logic '0' corresponds to the equilibrium state (depleted surface). To set this state, the selected word line is grounded (FIG. 11). This is important in that the logic '1' state does not change the state of any of the connected MOSFETs that may be in the logic '1' state as it is written in the grounded gate. After this, the corresponding bit line is grounded and closes the ground-to-ground circuit through the gate-channel capacitance to the MOSFET at the intersection between the word and gate lines. This removes electrons from the channel.

Recording logic '1'. Once again, the selected word line is grounded first. In this case, however, the source line parallel to the selected word line is not left broken and is connected to a negative voltage which is less than the forward-bias voltage of the substrate-source P-N junction. This causes a small increase in the hole density in the gate, but there should be no electron injection by the source, so that the original state of the depleted surface is restored to logic '0' MOSFETs that are not selected by the bit line (disconnected drain). Stated another way, a negative limit-voltage shift ("inverted body effect") by source-to-substrate bias keeps the limit voltage positive and no electrons It should be restricted so that it is not guided to the channel. A sufficiently large positive voltage is set in the forward-bias mode of the source-substrate N-P junction of the selected MOSFET and applied to the selected bit line (MOSFET drain) such that a flow of electrons flows through the channel. The presence of electrons in the channel means that the threshold voltage is shifted to a negative value by the drain bias. As channel electrons induce positive charge in the gate (Figure 5), the gate breaks to trap positive charge. If the inverse body effect in a given MOSFET is strong enough to shift the threshold voltage itself from positive to negative, a simpler procedure for writing a logic '1' state is possible. In such a case, if the drain and gate lines cross each other while allowing the selection of a single MOSFET, a drain-to-gate circuit must be used for writing. Therefore, after the gate is grounded, a sufficiently large negative drain voltage is applied to shift the threshold voltage to a negative value (once again, the drain voltage should not be greater than the on-voltage of the drain-to-substrate diode). If the gate-to-substrate voltage is zero, an electron channel is formed, increasing the gate capacitance to its inversion level and increasing the positive charge in the gate.

N-channel reversal type self-aligned MOSFET manufacturing steps:

The following details the fabrication process for an n-channel inversion type self-aligning MOSFET.

1] Active area specification: see FIG.

1.1. Wafer cleaning

1.2. Sputtered 500-nm thick field oxide-SiO ₂ [3 hrs = 1.1 μm]

1.3. Photoresist Deposition & Soft Bake

1.4. UV exposure (mask 1)

1.5. Photoresist Development & Hard Bake

1.6. Etching Field Oxides with BHF

1.7. Remove photoresist with ethanol

2] gate oxide growth: see FIG. 14

2.1. Wafer Cleaning (without HF) ^***

2.2. Thermally Growing 50nm Gate Oxide (nitride oxide)

[1 hour NO, 4 hours O ₂ , 2 hours NO, and overnight cooling]

3] formation of metal contact layer for gate oxide: see FIG. 15

3.1. Sputtered 1-μm Thickness Mo [200 W for 55 minutes]

3.2. 200 nm SiO ₂ deposition by spin-on-glass (sog) [4000 rpm]

3.3. Soft bake at 200 ° C. for 1 hour

3.4. Hard bake at 900 ° C. for 20 minutes

3.5. Cool down to 700 ℃

3.6. Photoresist Deposition & Soft Baking

3.7. Exposure to UV (mask 2)

3.8. Photoresist Development & Hard Baking

3.9. SiO ₂ (spin-on-glass) etching with BHF

3.10. Mo etch [1μm thick Mo etch possible for 1 minute 15 seconds]

4] ion implantation (N ⁺ ): see FIG. 16

5] Activation and drive-in of implanted ions: see FIG. 17

5.1. Annealing at 950 ° C (or 1300 ° C) for 30 minutes

6] Open source / drain window: see FIG. 18

6.1. Spin-on-glass, SiO _{2 ( MO )} (protects Mo sidewalls from Ni etchant)

6.2. Photoresist Deposition & Soft Baking

6.3. UV exposure (mask 3)

6.4. Photoresist Development & Hard Baking

6.5. SiO ₂ etching with BHF (SiO _{2 ( MO )} , spin-on-glass on MOS-C, MOSFET, and R _C Test Structure & Nitrided Oxide on R _C Test Structure)

6.6. Remove photoresist with ethanol

7] Bulk contact area preparation:

7.1. Photoresist Deposition & Soft Baking

7.2. UV exposure (mask 4)

7.3. Photoresist Development & Hard Baking

7.4. Mo etching

7.5. Nitrided Oxide Etching

8] metallization of the source / drain / bulk contacts: see FIG. 19

8.1. Sputtered 50 nm Ni (time = 40 min at 200 ° C.)

8.2. Photoresist Deposition & Soft Baking

8.3. UV exposure (mask 5)

8.4. Photoresist Development & Hard Baking

8.5. Ni etching [Al etching agent]

8.6. Photoresist Removal

In summary, the present invention explores the low bulk and surface recombination rates achievable in SiC. This fact is used to propose an inactive dynamic random-access memory (DRAM) having the following characteristics.

1. Store virtually unlimited information, even when no power is connected to the cell (memory).

2. Comparable to today's DRAMs (volatile DRAMs) on silicon that require refreshing-fast read and write

3. infinite number of write cycles

4. Cell size-4F ² , smaller than today's commercial volatile DRAMs, where F is the minimum feature size.

5. Easier downscaling of F compared to today's volatile DRAMs. This is mainly because the '0' and '1' logic levels are implemented as two states of channel resistance, so the difference between the two levels does not strictly depend on how small F is. In contrast, relatively small differences in the two capacitance levels are used in today's volatile DRAMs, so downscaling of the memory capacitor is one limiting factor.

6. Reduced power consumption

7. Multiple logic levels and consequently higher memory capacity

8. Full compatibility with silicon allows support electronics to be produced from such more mature materials.

9. Higher thermal conductivity also enables higher mass storage of digital information.

Those skilled in the art will appreciate that the invention can be implemented in many configurations in various ways without departing from the important teachings of the invention.

Claims (22)

3-terminal memory for storing information,
A first terminal electrically connected to the word line;
A second terminal electrically connected to the bit line;
A third terminal electrically connected to the source line; And
A silicon carbide device interposed between the first terminal and the other terminals
Including,
A voltage of a first polarity across the silicon carbide device is operative to store a first value, a voltage of a second polarity across the silicon carbide device is operative to store a second value,
And a resistor between the second terminal and the third terminal represents the stored value. The method of claim 1,
The silicon carbide device comprises an N-type silicon carbide layer, a P-type silicon carbide layer, and an NP junction between the N-type layer and the P-type layer. The method of claim 2,
The silicon carbide device further comprises a second N-type silicon carbide layer, and a PN junction between the P-type layer and the second N-type layer. The method of claim 3,
The word line and the second N-type layer are formed of the same material, whereby the first terminal is the second N-type layer. The method of claim 2,
The silicon carbide device further comprises a second P-type silicon carbide layer, and a PN junction between the second P-type layer and the N-type layer. The method of claim 5,
The word line and the second P-type layer are formed of the same material, whereby the first terminal is the second P-type layer. The method of claim 2,
And a dielectric interposed between the silicon carbide device and the second and third terminals. The method of claim 7, wherein
Wherein said dielectric is silicon oxide. The method of claim 2,
And a semiconductor material interposed between a dielectric and the second terminal and the third terminal. 10. The method of claim 9,
And the semiconductor material is polysilicon. The method of claim 10,
Wherein said polysilicon operates as a charge-control register. A memory array for storing information,
A plurality of word lines;
A plurality of bit lines;
A plurality of source lines; And
Multiple Silicon Carbide Devices
Including,
Each silicon carbide device is electrically connected to an associated word line, an associated bit line and an associated source line,
The selected silicon carbide device may be reversibly programmed to a first memory state by applying a first voltage to an associated word line of the selected silicon carbide device and applying a second voltage to an associated bit line of the selected silicon carbide device. The first voltage is higher than the second voltage such that the voltage across the selected silicon carbide device becomes negative polarity;
The selected silicon carbide device may be reversibly programmed to a second memory state by applying a third voltage to an associated word line of the selected silicon carbide device and applying a fourth voltage to an associated bit line of the selected silicon carbide device. The fourth voltage is higher than the third voltage such that the voltage across the selected silicon carbide device is positive polarity;
And the memory state of the selected silicon carbide device may be determined by sensing current across an associated word line of the selected silicon carbide device and an associated bit line of the selected silicon carbide device. The method of claim 12,
Each silicon carbide device comprises an N-type silicon carbide layer, a P-type silicon carbide layer, and an NP junction between the N-type layer and the P-type layer. The method of claim 13,
Each silicon carbide device further comprises a second N-type silicon carbide layer and a PN junction between the P-type layer and the second N-type layer. The method of claim 14,
And the word line and the second N-type layer are formed of the same material, whereby the first terminal is the second N-type layer. The method of claim 13,
Each silicon carbide device further comprises a second P-type silicon carbide layer and a PN junction between the second P-type layer and the N-type layer. The method of claim 16,
And the word line and the second P-type layer are formed of the same material. The method of claim 13,
Each silicon carbide device is interposed between an associated word line and a dielectric layer of the silicon carbide device. The method of claim 18,
And the dielectric is silicon oxide. The method of claim 13,
And a semiconductor material interposed between associated word lines and bit lines of each silicon carbide device. The method of claim 20,
And the semiconductor material is polysilicon. The method of claim 21,
And said polysilicon operates as a charge-control register.

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