KR20100102422A

KR20100102422A - Method for manufacturing contact hole using spacer patterning technology

Info

Publication number: KR20100102422A
Application number: KR1020090020791A
Authority: KR
Inventors: 박종천; 조병욱
Original assignee: 주식회사 하이닉스반도체
Priority date: 2009-03-11
Filing date: 2009-03-11
Publication date: 2010-09-24

Abstract

The present invention relates to the formation of a fine contact hole in a semiconductor device, using a spacer patterning process that improves the conventional reflow process, and forming first and second line and space patterns on the etched layer, the line pattern Forming a contact hole by etching the etched layer at the bottom by forming a spacer on the sidewall, and uniformly depositing the spacer to uniformly form the size of the contact hole and providing an advantageous effect for forming a finer pattern. .

Description

Method for forming a contact hole using a spacer patterning process {Method for manufacturing contact hole using spacer patterning technology}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a technique for forming a uniform contact hole by using a spacer patterning process in order to compensate for the disadvantages of the conventional resist reflow method in forming a fine pattern. It is started.

One of the most important things in the manufacture of semiconductor devices is the formation of accurate circuit patterns on semiconductor substrates such as wafers. Typically photolithography processes are used to form circuit patterns. The photo process is a photoresist coating process for applying a photoresist, which is a substance whose chemical properties change upon receiving light, onto the substrate, and placing the substrate on which the photoresist is applied is placed below a drawn reticle of a desired pattern. An exposure step of irradiating light having a wavelength so that the pattern of the reticle is transferred to the photoresist on the substrate as it is, and developing the substrate by supplying a developer on the substrate so that the pattern transferred to the photoresist is exposed to the outside. And a developing step and a baking step of heating the substrate before and after the exposure and developing steps. Therefore, after the photo process, the desired circuit pattern may be formed on the substrate by performing a subsequent process such as etching using the photoresist pattern as a mask.

With the development of the electronics industry, various methods have been developed to further improve the degree of integration in order to manufacture semiconductor devices capable of faster processing speeds and data storage. In the lithography field, high resolution exposure equipment and light-sensitive photoresist compositions have been developed. Research is ongoing. In particular, efforts have been made to increase the dimensional accuracy of patterns for structures having a minimum pitch. However, according to the drastically reduced design rule, it is difficult to resolve the current exposure equipment, and when using a photosensitive photoresist, a complicated additional process is involved.

Resist reflow technology is a technology developed to overcome the current resolution limit. The photoresist forming the pattern can be heated to flow to form a line-and-space (L / S) having a desired line width (CD) or a contact hole of a desired size. Briefly described as follows. After forming an initial photoresist pattern larger than the desired size, the line width or contact hole of the final L / S pattern is heated to a temperature above the glass transition temperature of the photoresist to flow the photoresist of the photoresist pattern, That is, reflow is possible. In other words, the viscosity of the photoresist is reduced by heating, which causes the photoresist to reflow, thereby reducing the line width of the L / S pattern or the size of the contact hole, thereby obtaining a desired fine pattern.

However, this reflow process is also in a situation where the uniformity of the fine pattern line width is poor due to the change of the degree of resist PR flowing according to the size of the line width, and the reflow is facing a limit as the line width becomes very small.

In order to solve the above-mentioned problems, the present invention provides a method of manufacturing a semiconductor device for forming a very fine contact hole using a spacer process when forming a fine pattern through lithography technology and simplifying the process.

In the semiconductor device manufacturing method according to the present invention, forming a first pattern by applying a photoresist film on the semiconductor substrate on which the etched layer is formed and exposing and developing with a first and a second mask to form a spacer on the sidewall of the first pattern Forming a second pattern, and etching the lower etching target layer using the second pattern as a barrier.

Here, the etched layer is formed of a laminated structure of a first oxide film, amorphous carbon, a second oxide film, silicon oxynitride, and the first and second oxide film using PE-TEOS, the anti-reflection film on the etched layer It is characterized by applying a.

In this case, the first and the second mask is a line and space (line and space) form, the exposure process is performed by exposure equipment of I-line, KrF, ArF, ArFi, EUV and the first pattern is formed Afterwards, the method further comprises etching the bottom anti-reflection film using the first pattern as a mask.

The forming of the second pattern may include embedding a spacer material on the front surface and anisotropically etching the spacer material and removing the remaining spacer material. And removing the etched layer remaining on the upper part of the stacked structure of the first oxide film and the amorphous carbon formed after the etching, to form a fine contact hole.

The present invention can improve the uniformity of the contact hole size by using a spacer deposited uniformly in the process of forming a fine pattern, it is possible to form a fine contact hole smaller than 30nm by adjusting the thickness of the spacer.

In addition, there is an advantage that the production yield is increased because it is simplified by reducing the number of steps compared to the conventional spacer process.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1E are cross-sectional views illustrating a pattern forming process of the present invention, and FIGS. 2A to 2E are plan views of FIGS. 1A to 1E seen from above.

Referring to FIG. 1A, a first oxide film 102, an amorphous carbon (aC) 104, a second oxide film 106, a nitride film 108, and an antireflection film 110 are sequentially disposed on a semiconductor substrate 100. It deposits. In this case, the first and second oxide films are preferably formed of PE-TEOS. Next, a photoresist layer (not shown) is coated on the entire surface, and the first photoresist layer pattern 112 is formed by exposing the photoresist layer with a line-and-space (L / S) -type mask thereon.

Referring to FIG. 2B, another line-and-space mask (not shown) is formed on the upper portion of the first photosensitive film pattern 112 formed in FIG. 1A so as to form a contact hole. Subsequently, when the second photoresist pattern 114 is formed by performing an exposure and development process, the first pattern 115 where the first photoresist pattern 112 and the second photoresist pattern 114 intersect in an oblique direction as shown in FIG. 2B. ) Is formed and the portion emptied without intersecting becomes a space where a contact hole is to be formed later. In this case, when exposing to form the first photoresist pattern 112 and the second photoresist pattern 114, it is preferable to use exposure equipment of I-line, KrF, ArFi, and EUV.

Referring to FIG. 3A, the anti-reflection film 110 is etched using the first pattern 115 as an etch mask to form an anti-reflection film pattern 110a.

Referring to FIG. 4A, a spacer material (not shown) is coated on the stacked structure of the anti-reflection film pattern 110a and the first pattern 115 and the silicon oxynitride 108 formed on FIG. 3A, and then After the anisotropic etching is performed, the second pattern 117 is formed by depositing the spacer 120 on the sidewalls of the stack structure of the anti-reflection film pattern 110a and the first pattern 115.

Referring to FIG. 5A, the silicon oxynitride 108, the second oxide layer 108, the aC 104, and the first oxide layer 102 may be sequentially etched using the second pattern 117 as an etch mask. The upper portion of the formed pattern is removed with an etch back so that a portion of the aC 104 remains, thereby forming a stacked structure of the first oxide layer pattern 102a and the aC pattern 104a. This leaves the a-C pattern 104a on the first oxide layer pattern 102a for etching margin, and then removes it by the strip process. That is, as shown in FIG. 5B, a micro contact hole 130 is formed in which an area where the lines of the first pattern 115 do not cross is reduced by the thickness of the spacer 120. In order to form a uniform contact hole according to the present invention, it is important to uniformly deposit the thickness of the spacer 120 formed on the sidewalls of the stacked structure of the first oxide layer pattern 102a and the aC 104a pattern of FIG. 4A. , By adjusting the thickness of the spacer 120 has a feature that can make the size of the contact hole more fine.

The method for forming a contact hole according to the present invention has an advantage of reducing the number of processes compared to etching only with a spacer after removing a partition (third pattern in the present invention) in a conventional spacer patterning process. In addition, the uniformity of the contact hole may be increased by uniformly depositing the spacers, thereby improving characteristics and reliability of the semiconductor device. The present invention can be used not only for DRAM, but also for forming semiconductor device patterns of flash memory, SRAM, and logic.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 5A are cross-sectional views illustrating the formation of contact holes in the present invention.

1B-5B are respective top views of FIGS. 1A-5A.

Claims

Depositing an anti-reflection film on the entire surface of the etched layer formed on the semiconductor substrate and then applying a photosensitive film;

Etching the bottom anti-reflection film with the first pattern formed by sequentially exposing and developing the first and second masks crossing each other;

Applying a spacer material to the entire surface of the first pattern and then anisotropically etching to form a second pattern;

Etching the lower layer of the etched layer using the second pattern as a barrier; And

Etching the etched layer to form a micro contact hole

A semiconductor device manufacturing method comprising a.

The method of claim 1, wherein the etched layer is formed of a stacked structure of a first oxide film, an amorphous carbon, a second oxide film, and a silicon oxynitride film (SiON).

The method of claim 2, wherein the first and second oxide films use PE-TEOS.

The method of claim 1, wherein the first and second masks have a line and space shape that crosses in an oblique direction.

The method of claim 1, wherein the exposing step is performed using an exposure apparatus of I-line, KrF, ArF, ArFi, and EUV.