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KR20100030499A - Flip chip package and method of fabricating the same - Google Patents

Flip chip package and method of fabricating the same Download PDF

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Publication number
KR20100030499A
KR20100030499A KR1020080089471A KR20080089471A KR20100030499A KR 20100030499 A KR20100030499 A KR 20100030499A KR 1020080089471 A KR1020080089471 A KR 1020080089471A KR 20080089471 A KR20080089471 A KR 20080089471A KR 20100030499 A KR20100030499 A KR 20100030499A
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South Korea
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gap
fill
substrate
fill member
semiconductor chip
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KR1020080089471A
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Korean (ko)
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박명근
김기영
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주식회사 하이닉스반도체
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Priority to KR1020080089471A priority Critical patent/KR20100030499A/en
Publication of KR20100030499A publication Critical patent/KR20100030499A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명에 따른 플립 칩 패키지 및 그의 제조방법은, 복수 개의 본드핑거들이 배치된 기판과, 상기 기판 상에 배치되며 상기 각 본드핑거들과 마주하는 본딩패드들을 갖는 반도체 칩과, 상기 각 본드핑거들 및 상기 각 본딩패드들을 전기적으로 연결하는 접속 부재와, 인접한 접속 부재들 사이의 공간을 1차적으로 갭-필(Gap-Fill)하는 제1갭-필 부재와, 상기 기판 및 상기 반도체 칩 사이를 2차적으로 갭-필하는 제2갭-필 부재를 포함한다.In accordance with another aspect of the present invention, a flip chip package and a method of manufacturing the same may include a substrate including a plurality of bond fingers, a semiconductor chip disposed on the substrate, and bonding pads facing the respective bond fingers, and the bond fingers. And a connection member for electrically connecting the respective bonding pads, a first gap-fill member that first gap-fills a space between adjacent connection members, and between the substrate and the semiconductor chip. A second gap-fill member that is secondarily gap-filled.

Description

플립 칩 패키지 및 그의 제조방법{FLIP CHIP PACKAGE AND METHOD OF FABRICATING THE SAME}Flip chip package and manufacturing method thereof {FLIP CHIP PACKAGE AND METHOD OF FABRICATING THE SAME}

본 발명은 플립 칩 패키지 및 그의 제조방법에 관한 것으로, 보다 자세하게는, 플립 칩 패키지 형성시 범프 주위의 보이드(Void) 발생을 방지할 수 있는 플립 칩 패키지 및 그의 제조방법에 관한 것이다. The present invention relates to a flip chip package and a method of manufacturing the same, and more particularly, to a flip chip package and a method of manufacturing the same that can prevent the generation of void (Void) around the bumps when forming the flip chip package.

각종 전기, 전자 제품의 크기가 소형화되는 추세에 따라, 한정된 크기의 기판에 보다 많은 수의 칩을 실장시켜 소형이면서도 고용량을 달성하고자 하는 많은 연구가 전개되고 있고, 이에 따라, 기판 상에 실장되는 반도체 패키지의 크기 및 두께가 점차 감소되고 있는 실정이다. As the size of various electric and electronic products is miniaturized, a lot of researches are attempting to achieve a small size and high capacity by mounting a larger number of chips on a limited size substrate, and thus, a semiconductor mounted on the substrate. The size and thickness of the package is gradually decreasing.

예들 들어, 패키지의 전체 사이즈에 대해 반도체 칩의 사이즈가 80% 이상이 되는 칩 사이즈 패키지(Chip Size Package)가 제안되었으며, 이러한 칩 사이즈 패키지는 경박단소의 잇점 때문에 여러가지 형태로 개발되고 있다. For example, a chip size package has been proposed in which the size of a semiconductor chip is 80% or more with respect to the total size of the package, and such a chip size package has been developed in various forms due to the advantages of light and small.

한편, 전형적인 반도체 패키지 및 일부 칩 사이즈 패키지는 인쇄회로기판(Printed Circuit Board)에의 실장방법으로 리드프레임에 의한 솔더링(soldering) 방식을 이용하고 있다. 그러나, 상기 리드프레임에 의한 솔더링 방 식은 공정 진행이 용이하고 신뢰성 측면에서 우수하다는 잇점이 있지만, 반도체 칩과 인쇄회로기판 간의 전기적 신호 전달 길이가 긴 것과 관련하여 전기적 특성 측면에서는 불리함이 있다. Meanwhile, typical semiconductor packages and some chip size packages use a soldering method using a lead frame as a mounting method on a printed circuit board. However, the soldering method by the lead frame has advantages in that the process proceeds easily and is superior in terms of reliability. However, there is a disadvantage in terms of electrical characteristics in connection with a long electrical signal transmission length between the semiconductor chip and the printed circuit board.

이에, 반도체 칩과 인쇄회로기판 간의 전기적 신호 전달 경로를 최소화시킬 목적으로, 범프(Bump)를 이용한 플립 칩 패키지 구조가 제안되었다. Accordingly, in order to minimize the electrical signal transmission path between the semiconductor chip and the printed circuit board, a flip chip package structure using a bump has been proposed.

상기 플립 칩 패키지는 칩의 본딩패드 상에 형성시킨 범프에 의해 상기 반도체 칩이 인쇄회로기판에의 접착이 이루어지도록 함과 동시에 반도체 칩과 인쇄회로기판 간의 전기적 접속이 이루어지도록 한 구조로서, 상기 반도체 칩과 인쇄회로기판 간의 전기적 신호 전달이 단지 범프에 의해서만 이루어지므로 신호 전달 경로가 매우 짧으며, 따라서, 전기적 특성 측면에서 잇점을 갖는다The flip chip package is a structure in which the semiconductor chip is adhered to the printed circuit board by the bump formed on the bonding pad of the chip, and at the same time, the electrical connection is made between the semiconductor chip and the printed circuit board. Since the electrical signal transfer between the chip and the printed circuit board is made only by bumps, the signal transmission path is very short and therefore has advantages in terms of electrical characteristics.

그러므로, 이러한 플립 칩 패키지는 반도체 칩과 인쇄회로기판을 전기적으로 연결하는 상기와 같은 범프의 조인트(Joint) 안정성을 확보하는 것이 가장 중요하며, 따라서, 상기 플립 칩 패키지는 상기 범프의 조인트 안정성을 확보하고 상기 범프를 외부 환경의 여러 요인으로부터 보호하기 위해 상기 범프가 형성되는 부분, 즉, 반도체 칩과 기판 사이의 공간이 충진되도록 갭-필(Gap-Fill) 부재로 갭-필하는 방식으로 형성되고 있다.Therefore, the flip chip package is most important to secure the joint stability of the bumps electrically connecting the semiconductor chip and the printed circuit board. Therefore, the flip chip package secures the joint stability of the bumps. And gap-filled with a gap-fill member to fill the space in which the bump is formed, ie, the space between the semiconductor chip and the substrate, to protect the bump from various factors of the external environment. have.

그러나, 자세하게 도시하고 설명하지는 않았지만, 전술한 종래의 갭-필 부재는 반도체 칩과 인쇄회로기판 사이의 공간 내부에 갭-필시 상기 갭-필 부재의 흐름의 조건이 변하는 곳에서는 보이드(Void)가 발생하게 되는데, 특히, 반도체 패키지의 구조 특성상 상기 범프가 형성된 곳에서 주로 보이드가 빈번하게 발생하게 된 다.However, although not shown and described in detail, the conventional gap-fill member described above has voids where the conditions of the flow of the gap-fill member change during gap-filling within the space between the semiconductor chip and the printed circuit board. In particular, due to the structural characteristics of the semiconductor package, voids are frequently generated where the bumps are formed.

더욱이, 상기와 같은 보이드는 반도체 칩을 기판 상에 부착시 초음파 접합 방식을 이용하여 플립 칩 패키지를 제작하는 경우, 상기 초음파 접합 방식의 상대적으로 약한 초기 접합 강도로 인해 상기 보이드로 인한 그 심각성은 매우 크게 영향을 미치게 된다.Furthermore, such voids are very serious due to the voids due to the relatively weak initial bonding strength of the ultrasonic bonding method when fabricating a flip chip package using an ultrasonic bonding method when attaching a semiconductor chip onto a substrate. It will greatly affect.

게다가, 상기 보이드는 반도체 패키지의 구조 특성상 갭-필 부재가 흘러들어가는 공간의 간격이 좁을수록 그 발생 확률이 기하 급수적으로 증가하게 된다.In addition, the voids are exponentially increased as the gap between the spaces through which the gap-fill member flows is narrowed due to the structural characteristics of the semiconductor package.

그 결과, 상기와 같은 보이드로 인해 범프의 접합 신뢰성이 저하됨은 물론, 그에 따른 전체 패키지의 작업성, 양산성 및 수율이 저하되게 된다.As a result, the above-mentioned voids lower the bonding reliability of the bumps and, as a result, the workability, mass productivity, and yield of the entire package.

본 발명은 플립 칩 패키지 형성시 갭-필 부재에 의한 보이드의 발생을 방지할 수 있는 플립 칩 패키지 및 그의 제조방법을 제공한다.The present invention provides a flip chip package and a method of manufacturing the same, which can prevent generation of voids caused by a gap-fill member in forming a flip chip package.

본 발명에 따른 플립 칩 패키지는, 복수 개의 본드핑거들이 배치된 기판; 상기 기판 상에 배치되며 상기 각 본드핑거들과 마주하는 본딩패드들을 갖는 반도체 칩; 상기 각 본드핑거들 및 상기 각 본딩패드들을 전기적으로 연결하는 접속 부재; 인접한 접속 부재들 사이의 공간을 1차적으로 갭-필(Gap-Fill)하는 제1갭-필 부재; 및 상기 기판 및 상기 반도체 칩 사이를 2차적으로 갭-필하는 제2갭-필 부재;를 포함한다.A flip chip package according to the present invention includes a substrate on which a plurality of bond fingers are disposed; A semiconductor chip disposed on the substrate and having bonding pads facing the respective bond fingers; A connection member electrically connecting the bond fingers and the respective bonding pads; A first gap-fill member that first gap-fills the space between adjacent connection members; And a second gap-fill member secondaryly gap-filling the substrate and the semiconductor chip.

상기 제1갭-필 부재 및 상기 제2갭-필 부재는 동일한 물질로 이루어진 것을 특징으로 한다.The first gap-fill member and the second gap-fill member may be made of the same material.

상기 제1갭-필 부재는 제1갭-필 물질을 포함하고, 상기 제2갭-필 부재는 제2갭-필 물질을 포함한다.The first gap-fill member includes a first gap-fill material and the second gap-fill member includes a second gap-fill material.

상기 제1갭-필 물질은 NCP(Non Conductive Paste), NCF(Non Conductive Film), ACP(Anisotropic Conductive Paste) 및 ACF(Anisotropic Conductive Film)들 중 적어도 어느 하나 이상을 포함한다.The first gap-fill material may include at least one of non-conductive paste (NCP), non-conductive film (NCF), anisotropic conductive paste (ACP), and anisotropic conductive film (ACF).

상기 제2갭-필 물질은 에폭시 또는 EMC(Epoxy Molding Compound) 중 어느 하나를 포함한다.The second gap-fill material includes either epoxy or an epoxy molding compound (EMC).

또한, 본 발명에 따른 플립 칩 패키지의 제조방법은, 복수 개의 본드핑거들이 배치된 기판을 마련하는 단계; 인접한 상기 본드핑거들 사이의 공간을 제1갭-필(Gap-Fill) 부재로 1차적으로 갭-필하는 단계; 상기 1차적으로 갭-필된 상기 기판 상에 상기 각 본드핑거들과 마주하는 본딩패드들을 갖는 반도체 칩을 마련하는 단계; 상기 각 본드핑거들 및 상기 각 본딩패드들을 전기적으로 연결하는 접속 부재를 형성하는 단계; 및 상기 반도체 칩 및 상기 기판 사이를 제2갭-필 부재로 2차적으로 갭-필하는 단계;를 포함한다.In addition, the method of manufacturing a flip chip package according to the present invention comprises the steps of: preparing a substrate on which a plurality of bond fingers are disposed; Firstly gap-filling the space between adjacent bond fingers with a first gap-fill member; Providing a semiconductor chip having bonding pads facing the respective bond fingers on the primarily gap-filled substrate; Forming a connection member electrically connecting the bond fingers and the respective bonding pads; And secondly gap-filling a second gap-fill member between the semiconductor chip and the substrate.

상기 제1갭-필 부재 및 상기 제2갭-필 부재는 동일한 물질로 형성되는 것을 특징으로 한다.The first gap-fill member and the second gap-fill member may be formed of the same material.

상기 제1갭-필 부재는 제1갭-필 물질로 형성되고, 상기 제2갭-필 부재는 제2갭-필 물질로 형성되는 것을 특징으로 한다.The first gap-fill member is formed of a first gap-fill material, and the second gap-fill member is formed of a second gap-fill material.

상기 제1갭-필 물질은 NCP(Non Conductive Paste), NCF(Non Conductive Film), ACP(Anisotropic Conductive Paste) 및 ACF(Anisotropic Conductive Film)들 중 적어도 어느 하나 이상으로 형성되는 것을 특징으로 한다.The first gap-fill material may be formed of at least one of non-conductive paste (NCP), non-conductive film (NCF), anisotropic conductive paste (ACP), and anisotropic conductive film (ACF).

상기 제2갭-필 물질은 에폭시 또는 EMC(Epoxy Molding Compound) 중 어느 하나로 형성되는 것을 특징으로 한다.The second gap-fill material may be formed of any one of epoxy or epoxy molding compound (EMC).

상기 반도체 칩을 배치시키는 단계에서 상기 반도체 칩은 초음파(Ultra Sonic) 또는 열 압착 방식으로 배치되는 것을 특징으로 한다.In the disposing of the semiconductor chip, the semiconductor chip may be disposed by ultrasonic or thermocompression.

상기 제2갭-필 부재로 2차적으로 갭-필하는 단계에서 상기 제2갭-필 부재는 캐필러리 효과(Capillary Effect) 또는 진공 챔버(Vacuum Chamber) 방식으로 형성되는 것을 특징으로 한다.In the second gap-filling step with the second gap-fill member, the second gap-fill member may be formed in a capillary effect or a vacuum chamber method.

본 발명은 플립 칩 패키지 형성시, 범프 주위에만 먼저 1차로 갭-필 부재가 형성되고, 그런 다음, 나머지 공간에 2차로 갭-필 부재가 형성됨으로써, 범프가 형성된 곳에서의 보이드 발생을 방지할 수 있다.According to the present invention, when a flip chip package is formed, a gap-fill member is first formed only around the bumps, and then a gap-fill member is formed second in the remaining space, thereby preventing voids from occurring where bumps are formed. Can be.

따라서, 본 발명은 범프의 접합 신뢰성 저하를 방지할 수 있으므로, 그에 따른 전체 패키지의 작업성, 양산성 및 수율 저하를 방지할 수 있다.Therefore, since the present invention can prevent the deterioration of the bonding reliability of the bumps, the workability, mass productivity, and yield deterioration of the entire package can be prevented accordingly.

이하, 첨부된 도면들을 참조하여 본 발명의 실시예들에 따른 플립 칩 패키지 및 그의 제조방법에 대하여 상세하게 설명하지만, 본 발명이 하기의 실시예들에 제한되는 것은 아니며, 해당 분야에서 통상의 지식을 가진 자라면 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 본 발명을 다양한 다른 형태로 구현할 수 있을 것이다. Hereinafter, a flip chip package and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and is commonly known in the art. Persons having the present invention may implement the present invention in various other forms without departing from the spirit of the present invention.

자세하게, 도 1은 본 발명의 실시예에 따른 플립 칩 패키지 및 그의 제조방법을 설명하기 위해 도시한 평면도이고, 도 2는 도 1의 X-X' 절단선에 대응하는 본 발명의 실시예에 따른 플립 칩 패키지를 설명하기 위해 도시한 단면도이며, 도 3은 도 1의 Y-Y' 절단선에 대응하는 본 발명의 실시예에 따른 플립 칩 패키지를 설명하기 위해 도시한 단면도로서, 이를 설명하면 다음과 같다.In detail, FIG. 1 is a plan view illustrating a flip chip package and a method of manufacturing the flip chip package according to an exemplary embodiment of the present invention, and FIG. 2 is a flip chip according to the exemplary embodiment of the present invention corresponding to the XX ′ cutting line of FIG. 1. 3 is a cross-sectional view illustrating a package, and FIG. 3 is a cross-sectional view illustrating a flip chip package according to an exemplary embodiment of the present invention corresponding to the YY ′ cutting line of FIG. 1.

도시된 바와 같이 본 발명의 실시예에 따른 플립 칩 패키지(100)는, 기판(102), 반도체 칩(104), 접속 부재(110), 제1갭-필 부재(106) 및 제2갭-필 부재(108)를 포함한다.As shown, the flip chip package 100 according to the embodiment of the present invention may include a substrate 102, a semiconductor chip 104, a connection member 110, a first gap-fill member 106, and a second gap- Peel member 108 is included.

기판(102)은 상면에 병렬 방식으로 배치된 복수 개의 본드핑거들(103)을 포함하며, 본드핑거들(103)은 예를 들면 직사각형 형상을 포함한다. The substrate 102 includes a plurality of bond fingers 103 disposed in a parallel manner on an upper surface, and the bond fingers 103 have a rectangular shape, for example.

반도체 칩(104)은 기판(102) 상에 기판(102)과 마주하도록 배치되며, 또한 반도체 칩(104)은 상면에 기판(102)의 각 본드핑거들(103)과 마주하는 복수 개의 본딩패드들(105)을 포함한다.The semiconductor chip 104 is disposed on the substrate 102 to face the substrate 102, and the semiconductor chip 104 has a plurality of bonding pads facing the respective bond fingers 103 of the substrate 102 on the upper surface thereof. Ones 105.

접속 부재(110)는 기판(102)의 각 본드핑거들(103) 및 반도체 칩(104)의 각 본딩패드들(105)을 전기적으로 상호 연결한다.The connection member 110 electrically interconnects the respective bond fingers 103 of the substrate 102 and the respective bonding pads 105 of the semiconductor chip 104.

접속 부재(110)는 예를 들면 범프를 포함할 수 있으며, 범프 이외에 스터드 타입의 범프도 포함할 수 있다. 또한, 접속 부재(110)는 예를 들면 솔더, 솔더 합금, 금 및 금 합금들로 이루어진 군으로부터 선택된 어느 하나를 포함하며, 플립 칩 패키지의 접합에 사용되는 모든 타입의 범프를 포함할 수 있다.The connection member 110 may include bumps, for example, and may include stud type bumps in addition to the bumps. In addition, the connection member 110 may include any one selected from the group consisting of, for example, solder, solder alloy, gold, and gold alloys, and may include all types of bumps used for bonding a flip chip package.

제1갭-필 부재(106)는 인접한 기판(102)의 각 본드핑거들(103) 및 인접한 기판(102)의 본드핑거들(103) 사이의 공간을 1차적으로 갭-필(Gap-Fill)한다.The first gap-fill member 106 primarily gap-fills the space between each of the bond fingers 103 of the adjacent substrate 102 and the bond fingers 103 of the adjacent substrate 102. )do.

이러한, 제1갭-필 부재(106)는 제1갭-필 물질을 포함하며, 제1갭-필 물질은 예를 들면 언더-필(Under-Fill), NCP(Non Conductive Paste), NCF(Non Conductive Film), ACP(Anisotropic Conductive Paste) 및 ACF(Anisotropic Conductive Film) 물질 중 적어도 어느 하나 이상을 포함한다.Such a first gap-fill member 106 includes a first gap-fill material, and the first gap-fill material may be, for example, under-fill, non-conductive paste, or NCF ( At least one of a non-conductive film (AC), an anisotropic conductive paste (ACP), and an anisotropic conductive film (ACF) material.

여기서, 제1갭-필 부재(106)는 범프와 같은 접속 부재(110)가 배치되는 기판(102)의 각 인접한 본드핑거들(103) 및 기판(102)의 인접한 각 본드핑거들(103) 사이의 공간만을 갭-필함으로써, 접속 부재(110)에 인접한 부분에서 발생하는 보이드(Void)의 발생을 억제할 수 있다.Here, the first gap-fill member 106 may include each adjacent bond fingers 103 of the substrate 102 on which the connection member 110, such as a bump, is disposed, and each adjacent bond fingers 103 of the substrate 102. By gap-filling only the space therebetween, generation | occurrence | production of the void (Void) which generate | occur | produces in the part adjacent to the connection member 110 can be suppressed.

제2갭-필 부재(108)는 기판(102) 및 반도체 칩(104) 사이의 제1갭-필 부재(106)가 갭-필되지 않은 나머지 공간을 2차적으로 갭-필한다.The second gap-fill member 108 secondaryly gap-fills the remaining space where the first gap-fill member 106 between the substrate 102 and the semiconductor chip 104 is not gap-filled.

이러한, 제2갭-필 부재(108)는 제2갭-필 물질을 포함하며, 제2갭-필 물질은 예를 들면, 에폭시 또는 EMC(Epoxy Molding Compound) 중 어느 하나의 물질을 포함한다.This second gap-fill member 108 includes a second gap-fill material, and the second gap-fill material includes, for example, a material of either epoxy or an epoxy molding compound (EMC).

여기서, 제2갭-필 부재(108)는 반도체 칩(104)과 기판(102) 사이의 상이한 열팽창계수를 완화시킬 수 있다.Here, the second gap-fill member 108 may mitigate different coefficients of thermal expansion between the semiconductor chip 104 and the substrate 102.

한편, 전술한 바와 같이 제1갭-필 부재(106) 및 제2갭-필 부재(108)는 각각 보이드 발생 및 열팽창계수의 완화를 위해 서로 상이한 물질을 포함할 수도 있으 며, 이와 달리, 제1갭-필 부재(106) 및 제2갭-필 부재(108)는 서로 동일한 물질을 포함할 수 있다.On the other hand, as described above, the first gap-fill member 106 and the second gap-fill member 108 may include different materials from each other to reduce void generation and thermal expansion coefficient, respectively. The first gap-fill member 106 and the second gap-fill member 108 may include the same material as each other.

또한, 반도체 패키지(100)는 제2갭-필 부재(108) 및 반도체 칩(104)을 포함하는 기판(102)의 상면에 구비되어 반도체 칩(104)을 외부의 스트레스로부터 보호하는 봉지 부재를 더 포함한다.In addition, the semiconductor package 100 may include an encapsulation member provided on an upper surface of the substrate 102 including the second gap-fill member 108 and the semiconductor chip 104 to protect the semiconductor chip 104 from external stress. It includes more.

봉지 부재는 예를 들면 EMC(Epoxy Molding Compound)를 포함한다.The sealing member includes, for example, an epoxy molding compound (EMC).

그리고, 반도체 패키지(100)는 하면에 실장수단으로서 구비된 솔더 볼과 같은 다수의 외부 접속 단자(114)를 포함한다.The semiconductor package 100 includes a plurality of external connection terminals 114 such as solder balls provided on the bottom surface as mounting means.

구체적으로, 도 4a 내지 도 4d는 본 발명의 실시예에 따른 플립 칩 패키지의 제조방법을 설명하기 위해 도시한 공정별 평면도이고, 도 5a 내지 도 5d는 도 1의 X-X' 절단선에 대응하는 본 발명의 실시예에 따른 플립 칩 패키지의 제조방법을 설명하기 위해 도시한 공정별 단면도로서,이를 설명하면 다음과 같다.Specifically, FIGS. 4A to 4D are plan views illustrating processes for manufacturing a flip chip package according to an exemplary embodiment of the present invention, and FIGS. 5A to 5D are patterns corresponding to the XX ′ cutting lines of FIG. 1. A cross-sectional view illustrating a method of manufacturing a flip chip package according to an embodiment of the present invention, which will be described below.

도 4a 및 도 5a를 참조하면, 상면에 복수 개의 본드핑거들(103)이 병렬 방식으로 배치된 기판(120)이 마련된다. 여기서, 복수 개의 본드핑거들(103)은 예를 들면 직사각형 형상으로 형성된다.4A and 5A, a substrate 120 having a plurality of bond fingers 103 arranged in a parallel manner is provided on an upper surface thereof. Here, the plurality of bond fingers 103 is formed in a rectangular shape, for example.

도 4b 및 도 5b를 참조하면, 기판(102)의 인접한 각 본드핑거들(103) 및 인접한 각 본드핑거들(103) 사이의 공간이 제1갭-필(Gap-Fill) 부재(106)가 이용되어 1차적으로 갭-필된다.4B and 5B, the space between the adjacent bond fingers 103 and the adjacent bond fingers 103 of the substrate 102 is defined by the first gap-fill member 106. Used to primary gap-fill.

여기서, 제1갭-필 부재(106)는 제1갭-필 물질을 포함하도록 형성되며, 제1갭-필 물질은 예를 들면, 언더-필(Under-Fill), NCP(Non Conductive Paste), NCF(Non Conductive Film), ACP(Anisotropic Conductive Paste) 및 ACF(Anisotropic Conductive Film) 물질 중 적어도 어느 하나 이상으로 형성된다.Here, the first gap-fill member 106 is formed to include a first gap-fill material, and the first gap-fill material may be, for example, under-fill or non-conductive paste (NCP). , At least one of a non-conductive film (NCF), an anisotropic conductive paste (ACP), and an anisotropic conductive film (ACF) material.

도 4c 및 도 5c를 참조하면, 제1갭-필 부재(106)가 이용되어 1차적으로 갭-필된 기판(102) 상에 반도체 칩(104)이 배치된다.4C and 5C, a first gap-fill member 106 is used to place a semiconductor chip 104 on a first gap-filled substrate 102.

이때, 반도체 칩(104)은 기판(102)의 각 본드핑거들(103)과 마주하는 본딩패드들(105)이 형성되며, 각 본드핑거들(103) 및 각 본딩패드들(105)을 전기적으로 연결하는 접속 부재(110)가 각 본딩패드들(105) 상에 형성된다.At this time, the semiconductor chip 104 is formed with bonding pads 105 facing the respective bond fingers 103 of the substrate 102, and the respective bonding fingers 103 and the bonding pads 105 are electrically connected to each other. Connection members 110 connected to each other are formed on the respective bonding pads 105.

또한, 반도체 칩(104)은 초음파(Ultra Sonic) 또는 열 압착 방식으로 기판 상에 배치된다.In addition, the semiconductor chip 104 is disposed on the substrate by an ultrasonic or thermocompression method.

도 4d 및 도 5d를 참조하면, 제1갭-필 부재(106)가 갭-필되지 않은 나머지 반도체 칩(104) 및 기판(102) 사이의 공간이 제2갭-필 부재(108)가 이용되어 2차적으로 갭-필된다.4D and 5D, the space between the remaining semiconductor chip 104 and the substrate 102 where the first gap-fill member 106 is not gap-filled is used by the second gap-fill member 108. And secondarily gap-filled.

여기서, 제2갭-필 부재(108)는 캐필러리 효과(Capillary Effect) 또는 진공 챔버(Vacuum Chamber) 방식으로 형성된다.Here, the second gap-fill member 108 is formed in a capillary effect or a vacuum chamber method.

또한, 제2갭-필 부재(108)는 제2갭-필 물질을 포함하도록 형성되며, 제2갭-필 물질은 예를 들면 에폭시 또는 EMC(Epoxy Molding Compound) 중 어느 하나의 물질로 형성된다.In addition, the second gap-fill member 108 is formed to include a second gap-fill material, and the second gap-fill material is formed of, for example, any one of epoxy or epoxy molding compound (EMC). .

한편, 전술한 바와 같이 제1갭-필 부재(106) 및 제2갭-필 부재(108)는 각각 보이드 발생 및 열팽창계수의 완화를 위해 서로 상이한 물질로 형성될 수 있지만, 이와 달리, 제1갭-필 부재(106) 및 제2갭-필 부재(108)는 서로 동일한 물질로 형성 될 수 있다.On the other hand, as described above, the first gap-fill member 106 and the second gap-fill member 108 may be formed of different materials from each other to reduce void generation and thermal expansion coefficient, respectively. The gap-fill member 106 and the second gap-fill member 108 may be formed of the same material as each other.

이후, 도시하지는 않았지만, 제2갭-필 부재 및 반도체 칩을 포함하는 기판의 상면이 반도체 칩을 외부의 스트레스로부터 보호하기 위해 EMC(Epoxy Molding Compound)와 같은 봉지 부재로 밀봉되며, 그런 다음, 기판 하면에 실장수단으로서 솔더 볼과 같은 다수의 외부 접속 단자가 부착된다.Subsequently, although not shown, the top surface of the substrate including the second gap-fill member and the semiconductor chip is sealed with an encapsulation member such as an epoxy molding compound (EMC) to protect the semiconductor chip from external stress, and then the substrate A plurality of external connection terminals such as solder balls are attached to the lower surface as mounting means.

전술한 바와 같이 본 발명은, 상기와 같이 범프 주위에만 1차로 갭-필 부재가 형성되고, 그런 다음, 나머지 공간에 2차로 갭-필 부재가 형성됨으로써, 갭-필 부재의 흐름의 조건이 변하는 곳인 범프가 형성된 곳에서의 보이드 발생을 방지할 수 있다.As described above, according to the present invention, the gap-fill member is formed first only around the bumps as described above, and then the gap-fill member is formed secondly in the remaining space, thereby changing the conditions of the flow of the gap-fill member. It is possible to prevent the generation of voids in the place where the bump is formed.

따라서, 본 발명은 범프의 접합 신뢰성 저하를 방지할 수 있으므로, 전체 패키지의 작업성, 양산성 및 수율 저하를 방지할 수 있다.Therefore, since this invention can prevent the fall of the joining reliability of bump, it can prevent the fall of workability, mass productivity, and a yield of the whole package.

앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술 될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

도 1은 본 발명의 실시예에 따른 플립 칩 패키지 및 그의 제조방법을 설명하기 위해 도시한 평면도.1 is a plan view illustrating a flip chip package and a method of manufacturing the same according to an embodiment of the present invention.

도 2는 도 1의 X-X' 절단선에 대응하는 본 발명의 실시예에 따른 플립 칩 패키지를 설명하기 위해 도시한 단면도.FIG. 2 is a cross-sectional view illustrating a flip chip package according to an embodiment of the present invention corresponding to the cut line X-X 'of FIG.

도 3은 도 1의 Y-Y' 절단선에 대응하는 본 발명의 실시예에 따른 플립 칩 패키지를 설명하기 위해 도시한 단면도.3 is a cross-sectional view for explaining a flip chip package according to an embodiment of the present invention corresponding to the cutting line Y-Y 'of FIG.

도 4a 내지 도 4d는 본 발명의 실시예에 따른 플립 칩 패키지의 제조방법을 설명하기 위해 도시한 공정별 평면도.4A to 4D are plan views illustrating processes for illustrating a method of manufacturing a flip chip package according to an exemplary embodiment of the present invention.

도 5a 내지 도 5d는 도 1의 X-X' 절단선에 대응하는 본 발명의 실시예에 따른 플립 칩 패키지의 제조방법을 설명하기 위해 도시한 공정별 단면도.5A through 5D are cross-sectional views illustrating a method of manufacturing a flip chip package according to an exemplary embodiment of the present invention corresponding to the cut line X-X ′ of FIG. 1.

Claims (12)

복수 개의 본드핑거들이 배치된 기판;A substrate on which a plurality of bond fingers are disposed; 상기 기판 상에 배치되며 상기 각 본드핑거들과 마주하는 본딩패드들을 갖는 반도체 칩;A semiconductor chip disposed on the substrate and having bonding pads facing the respective bond fingers; 상기 각 본드핑거들 및 상기 각 본딩패드들을 전기적으로 연결하는 접속 부재;A connection member electrically connecting the bond fingers and the respective bonding pads; 인접한 접속 부재들 사이의 공간을 1차적으로 갭-필(Gap-Fill)하는 제1갭-필 부재; 및A first gap-fill member that first gap-fills the space between adjacent connection members; And 상기 기판 및 상기 반도체 칩 사이를 2차적으로 갭-필하는 제2갭-필 부재;A second gap-fill member secondaryly gap-filling between the substrate and the semiconductor chip; 를 포함하는 것을 특징으로 하는 플립 칩 패키지.Flip chip package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제1갭-필 부재 및 상기 제2갭-필 부재는 동일한 물질로 이루어진 것을 특징으로 하는 플립 칩 패키지.And the first gap-fill member and the second gap-fill member are made of the same material. 제 1 항에 있어서,The method of claim 1, 상기 제1갭-필 부재는 제1갭-필 물질을 포함하고, 상기 제2갭-필 부재는 제2갭-필 물질을 포함하는 것을 특징으로 하는 플립 칩 패키지.And wherein the first gap-fill member comprises a first gap-fill material and the second gap-fill member comprises a second gap-fill material. 제 3 항에 있어서,The method of claim 3, wherein 상기 제1갭-필 물질은 NCP(Non Conductive Paste), NCF(Non Conductive Film), ACP(Anisotropic Conductive Paste) 및 ACF(Anisotropic Conductive Film)들 중 적어도 어느 하나 이상을 포함하는 것을 특징으로 하는 플립 칩 패키지.The first gap-fill material may include at least one of a non-conductive paste (NCP), a non-conductive film (NCF), an anisotropic conductive paste (ACP), and an anisotropic conductive film (ACF). package. 제 3 항에 있어서,The method of claim 3, wherein 상기 제2갭-필 물질은 에폭시 또는 EMC(Epoxy Molding Compound) 중 어느 하나를 포함하는 것을 특징으로 하는 플립 칩 패키지.And the second gap-fill material comprises any one of epoxy or epoxy molding compound (EMC). 복수 개의 본드핑거들이 배치된 기판을 마련하는 단계;Providing a substrate on which a plurality of bond fingers are disposed; 인접한 상기 본드핑거들 사이의 공간을 제1갭-필(Gap-Fill) 부재로 1차적으로 갭-필하는 단계;Firstly gap-filling the space between adjacent bond fingers with a first gap-fill member; 상기 1차적으로 갭-필된 상기 기판 상에 상기 각 본드핑거들과 마주하는 본딩패드들을 갖는 반도체 칩을 마련하는 단계;Providing a semiconductor chip having bonding pads facing the respective bond fingers on the primarily gap-filled substrate; 상기 각 본드핑거들 및 상기 각 본딩패드들을 전기적으로 연결하는 접속 부재를 형성하는 단계; 및Forming a connection member electrically connecting the bond fingers and the respective bonding pads; And 상기 반도체 칩 및 상기 기판 사이를 제2갭-필 부재로 2차적으로 갭-필하는 단계;Secondly gap-filling a second gap-fill member between the semiconductor chip and the substrate; 를 포함하는 것을 특징으로 하는 플립 칩 패키지의 제조방법.Method of manufacturing a flip chip package comprising a. 제 6 항에 있어서,The method of claim 6, 상기 제1갭-필 부재 및 상기 제2갭-필 부재는 동일한 물질로 형성되는 것을 특징으로 하는 플립 칩 패키지의 제조방법.And the first gap-fill member and the second gap-fill member are formed of the same material. 제 6 항에 있어서,The method of claim 6, 상기 제1갭-필 부재는 제1갭-필 물질로 형성되고, 상기 제2갭-필 부재는 제2갭-필 물질로 형성되는 것을 특징으로 하는 플립 칩 패키지의 제조방법.And the first gap-fill member is formed of a first gap-fill material, and the second gap-fill member is formed of a second gap-fill material. 제 8 항에 있어서,The method of claim 8, 상기 제1갭-필 물질은 NCP(Non Conductive Paste), NCF(Non Conductive Film), ACP(Anisotropic Conductive Paste) 및 ACF(Anisotropic Conductive Film)들 중 적어도 어느 하나 이상으로 형성되는 것을 특징으로 하는 플립 칩 패키지의 제조방법.The first gap-fill material may be formed of at least one of a non-conductive paste (NCP), a non-conductive film (NCF), an anisotropic conductive paste (ACP), and an anisotropic conductive film (ACF). Method of making the package. 제 8 항에 있어서,The method of claim 8, 상기 제2갭-필 물질은 에폭시 또는 EMC(Epoxy Molding Compound) 중 어느 하나로 형성되는 것을 특징으로 하는 플립 칩 패키지의 제조방법.The second gap-fill material is a method of manufacturing a flip chip package, characterized in that formed of either epoxy or epoxy molding compound (EMC). 제 6 항에 있어서,The method of claim 6, 상기 반도체 칩을 배치시키는 단계에서 상기 반도체 칩은 초음파(Ultra Sonic) 또는 열 압착 방식으로 배치되는 것을 특징으로 하는 플립 칩 패키지의 제조방법.In the step of placing the semiconductor chip, the semiconductor chip is a manufacturing method of a flip chip package, characterized in that arranged in the ultrasonic (Ultra Sonic) or thermal compression method. 제 6 항에 있어서,The method of claim 6, 상기 제2갭-필 부재로 2차적으로 갭-필하는 단계에서 상기 제2갭-필 부재는 캐필러리 효과(Capillary Effect) 또는 진공 챔버(Vacuum Chamber) 방식으로 형성되는 것을 특징으로 하는 플립 칩 패키지의 제조방법.In the step of second gap-filling with the second gap-fill member, the second gap-fill member is formed in a capillary effect (Capillary Effect) or a vacuum chamber (Vacuum Chamber) method characterized in that the flip chip Method of making the package.
KR1020080089471A 2008-09-10 2008-09-10 Flip chip package and method of fabricating the same KR20100030499A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324696B2 (en) 2013-08-29 2016-04-26 Samsung Electronics Co., Ltd. Package-on-package devices, methods of fabricating the same, and semiconductor packages

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324696B2 (en) 2013-08-29 2016-04-26 Samsung Electronics Co., Ltd. Package-on-package devices, methods of fabricating the same, and semiconductor packages

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