KR20100024275A - Apparatus and method for interleaving in communication system - Google Patents

Abstract

PURPOSE: An apparatus and a method for interleaving in a communication system are provided to implement interleaving of CTC(Convolutional Turbo Code) coded bits which is coded per sub by applying different interleaving pattern according to a size of a packet. CONSTITUTION: An interleaver decides a variable representing the randomness and a variable representing uniformity(301). The Interleaver initializes an index of the code bit and an index of the provisional output address(303). The interleaver decides an interleaving pattern according to a variable which represents uniformity(305). The interleaver generates a provisional output address(307). The interleaver confirms the validity of the provisional output address(309). The interleaver interleaves a bit to the provisional output address(311). The interleaver increases the index of the code bit and the index of the provisional output address one by one(313). The interleaver confirms the crystallization of the output address for interleaving all bits of a sub block(315).

Description

Interleaving apparatus and method in communication system {APPARATUS AND METHOD FOR INTERLEAVING IN COMMUNICATION SYSTEM}

The present invention relates to an interleaving apparatus and method in a communication system, and more particularly, to an apparatus and method for generating an output address for interleaving a signal encoded through a convolutional turbo code (CTC) in a communication system.

Wired and wireless digital communication systems use error correction codes to correct errors on transmission paths. For example, a communication system corrects an error using a CTC that receives and processes two information bits every clock.

In the case of using the CTC, the communication system generates code bits by CTC encoding the information bit string according to a predetermined code rate to generate a sub packet. Thereafter, the communication system interleaves the CTC coded code bits for each subblock. Thereafter, the communication system punctures the interleaved bits according to a transmission rate to generate a subpacket for transmission.

As described above, the communication system performs subblock interleaving on the CTC coded code bits. In this case, randomness of the interleaving pattern for the sign bit affects performance in a fading channel, and uniformity affects performance for puncturing. Accordingly, the communication system requires an interleaving technique for satisfying the performance of the fading channel and the performance of puncturing for packets of various sizes.

It is therefore an object of the present invention to provide an apparatus and method for generating an output address for interleaving in a communication system.

Another object of the present invention is to provide an interleaving apparatus and method for satisfying the superiority of performance in a fading channel and performance of puncturing for packets of various sizes in a communication system.

It is still another object of the present invention to provide an apparatus and method for generating an output address for interleaving a code bit encoded through a convolutional turbo code (CTC) in a communication system.

According to a first aspect of the present invention for achieving the objects of the present invention, an interleaving method in a communication system includes the steps of determining an interleaving pattern according to a parameter representing uniformity and interleaving according to the determined interleaving pattern. It characterized in that it comprises a process of generating an output address for.

According to a second aspect of the present invention, an interleaving apparatus in a communication system includes an interleaving control unit for determining an interleaving pattern according to a parameter representing uniformity, and a sub generation unit for generating an output address for interleaving according to the determined interleaving pattern. And a block interleaver.

According to a third aspect of the present invention, an apparatus for generating a sub packet in a communication system includes a convolutional turbo coder that generates at least one code bit by encoding an input information bit into a convolutional turbo code (CTC). And an interleaver interleaving the at least one subblocks of the code bits to have different interleaving patterns according to variables representing uniformity, and puncturing the bits of the interleaved subblocks according to a predetermined transmission rate. And a bit selector for generating a subpacket to be transmitted.

As described above, by performing interleaving for each subblock of CTC-coded coded bits by applying different interleaving patterns according to packet sizes in a communication system, performance of a fading channel and performance of puncturing for packets of various sizes are measured. There is an advantage that can satisfy the excellence.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Hereinafter, a description will be given of a technique for interleaving a coded symbol coded through a convolutional turbo code (CTC) in a communication system.

Hereinafter, a channel interleaver used in an orthogonal frequency division multiplexing (OFDM) wireless communication system will be described. However, the interleaving scheme according to the present invention can be equally applied to the channel interleaver of a communication system using another communication scheme.

1 is a diagram showing a configuration for generating a subpacket in a communication system according to the present invention;

As shown in FIG. 1, the communication system includes a CTC encoder 100, a subblock interleaver 102, a bit selector 104, and an interleaving control unit 106 to generate a sub packet.

The CTC encoder 100 generates a code bit by CTC encoding an information bit string input for each clock according to a predetermined code rate. For example, when the code rate is 1/3, the CTC encoder 100 generates and outputs six code bits by performing CTC encoding on two input information bits. In this case, the six bit strings output from the CTC encoder 100 form two information subblocks and four parity subblocks, and each subblock is independently interleaved through the subblock interleaver 102. .

The subblock interleaver 102 interleaves and outputs a plurality of subblocks provided from the CTC encoder 100 under the control of the interleaving controller 106. In this case, the subblock interleaver 102 generates an output address for interleaving the code bits included in the subblock by applying the f (k) value provided from the interleaving controller 106 to Equation 1 below. do.

은 m과 J의 나눗셈에 대한 몫의 내림(flooring) 연산을 나타내고, 상기 BRO_m(y)는 상기 y의 m비트 값의 역수를 나타낸다. 예를 들어, BRO₃(6)은 3(= 011(2))을 나타낸다.Here, T _k denotes a temporary output address of the i-th bit for interleaving, m denotes a variable representing randomness for sub-block interleaving, and J denotes uniformity for sub-block interleaving. Denotes the index of the temporary output address. In addition, the mod represents a modulo operation for calculating the remainder to the division, and the / represents a divider operation for calculating the quotient for the division.

Denotes a flooring operation of the quotient of the division of m and J, and BRO _m (y) represents the inverse of the m-bit value of y. For example, BRO ₃ (6) represents 3 (= 011 (2)).

According to Equation 1, when the variable representing uniformity is not 4, the subblock interleaver 102 sequentially configures the interleaved bit groups under the control of the interleaving controller 106. To interleave the sign bits of the subblock. On the other hand, when the variable representing uniformity is 4, the subblock interleaver 102 may intersect the order of the interleaved bit groups as shown in FIG. 2 according to the control of the interleaving controller 106. Interleaves the sign bits of the sub block.

The interleaving control unit 106 controls the subblock interleaver 102 to vary the interleaving pattern according to a variable J representing uniformity so that puncturing of the interleaved symbol is uniform. For example, when the variable representing uniformity is not 4, the interleaving control unit 106 may configure the subblock interleaver 102 to sequentially configure the interleaved bit groups in the subblock according to an interleaving pattern. To control. On the other hand, when the variable representing uniformity is 4, the interleaving control unit 106 interleaves the interleaving pattern so that the order of the interleaved bit groups in the subblock intersects as shown in FIG. 102).

The bit selector 104 punctures the code bits of the interleaved subblocks received from the subblock interleaver 102 according to a predetermined transmission rate to generate a subpacket to be transmitted.

In the above-described embodiment, the subblock interleaver 102 outputs addresses for bits encoded according to the interleaving pattern f (k) determined by the interleaving control unit 106 according to a variable J representing uniformity. Interleaving is performed by generating. In another embodiment, the interleaving controller 106 generates an output address for bits encoded to satisfy an interleaving pattern determined according to a parameter representing uniformity. Accordingly, the subblock interleaver 102 may perform interleaving according to the output address provided from the interleaving controller 106. In another embodiment, the sub block interleaver 102 may be configured to include the interleaving control unit 106.

2 illustrates an interleaving pattern in a communication system according to an exemplary embodiment of the present invention.

As shown in FIG. 2, when the variable J representing uniformity is 4, the subblock interleaver 102 configures four bit groups by interleaving the code bits included in the subblock. At this time, the subblock interleaver 102 interleaves the sign bits of the subblock so that the order of the interleaved bit groups intersects. That is, the subblock interleaver 102 generates an output address for interleaving the code bits of the subblock using Equation 1 so that the order of the interleaved bit groups intersects.

Hereinafter, a method for interleaving by changing an interleaving pattern according to a parameter representing uniformity in a communication system will be described. The operation of generating an output address of a bit for interleaving of FIG. 3 may be performed by the subblock interleaver 102 or the interleaving controller 106 of FIG. 1. Accordingly, the following description will be based on the assumption that an output address of a bit for interleaving is generated in an interleaver in which the sub-block interleaver 102 and the interleaving control unit 106 are integrated.

3 illustrates an interleaving procedure in a communication system according to an embodiment of the present invention.

Referring to FIG. 3, first, in step 301, the interleaver determines a variable m representing randomness defined for the size of a subblock and a variable J representing uniformity.

After determining the variable m indicating the randomness and the variable J indicating the uniformity, the interleaver initializes the index i of the sign bit for interleaving and the index k of the temporary output address in step 303. Here, the index i of the sign bit for interleaving and the index k of the temporary output address have an initial value of 0.

In step 305, the interleaver determines the interleaving pattern according to the uniformity J indicating uniformity so that puncturing of the code bits of the interleaved subblock is uniform. For example, the interleaver selects an equation for calculating an output address of code bits for interleaving according to the variable J representing uniformity using Equation 1. In this case, when the variable representing uniformity is less than 4, the interleaver selects an equation having an interleaving pattern in which the order of interleaved bit groups in the subblock is sequential. On the other hand, when the variable representing uniformity is 4, the interleaver selects an equation having an interleaving pattern in which the order of interleaved bit groups in the subblock intersects.

After determining the interleaving pattern, the interleaver proceeds to step 307 to generate a temporary output address T _k that matches the determined interleaving pattern. That is, the interleaver generates a temporary output address of code bits for interleaving using an equation according to the interleaving pattern selected in step 305.

After generating the temporary output address, the interleaver proceeds to step 309 to check whether the temporary output address is valid. That is, the interleaver compares the temporary output address T _k with the size N of the subblock to determine the validity of the temporary output address generated in step 307. At this time, the sub block is composed of bits from 0 to (N-1). In addition, since the temporary output address index also sets the initial value to 0, the interleaver compares the index of the temporary output address with N-1.

If the temporary output address is smaller than the size of the sub block (T _k ≤ (N-1)), the interleaver proceeds to step 311 and outputs an AD address for interleaving the i th bit of the temporary output address. _i ) (AD _i = T _k ). That is, the interleaver interleaves the i th bit to the temporary output address.

In step 313, the interleaver increments the index i of the sign bit for interleaving and the index k of the temporary output address by one (i ++, k ++).

After increasing the index i of the interleaving bit and the index k of the temporary output address, the interleaver proceeds to step 315 to determine whether the output address for interleaving of all the bits of the subblock is determined. That is, the interleaver compares the index i of the bit for determining the next output address with the size N of the subblock.

On the other hand, if the temporary output address is greater than or equal to the size of the subblock in step 309 (T _k > (N-1)), the interleaver proceeds to step 317 and discards the temporary output address, and temporarily outputs the temporary output address. Increment the index (k) of the address (k ++).

After increasing the index k of the temporary output address, the interleaver proceeds to step 315 to determine whether the output address for interleaving for all bits of the subblock is determined. That is, the interleaver compares the index i of the bit for determining the next output address with the size N of the subblock. At this time, the sub block is composed of bits from 0 to (N-1). In addition, since the index of the bit for interleaving also sets the initial value to 0, the interleaver compares the index of the bit for interleaving with N-1.

If the output address for interleaving for all bits is not determined (i < RTI ID = 0.0 > (N-1)), < / RTI > the interleaver returns to step 305 to uniformly puncture the symbols of the interleaved subblock. The interleaving pattern is determined according to the variable J representing uniformity.

On the other hand, when the output address for interleaving for all bits is determined (i> (N-1)), the interleaver ends the present algorithm.

As described above, when the variable representing the uniformity is 4, the subblock interleaver 102 performs interleaving so that the order of interleaved bit groups intersects so that the puncturing according to the transmission rate is uniform. That is, when the subblock interleaver 102 sequentially interleaves the order of the interleaved bit groups, the bit selector 104 punctures the (4k + 2) th bit group and the (4k + 3) th bit group through puncturing. Perforate. In this case, consecutive (4k + 2) th bits and (4k + 3) th bits are punctured in the interleaved subblock.

However, when the interleaving of the interleaved bit groups in the subblock interleaver 102 intersects, the bit selector 104 punctures the (4k + 1) th bit group and the (4k + 3) th bit group through puncturing. Perforate. In this case, since the (4k + 1) -th bit and the (4k + 3) -th bit in the interleaved sub-block are punctured, the puncturing is uniform compared to the method of sequentially interleaving the order of the bit groups.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

1 is a diagram showing a configuration for generating a subpacket in a communication system according to the present invention;

2 illustrates an interleaving pattern in a communication system according to an embodiment of the present invention; and

3 is a diagram illustrating an interleaving procedure in a communication system according to an embodiment of the present invention;

Claims (16)

In the interleaving method in a communication system, Determining an interleaving pattern according to a parameter representing uniformity, And generating an output address for interleaving according to the determined interleaving pattern. The method of claim 1, The process of determining the interleaving pattern, When the variable representing the uniformity is 4, determining an interleaving pattern for interleaving such that the order of interleaved bit groups is crossed; And determining an interleaving pattern for interleaving such that the order of the interleaved bit groups is sequential when the variable representing the uniformity is not four. The method of claim 1, The generating of the output address may include generating an output address using an interleaving pattern determined according to a parameter representing uniformity as shown in Equation 2 below.

Where T _k is a temporary output address of the i-th bit for interleaving, m is a variable representing randomness for sub-block interleaving, J is a variable representing uniformity for sub-block interleaving, K is an index of a temporary output address, mod is a modulo operation for calculating the remainder for division, / is a divider operation for calculating the quotient for division, and

Is a flooring operation of the quotient of the division of m and J, wherein BRO _m (y) represents the inverse of the m-bit value of y. The method of claim 1, Determining the validity of the output address after generating the output address; And if the output address is valid, mapping the corresponding bit of the encoded sub-block to the output address and interleaving. The method of claim 4, wherein The process of determining the validity, And comparing the output address with the size of the subblock to determine whether the output address is valid. An interleaving apparatus in a communication system, An interleaving control unit for determining an interleaving pattern according to a parameter representing uniformity, And a sub-block interleaver for generating an output address for interleaving according to the determined interleaving pattern. The method of claim 6, The interleaving controller, when the variable representing the uniformity is 4, determines an interleaving pattern for interleaving such that the order of interleaved bit groups is crossed, And if the variable representing the uniformity is not 4, determining an interleaving pattern for interleaving such that the order of interleaved bit groups is sequential. The method of claim 6, The subblock interleaver generates an output address using an interleaving pattern determined according to a variable representing uniformity by the interleaving controller as shown in Equation 3 below.

Where T _k is a temporary output address of the i-th bit for interleaving, m is a variable representing randomness for sub-block interleaving, J is a variable representing uniformity for sub-block interleaving, K is an index of a temporary output address, mod is a modulo operation for calculating the remainder for division, / is a divider operation for calculating the quotient for division, and

Is a flooring operation of the quotient of the division of m and J, wherein BRO _m (y) represents the inverse of the m-bit value of y. The method of claim 1, And the subblock interleaver determines the validity of the generated output address and interleaves the corresponding bit of the encoded subblock to the output address when the output address is valid. The method of claim 9, And the subblock interleaver compares the size of the output address with the size of the subblock to determine whether the output address is valid. An apparatus for generating a sub packet in a communication system, A convolutional turbo coder for encoding at least one code bit by encoding an input information bit into a convolutional turbo code (CTC); An interleaver for interleaving the at least one subblocks of the code bits to have different interleaving patterns according to variables representing uniformity; And a bit selector for puncturing the code bits of the interleaved subblocks according to a predetermined transmission rate to generate a subpacket to be transmitted. The method of claim 10, The interleaver may include: an interleaving controller configured to determine an interleaving pattern according to a parameter representing the uniformity; And a sub-block interleaver for generating an output address for interleaving according to the determined interleaving pattern. The method of claim 12, The interleaving controller, when the variable representing the uniformity is 4, determines an interleaving pattern for interleaving such that the order of interleaved bit groups is crossed, And if the variable representing the uniformity is not 4, determining an interleaving pattern for interleaving such that the order of interleaved bit groups is sequential. The method of claim 12, The subblock interleaver generates an output address using an interleaving pattern determined according to a parameter representing uniformity in the interleaving controller as shown in Equation 4 below.

Where T _k is a temporary output address of the i-th bit for interleaving, m is a variable representing randomness for sub-block interleaving, J is a variable representing uniformity for sub-block interleaving, K is an index of a temporary output address, mod is a modulo operation for calculating the remainder for division, / is a divider operation for calculating the quotient for division, and

Is a flooring operation of the quotient of the division of m and J, wherein BRO _m (y) represents the inverse of the m-bit value of y. The method of claim 12, And the subblock interleaver determines the validity of the generated output address and interleaves the corresponding bit of the encoded subblock to the output address when the output address is valid. The method of claim 15, And the subblock interleaver determines whether the output address is valid.

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