KR20100021748A

KR20100021748A - Non volatile memory device and and operating method thereof

Info

Publication number: KR20100021748A
Application number: KR1020080080334A
Authority: KR
Inventors: 이정환
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-08-18
Filing date: 2008-08-18
Publication date: 2010-02-26

Abstract

The present invention relates to a nonvolatile memory device and a method of operating the same, and includes a plurality of memory cells connected in series between a bit line and a common source line, and a common source voltage generator configured to apply a source voltage to the common source line. The common source voltage generator outputs the source voltage lower than the potential of the bit line and gradually lowered to the ground voltage to discharge the potential of the precharged bit line during the verify operation or the read operation of the device. And a method of operation thereof.

Description

Non-volatile memory device and its operating method

The present invention relates to a nonvolatile memory device and a method of operating the same, and more particularly, to a nonvolatile memory device and a method of operating the same that can reduce source line bouncing of a memory cell array.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in a specific cell. . In order to determine whether to program a specific cell included in the memory cell array, a voltage level of a bit line connected to a cell string including the specific cell is evaluated.

In order to accurately determine whether a specific cell is programmed, a read margin is better. In particular, since each cell of a nonvolatile memory device to which the Multi Level Cell (MLC) programming method is applied has a different distribution of threshold voltages than cells to which the Single Level Cell (SLC) programming method is applied, Sufficient sensing margin should be available for each distribution.

However, due to the bouncing of the source line generated according to the characteristics of the memory cell array, the sensing margin is reduced by changing the potential of the bit line in the target cell during the read operation and the program verify operation of the nonvolatile memory device. .

This causes the source line bouncing due to the resistance of the metal lines from the bit line to the common source line. Referring to FIG. 1, in a read operation and a program verify operation of a nonvolatile memory device, after a bit line to which a target cell is connected is precharged to a high level using a page buffer, whether the potential of the bit line is discharged or the high level is changed. When the bit line is discharged, the potential of the source line is increased by the resistance value to the common source line, which causes the bounce phenomenon. This bouncing phenomenon acts as a noise of the source line to reduce the sensing current of the cell. This causes a malfunction of the read operation and the program verify operation of the nonvolatile memory device.

SUMMARY OF THE INVENTION The present invention provides a bit line and a common source during a read operation and a verify operation of a nonvolatile memory device using a common source line voltage generator that applies a control voltage lowered step by step to a common source line of a nonvolatile memory device. The present invention provides a nonvolatile memory device and a method of operating the same, which reduce the current flowing through the bit line by reducing the potential difference between the lines.

A nonvolatile memory device according to an embodiment of the present invention includes a plurality of memory cells connected in series between a bit line and a common source line, a common source voltage generator for applying a source voltage to the common source line, and the common source. The voltage generator outputs the source voltage lower than the potential of the bit line and gradually lowered to the ground voltage to discharge the potential of the precharged bit line during the verify operation or the read operation of the device.

The bit line potential is 1V and the source voltage starts at a potential of 0.9V and falls to the ground potential, but gradually falls by a step voltage.

The source voltage gradually decreases by 0.1V.

A method of operating a nonvolatile memory device according to an embodiment of the present invention includes precharging a bit line in which a plurality of memory cells are connected in series, and applying a pass voltage to a plurality of non-selected memory cells among the plurality of memory cells. And applying a read voltage or a verify voltage to a selected memory cell among the plurality of memory cells, and applying a common source voltage to a common source line connected in series with the plurality of memory cells to discharge the voltage of the precharged bit line. However, the common source voltage is lower than the bit line potential and gradually decreases to the ground voltage.

The common source voltage is

The common source voltage is lower than the potential of the bit line in order to discharge the potential of the precharged bit line during the verify operation or the read operation, and sequentially descends to the ground voltage by the step voltage.

The bit line potential is 1V and the source voltage starts with a potential of 0.9V and drops to the ground potential.

The step voltage is 0.1V.

According to an embodiment of the present invention, a common source line voltage generator for applying a control voltage lowered step by step to a common source line of a nonvolatile memory device is common with a bit line during read and verify operations of the nonvolatile memory device. The sensing margin of the device may be increased by reducing the potential difference between the source lines to reduce the current flowing through the bit lines, thereby reducing the bouncing effect of the source lines.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

2 is a configuration diagram of a nonvolatile memory device according to an embodiment of the present invention.

2, a nonvolatile memory device includes a memory cell array 100 and a common source voltage generator 200.

In the memory cell array 100, a plurality of memory cells MC <0> to MC <31>, a drain select transistor DST, and a source select transistor SST may include a bit line BL and a common source line CSL. Contains a number of strings connected in series

The common source voltage generator 200 is connected to the common source line CSL to precharge the bit line BL during read and verify operations of the nonvolatile memory device, and then gradually moves from the constant voltage to the ground voltage in the discharge period. The lowering control voltage is applied to the common source line CSL.

3 is a potential graph illustrating a control voltage output from a common source voltage generator.

Referring to FIG. 3, the control voltage output from the common source voltage generator is gradually lowered by a predetermined step and lowered to the ground voltage.

Referring to FIGS. 2 and 3, a read operation and a verify operation of a nonvolatile memory device will be described below.

As an example, a memory cell that performs a read operation or a verify operation is assumed to be an MC <31> cell.

First, the bit line BL is precharged to a predetermined potential (for example, 1V) by using a page buffer (not shown) connected to the bit line BL of the memory cell array 100.

Thereafter, a high level signal is applied to the drain select line DSL and the source select line SSL to turn on the drain select transistor DST and the source select transistor SST. In this case, a pass voltage is applied to the word lines WL <30> to WL <0> connected to the non-selected memory cells MC <30> to MC <0>, so that the unselected memory cells MC <30> to MC < 0>) is turned on, that is, a channel is formed.

A read voltage during a read operation and a verify voltage during a verify operation are applied to the selected memory cell MC <31> to turn the memory cell on or off according to the threshold voltage of the MC <31>. At this time, when the MC <31> is turned on, the bit line BL precharged to the predetermined potential is discharged through the common source line CSL.

The common source voltage generator 200 outputs a control voltage to the common source line CSL during the discharge operation of the bit line BL to discharge the potential of the bit line BL. For example, when the potential of the bit line BL is discharged at 1 V, the common source voltage generator 200 outputs a control voltage of, for example, 0.9 V lower than the potential of the bit line BL. In addition, a predetermined potential decreases for a predetermined time, that is, the control voltage gradually decreases by the step voltage to the ground voltage OV. It is preferable that the control voltage falls by 0.1V to 0.2V.

As a result, the bit line BL reduces the potential difference between the bit line BL and the common source line CSL rather than discharging the potential to the conventional ground voltage, thereby gradually discharging the potential of the source line. Bouncing can be reduced.

By reducing the bouncing of the source line, the noise of the source line is suppressed, thereby increasing the sensing margin of the nonvolatile memory device.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a circuit diagram illustrating a structure of a nonvolatile memory device.

2 is a circuit diagram illustrating a structure of a nonvolatile memory device according to an embodiment of the present invention.

3 is a potential graph illustrating an output voltage (control voltage) of the common source voltage generator of FIG. 2.

100: memory cell array 200: common source voltage generator

MC <0> to MC <31>: memory cells

Claims

A memory cell array including a string in which a plurality of memory cells are connected in series; And

And a common source voltage generator configured to output a source voltage to a source line connected to the string, wherein the source voltage is lower than a bit line potential of the string and gradually decreases to a ground voltage.

A plurality of memory cells connected in series between the bit line and the common source line;

A common source voltage generator configured to apply a source voltage to the common source line,

The common source voltage generator outputs the source voltage lower than the potential of the bit line and gradually lowered to the ground voltage to discharge the potential of the precharged bit line during the verify operation or the read operation of the device. device.

The method of claim 2,

And the bit line potential is 1V, and the source voltage starts at a potential of 0.9V and falls to the ground potential, but gradually decreases by a step voltage.

The method of claim 2,

And the source voltage gradually decreases by 0.1V.

Precharging a bit line with a plurality of memory cells connected in series;

Applying a pass voltage to a plurality of non-selected memory cells of the plurality of memory cells, and applying a read voltage or a verify voltage to selected memory cells of the plurality of memory cells; And

A common source voltage is applied to a common source line connected in series with the plurality of memory cells to discharge the voltage of the precharged bit line.

And the common source voltage is lower than the bit line potential and gradually falls to the ground voltage.

The method of claim 5,

The common source voltage is

And a step lower than the potential of the bit line and sequentially lowered to the ground voltage by a step voltage to discharge the potential of the precharged bit line during the verify operation or the read operation.

The method of claim 6,

And said bit line potential is 1V and said source voltage starts at a potential of 0.9V and falls to said ground potential.

The method of claim 6,

And the step voltage is 0.1V.